dullard
Elite Member
- May 21, 2001
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I've always wondered, why do they bother with incomplete chips at the edges? Do they use them for design testing purposes?
BorisTheBlade82
Senior member
- May 1, 2020
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And according to the article it is also right at the reticle limit and therefore the maximum core count possible on a monolithic Intel7. This thing must be really expensive to produce.
Divide 60 fully functional Dies by about $9,000. At about $150 per die(being generous)
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No, they just throw them to the trash bin.
It's pretty wasteful process.
300mm Wafer = 70,695 mm^2
68 Complete Dies = 52,360 mm^2
60 Fully Functional dies = 46,620 mm^2
dullard
Elite Member
- May 21, 2001
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Why put them on the photoresist? That just leads to more etching and more chemical waste.
So if this is at 770 mm^2 their largest die ever Intel's engineers still haven't gone conservative to reduce risk as people were claiming (vis-à-vis the original 10nm process that shot too high and had to be scaled back)
Based on how many revisions it has gone through and how late it is, they need to learn that lesson.
Based on how many revisions it has gone through and how late it is, they need to learn that lesson.
Look what I just found...!!
Details for Genuine Intel CPU 0000%@32C/64T 1.7GHz, 900MHz/2.2GHz IMC, 32x 2MB L2, 90MB L3
The 90 MiB L3 per 32C would put this past the 1.875 limit of Sapphire Rapids Xeon Platinum and W9 models we have seen so far. Is this the Elusive Monolithic Design or Emerald Rapids?
I guess this one was not the Monolithic design I Had Hoped... Let see if Locuza can detect the exact amount of L3$ on that Monolithic Die pictured.
Look What I found guys.
Xeon Silver 4400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
4416+ 20-core / 40-thread 2.10-3.00GHz TDP165W
4410T 12-core / 24-thread 2.10-3.00GHz TDP145W
4410T 10-core / 20-thread 2.90-3.10GHz TDP150W
The strange 10 Core 20 Thread Sapphire Rapids makes it's debut in Sisoftware in 2S form..
Silver 4410T (10C 20T 2.7GHz/4GHz, 10x 2MB L2, 26.25MB L3)
Some Benchmarks of 60C/120T Sapphire Rapids-SP vs AMD EPYC 7763,
The funny part is, those are Zen 3 numbers. If Intel had opted not to create a hybrid CPU, but rather, had focused on efficiency, they would have had their own '5950x'. It would have been slightly worse thanks to a slightly worse process, lack of chiplets, and a garbage interconnect, but they could have sold people like me one thanks to sane power consumption.
I do happen to know for a fact Intel 7 does not cost Intel anywhere close to $9,000/wafer. Note that my number includes everything, including R&D. Intel's number for Intel 7 is close to half of your number, FWIW. I can't disclose much, but if you think I am wrong, just look at the 'margins' section of the earnings report. You, as an end user can easily calculate the number of dies per wafer, and therefore guess as to whether what I say is accurate. A typical split on a manufactured product is 33% manufacturer, 33% distributor, and 33% retailer FYI. Take from that what you may.
EDIT: I did want to add one thing here. I don't expect you to believe the above statement because I am a random internet person, but TSMC N7 originally launched at around 10 grand a wafer. Look at TSMC's margins and do the math from there if you don't. If you doubt the 10 grand number, just do some Googling. Intel's costs are lower than TSMC's, and total margin required is significantly less.
Good night.
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IntelUser2000
Elite Member
- Oct 14, 2003
- 8,686
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They said early in the days of semiconductors when everyone was trying to figure out things, by printing it all the way to the edge, it helps with yields on the whole wafer.
By not printing all the way to the edge, the new "edge" dies have increased defects.
Redirecting some conversations here. Better match for this threat than the Raptor Lake one.
I don't really care if someone makes a prediction that happens to be wrong. Part of the process. But once it's obvious that that prediction was, indeed, wrong, then the only sensible thing is to revise the assumptions that led to that prediction, rather than double down on them. Occam's razor, really. What's more likely - a whole bunch of professionals having no idea what they're doing, or someone on the internet being wrong?
I really don't see what's confusing about it. In the Angstronomics article, they pointed out that even with the lower wafer utilization, the MCC die still produces more cores than a wafer of XCC dies. The chiplet area overhead is really significant. And then add in the power, performance, and cost savings of monolithic, and it's an obvious choice for a design like SPR.
There's nothing magical about 18c, or any other number, that makes chiplets better. Taking the same mesh interface and going over EMIB (or any other advanced packaging) will always be worse than keeping that same interface on die.
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Not even remotely close to accurate in enterprise server space.
The IT/telco company i work for ( 400k ppl) buys direct from vendor , is a disty oursevles and also buys from other distys when it makes sense .
Hulk
Diamond Member
- Oct 9, 1999
- 5,138
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After the Rocket Lake fiasco Intel has come back from the dead with ADL and now only a year later RKL. I love that for the first time in a long time Intel and AMD are releasing competing products at the same time.
They are both at the same "starting line." Now it's going to be very interesting to see which one gets out the next update first. The competition is fantastic to watch.
They are both at the same "starting line." Now it's going to be very interesting to see which one gets out the next update first. The competition is fantastic to watch.
Interesting, but a very particular accelerator workload, so unfortunately not very generalizable.
DrMrLordX
Lifer
- Apr 27, 2000
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Unknown, since we don't know what would happen to yields on larger chips, though it does seem that Intel is now able to fab large dice on 10ESF. Or Intel 7 "super" as they call it now. It would leave less room for margins at the same price. Intel is a little pinched by transistor density and what may be a wasteful design in Golden Cove.
Fascinating. That die is huge, though it seems like they have better use of available silicon area there than in the Sapphire Rapids 400mm2 tiles. By a bit.
At least now we know that if they had wanted to do 16c Golden Cove Alder Lake, they probably could have.
We haven't seen that product yet, either. Plus, Amdahl's Law makes the e-core spam less desirable than some benchmarks might indicate.
inf64
Diamond Member
- Mar 11, 2011
- 3,884
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This chip should be very power efficient. 12900K's E cores draw between 5 and 6W so these lower clocked E cores can go even lower.
moinmoin
Diamond Member
- Jun 1, 2017
- 5,242
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I really hope this chip is optimized for efficiency instead pure frequency as on desktop. Then it should easily be the most efficient mobile ADL chip.
DrMrLordX
Lifer
- Apr 27, 2000
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Looks like the all-core clock in GB5 is ~3.2 GHz. That's much better than Alder Lake's 3.9 GHz for Gracemont (from a power efficiency standpoint).
Look at the System Cache of that Gracemont only CPU and compare it to the 13400 that was posted.
That's, uh, interesting if they are going to brand the 8 core Gracemonts as Core i3. I'd say the 2+4 i3 1210U is overall better.
HP HP ProBook Fortis 14 inch G10 Notebook PC - Geekbench
Benchmark results for a HP HP ProBook Fortis 14 inch G10 Notebook PC with an Intel Core i3-1210U processor.
browser.geekbench.com
That's a chip that turbos to 29W. That's likely going to affect battery life.
True but we don't know what the Gracemonts power ranges will be. Only that presumably the N305 is the higher power one.
Gracemont Cores were design for Die Area/Performance efficiency, specially on Integer Performance. They are efficient cores but that is not their main design goal.
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