Discussion Intel current and future Lakes & Rapids thread

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BorisTheBlade82

Senior member
May 1, 2020
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And according to the article it is also right at the reticle limit and therefore the maximum core count possible on a monolithic Intel7. This thing must be really expensive to produce.
 

nicalandia

Platinum Member
Jan 10, 2019
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And according to the article it is also right at the reticle limit and therefore the maximum core count possible on a monolithic Intel7. This thing must be really expensive to produce.
Divide 60 fully functional Dies by about $9,000. At about $150 per die(being generous)
 
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nicalandia

Platinum Member
Jan 10, 2019
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I've always wondered, why do they bother with incomplete chips at the edges? Do they use them for design testing purposes?
No, they just throw them to the trash bin.

It's pretty wasteful process.

300mm Wafer = 70,695 mm^2
68 Complete Dies = 52,360 mm^2
60 Fully Functional dies = 46,620 mm^2
 

dullard

Elite Member
May 21, 2001
24,192
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No, they just throw them to the trash bin.

It's pretty wasteful process.

300mm Wafer = 70,695 mm^2
68 Complete Dies = 52,360 mm^2
60 Fully Functional dies = 46,620 mm^2
Why put them on the photoresist? That just leads to more etching and more chemical waste.
 

Doug S

Golden Member
Feb 8, 2020
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So if this is at 770 mm^2 their largest die ever Intel's engineers still haven't gone conservative to reduce risk as people were claiming (vis-à-vis the original 10nm process that shot too high and had to be scaled back)

Based on how many revisions it has gone through and how late it is, they need to learn that lesson.
 

nicalandia

Platinum Member
Jan 10, 2019
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Look what I just found...!!

Details for Genuine Intel CPU 0000%@32C/64T 1.7GHz, 900MHz/2.2GHz IMC, 32x 2MB L2, 90MB L3


The 90 MiB L3 per 32C would put this past the 1.875 limit of Sapphire Rapids Xeon Platinum and W9 models we have seen so far. Is this the Elusive Monolithic Design or Emerald Rapids?
I guess this one was not the Monolithic design I Had Hoped... Let see if Locuza can detect the exact amount of L3$ on that Monolithic Die pictured.
 

nicalandia

Platinum Member
Jan 10, 2019
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◇ Xeon Platinum 8400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
  8490H 60-core / 120-thread 1.90-2.90GHz TDP350W
8480+ 56-core / 112-thread 2.00-3.00GHz TDP350W
  8471N 52-core / 104-thread 1.80-2.80GHz TDP300W
  8470Q 52-core / 104-thread 2.00-3.00GHz TDP350W
  8470N 52-core / 104-thread 1.70-2.70GHz TDP300W
  8470 52-core / 104-thread 2.00-3.00GHz TDP350W 8468V
  48- core / 96-thread 2.40-2.90GHz TDP330W
  8468H 48-core / 96-thread 2.10-3.00GHz TDP330W
  8468 48-core / 96-thread 2.10-3.00GHz TDP350W
  8461V 48-core / 96-thread 2.20-2.80GHz TDP300W
  8460Y + 40-core / 80-thread 2.00-2.80GHz TDP300W
  8460H 40-core / 80-thread 2.20-3.10GHz TDP350W
  8458P 44-core / 88-thread 2.70-3.20GHz TDP350W
  8454H 32-core / 64-thread 2.10-2.70GHz TDP270W
  8452Y 36-core / 72-thread 2.00-2.80GHz TDP300W
  8450H 28-core / 56-thread 2.00-2.60GHz TDP250W
  8444H 16-core / 32-thread 2.00-2.80 GHz TDP320W

◇ Xeon Gold 6400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
  6454Y + 32-core / 64-thread 2.60-3.80GHz TDP270W
  6454S 32-core / 64-thread 2.20-2.80GHz TDP270W
  6448Y 32-core /64-thread 2.20-3.30GHz TDP225W
  6448H 32-core / 64-thread 2.20-3.82GHz TDP225W
  6444Y 16-core / 32-thread 3.50-4.10GHz TDP270W
  6442Y 24-core / 48-thread 2.60-3.00GHz TDP225W
  6441V 44 -core / 88-thread 2.10-2.60GHz TDP270W
  6438Y + 32-core / 64-thread 1.90-2.10-3.00GHz TDP205W
  6438N 32-core / 64-thread 2.00-3.00GHz TDP205W
  6438M 32-core / 64-thread 2.30-3.10GHz TDP205W
  6434H 8-core / 16-thread 4.00-4.10GHz TDP205W
  6434 8-core / 16-thread 3.90-4.20GHz TDP270W
  6430 32-core / 64-thread 1.90-3.00 GHz TDP270W
  6428N 32-core / 64-thread 1.80-2.70GHz TDP185W
  6426Y 16-core / 32-thread 2.60-3.50GHz TDP185W
  6421N 32-core / 64-thread 1.80-2.70GHz TDP185W
  6418H 24-core / 48-thread 2.00 -3.00GHz TDP185W
  6416H 18-core / 36-thread 2.20-3.00GHz TDP165W
  6414U 32-core / 64-thread 2.00-2.60GHz TDP250W

◇ Xeon Gold 5400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
  5420+ 28-core / 56-thread 1.90-2.10GHz TDP205W
  5418Y 24-core / 48-thread 2.10-2.90GHz TDP185W
  5418N 24-core / 48-thread 2.00-2.80GHz TDP165W
  5416S 16-core / 32-thread 2.10-2.90GHz TDP150W
  5415+ 8-core / 16-thread 2.90-3.70GHz TDP150W
  5411N 24-core / 48-thread 2.00-2.80GHz TDP165W

◇ Xeon Silver 4400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
  4416+ 20-core / 40-thread 2.10-3.00GHz TDP165W
  4410T 12-core / 24-thread 2.10-3.00GHz TDP145W
  4410T 10-core / 20-thread 2.90-3.10GHz TDP150W

◇ Xeon Bronze 3400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
  3408U 8-core / 16-thread 1.80-1.90GHz TDP125W

Look What I found guys.
Xeon Silver 4400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
  4416+ 20-core / 40-thread 2.10-3.00GHz TDP165W
  4410T 12-core / 24-thread 2.10-3.00GHz TDP145W
  4410T 10-core / 20-thread 2.90-3.10GHz TDP150W

The strange 10 Core 20 Thread Sapphire Rapids makes it's debut in Sisoftware in 2S form..

Silver 4410T (10C 20T 2.7GHz/4GHz, 10x 2MB L2, 26.25MB L3)


1664409696930.png
 

eek2121

Platinum Member
Aug 2, 2005
2,212
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According to Computerbase, GC P-core consumes 21W at 4.9Ghz : https://www.computerbase.de/2021-11/intel-core-i9-12900k-i7-12700k-i5-12600k-test/2/
They also found that E-Core under full load consumes between 5 and 6 watts.

So if they opted to create a monolithic 16 P-core part, it would had to be clocked much lower (my guess ~11 to 15%) to keep it under the same 241W limit. 12900K with E cores is about 30% faster than without E cores (see here). Since Ryzens gain between 65 and 75% going from 8 to 16 cores in MT scenarios (average, see here for 7700X/7950X and 5800X/5950X), my guess is that 16 P core part (with ~10% clock regression and 241W limit) would have performed around ~18-21% faster than 12900K (stock) in MT.

Intel actually did good with 13900K, as they claim to get "up to" 41% better MT performance vs 12900K which is around 17-19% better than a hypothetical 16 P core part based on Golden Cove. They will most likely still lose the MT crown but they are going to be much closer to 7950X versus the hypothetical 16 P part.
The funny part is, those are Zen 3 numbers. If Intel had opted not to create a hybrid CPU, but rather, had focused on efficiency, they would have had their own '5950x'. It would have been slightly worse thanks to a slightly worse process, lack of chiplets, and a garbage interconnect, but they could have sold people like me one thanks to sane power consumption.
Divide 60 fully functional Dies by about $9,000. At about $150 per die(being generous)
I do happen to know for a fact Intel 7 does not cost Intel anywhere close to $9,000/wafer. Note that my number includes everything, including R&D. Intel's number for Intel 7 is close to half of your number, FWIW. I can't disclose much, but if you think I am wrong, just look at the 'margins' section of the earnings report. You, as an end user can easily calculate the number of dies per wafer, and therefore guess as to whether what I say is accurate. A typical split on a manufactured product is 33% manufacturer, 33% distributor, and 33% retailer FYI. Take from that what you may.

EDIT: I did want to add one thing here. I don't expect you to believe the above statement because I am a random internet person, but TSMC N7 originally launched at around 10 grand a wafer. Look at TSMC's margins and do the math from there if you don't. If you doubt the 10 grand number, just do some Googling. Intel's costs are lower than TSMC's, and total margin required is significantly less.

Good night.
 
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IntelUser2000

Elite Member
Oct 14, 2003
8,518
3,567
136
Why put them on the photoresist? That just leads to more etching and more chemical waste.
They said early in the days of semiconductors when everyone was trying to figure out things, by printing it all the way to the edge, it helps with yields on the whole wafer.

By not printing all the way to the edge, the new "edge" dies have increased defects.
 

Exist50

Golden Member
Aug 18, 2016
1,404
1,472
136
Redirecting some conversations here. Better match for this threat than the Raptor Lake one.
Regarding the former argument about whether the rumors of the monolithic chip are true or not...
<snip>
I don't really care if someone makes a prediction that happens to be wrong. Part of the process. But once it's obvious that that prediction was, indeed, wrong, then the only sensible thing is to revise the assumptions that led to that prediction, rather than double down on them. Occam's razor, really. What's more likely - a whole bunch of professionals having no idea what they're doing, or someone on the internet being wrong?
I am kind of perplexed on the design choice since Huge Monolithic CPUs were believed to be a thing of the past.
I really don't see what's confusing about it. In the Angstronomics article, they pointed out that even with the lower wafer utilization, the MCC die still produces more cores than a wafer of XCC dies. The chiplet area overhead is really significant. And then add in the power, performance, and cost savings of monolithic, and it's an obvious choice for a design like SPR.
Up to certain amount of CPU cores yes... But that is no longer the case when you cross the 18 Core CPU barrier. You can bet that those monolithic CPUs will have Subnuma domains(to alleviate the latencies of such large Mesh), the power consumption on such large mesh is significant too.
There's nothing magical about 18c, or any other number, that makes chiplets better. Taking the same mesh interface and going over EMIB (or any other advanced packaging) will always be worse than keeping that same interface on die.
 
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itsmydamnation

Platinum Member
Feb 6, 2011
2,423
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. A typical split on a manufactured product is 33% manufacturer, 33% distributor, and 33% retailer FYI. Take from that what you may.
Not even remotely close to accurate in enterprise server space.
The IT/telco company i work for ( 400k ppl) buys direct from vendor , is a disty oursevles and also buys from other distys when it makes sense .
 

Hulk

Diamond Member
Oct 9, 1999
3,575
1,173
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After the Rocket Lake fiasco Intel has come back from the dead with ADL and now only a year later RKL. I love that for the first time in a long time Intel and AMD are releasing competing products at the same time.

They are both at the same "starting line." Now it's going to be very interesting to see which one gets out the next update first. The competition is fantastic to watch.
 

DrMrLordX

Lifer
Apr 27, 2000
20,297
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What would the manuf costs have been and the price to hold margins?
Unknown, since we don't know what would happen to yields on larger chips, though it does seem that Intel is now able to fab large dice on 10ESF. Or Intel 7 "super" as they call it now. It would leave less room for margins at the same price. Intel is a little pinched by transistor density and what may be a wasteful design in Golden Cove.

well you asked and Skyjuice of Angstronomics fame delivered.
Fascinating. That die is huge, though it seems like they have better use of available silicon area there than in the Sapphire Rapids 400mm2 tiles. By a bit.

This is sounding like a broken record, repeating the same thing over and over again.
At least now we know that if they had wanted to do 16c Golden Cove Alder Lake, they probably could have.

If you can fit 16P cores, then you can do 8P cores and 32E cores for even better performance.
We haven't seen that product yet, either. Plus, Amdahl's Law makes the e-core spam less desirable than some benchmarks might indicate.
 

moinmoin

Diamond Member
Jun 1, 2017
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This chip should be very power efficient. 12900K's E cores draw between 5 and 6W so these lower clocked E cores can go even lower.
I really hope this chip is optimized for efficiency instead pure frequency as on desktop. Then it should easily be the most efficient mobile ADL chip.
 

DrMrLordX

Lifer
Apr 27, 2000
20,297
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I really hope this chip is optimized for efficiency instead pure frequency as on desktop. Then it should easily be the most efficient mobile ADL chip.
Looks like the all-core clock in GB5 is ~3.2 GHz. That's much better than Alder Lake's 3.9 GHz for Gracemont (from a power efficiency standpoint).
 
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jpiniero

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nicalandia

Platinum Member
Jan 10, 2019
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I really hope this chip is optimized for efficiency instead pure frequency as on desktop. Then it should easily be the most efficient mobile ADL chip.
Gracemont Cores were design for Die Area/Performance efficiency, specially on Integer Performance. They are efficient cores but that is not their main design goal.
 
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nicalandia

Platinum Member
Jan 10, 2019
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Look What I found guys.
Xeon Silver 4400 (Sapphire Rapids-SP / Intel 7 / LGA4766 / 8ch DDR5)
  4416+ 20-core / 40-thread 2.10-3.00GHz TDP165W
  4410T 12-core / 24-thread 2.10-3.00GHz TDP145W
  4410T 10-core / 20-thread 2.90-3.10GHz TDP150W

The strange 10 Core 20 Thread Sapphire Rapids makes it's debut in Sisoftware in 2S form..

Silver 4410T (10C 20T 2.7GHz/4GHz, 10x 2MB L2, 26.25MB L3)


View attachment 68394
Not sure if you Guys saw this....

Those 10C/20T CPUs(on 2S System) are 100% Monolithic in nature You can't divide 10 cores on 4 tiles. Likely they have built a smaller Monolithic die for smaller core size Sapphire Rapids


Also. Credit to YuuKi_AnS for leaking the entire line, he was Spot On(at first I did not believe that Intel was actually going to release a Monolithic 10C/20T SPR-SP, but he proved me wrong)
 
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