Discussion Intel current and future Lakes & Rapids thread

[coercitiv]

What happens if some Zen 4 CPUs can't run their IF at 2ghz due to instability?

The same thing that happens when Alder Lake or Raptor Lake can't run high frequencies that media showcases in reviews. Even you asked for Alder Lake to be tested with DDR5 6400 CL32 though you had no idea on the reliability of such settings on a wide range of ADL silicon.

FYI Alder Lake DDR4 IMC was a hit or miss when attempting to run DDR4 3600+ DR even in 2 DIMM configs. The funniest example I can think of was Buildzoid realizing his 12600K had a much better IMC than his 12900K sample. He could run 4000+ on the first, but was stuck bellow 4000 on the flagship silicon while using the same motherboard and same memory sticks.

Relax a bit, and please stop with the FUD. We have 2 nice CPU launches and we'll have ample time to compare both products inside and out, including overclocking reliability.

 

[DrMrLordX]

Software Defined Silicon

. . .

No news on SPR-X for Workstations

SDSI sure sounds like a money grab, which is awkward considering how long it is taking Intel to even bring Sapphire Rapids to market, in ANY form.

 

[Timmah!]

Intel's 34-Core Raptor Lake-S CPU Die Shown Off, Hinting At Possible HEDT Launch

A 34-Core and unreleased Intel Raptor Lake-S Desktop CPU die has been spotted over at Innovation 2022 event, hinting at a HEDT launch.

wccftech.com

right when i was definitely decided to go with Zen4
that said, i realized i dont really want to spend more than 7950x costs, and 34C from Intel will be surely like 3x that much.

 

[DrMrLordX]

So Intel can do a 34c Raptor Cove die for HEDT, but they can't do 12-16c Raptor Cove for consumer desktop? Wtf Intel.

 

[inf64]

So Intel can do a 34c Raptor Cove die for HEDT, but they can't do 12-16c Raptor Cove for consumer desktop? Wtf Intel.

Imagine the power draw on this 34C workstation part. If 13900K with E cores can draw up to 350W (unlimited) then I doubt they could ran a native 16C big core part at decent clocks in MT workloads and remain within 241W envelope.

 

[Kocicak]

Those P cores are powerfull and also power hungry monsters. Having 8 of them in a consumer CPU is enough.

 

[inf64]

Those P cores are powerfull and also power hungry monsters. Having 8 of them in a consumer CPU is enough.

Having 16 big cores is better in consumer CPU but intel can't do it on their current node. If they could, they would

 

[Timmah!]

Imagine the power draw on this 34C workstation part. If 13900K with E cores can draw up to 350W (unlimited) then I doubt they could ran a native 16C big core part at decent clocks in MT workloads and remain within 241W envelope.

Thats because its clocked to the blood, way beyond its optimum. With 34C you can clock them at maybe at 3,5~4 GHz and draw maybe less than 13900 does, while still scoring significantly more in MT. And then have maybe with 2 cores active boost up to 6GHz, 4core 5,5GHz, 8 cores 5GHz and step down. Usual business.

 

[DrMrLordX]

Thats because its clocked to the blood, way beyond its optimum. With 34C you can clock them at maybe at 3,5~4 GHz and draw maybe less than 13900 does, while still scoring significantly more in MT. And then have maybe with 2 cores active boost up to 6GHz, 4core 5,5GHz, 8 cores 5GHz and step down. Usual business.

Thank you, that summarizes what I wanted to say more simply, at the very least.

Tbh Intel could have done this with Alder Lake OR Raptor Lake if they had just had the guts to sell a larger die with more Golden Cove/Raptor Cove. I don't know what kind of interconnect they would have used for the cores - having two separate core complexes with 6 or 8 P-cores each could have duplicated some of the interconnect and memory latency problems present on existing Alder Lake and (to a lesser extent, hopefully) Raptor Lake. But mesh might not be ideal for that sort of part either.

In any case, assuming Intel could get the interconnect right, Intel could have sold 16P Golden/Raptor cove parts on the consumer platform that hit the same ST and "sparsely threaded" clocks as Alder or Raptor without having to make compromises with a goofy scheduler or by crippling their P-cores by disabling AVX512. And they could just downclock Golden/Raptor cores in MT workloads to get them closer to their ideal efficiency range where Golden can be just as efficient as Gracemont. Not sure how many improvements there really have been to the soon-to-be-current iteration of Gracemont, or if Raptor Cove "keeps up" in terms of efficiency at ideal points in the voltage/clockspeed curve.

It remains to be seen how large this 34c HEDT monolithic die will be in comparison to the 400mm2 tiles of Sapphire Rapids. Should be interesting.

 

[inf64]

According to Computerbase, GC P-core consumes 21W at 4.9Ghz : https://www.computerbase.de/2021-11/intel-core-i9-12900k-i7-12700k-i5-12600k-test/2/
They also found that E-Core under full load consumes between 5 and 6 watts.

So if they opted to create a monolithic 16 P-core part, it would had to be clocked much lower (my guess ~11 to 15%) to keep it under the same 241W limit. 12900K with E cores is about 30% faster than without E cores (see here). Since Ryzens gain between 65 and 75% going from 8 to 16 cores in MT scenarios (average, see here for 7700X/7950X and 5800X/5950X), my guess is that 16 P core part (with ~10% clock regression and 241W limit) would have performed around ~18-21% faster than 12900K (stock) in MT.

Intel actually did good with 13900K, as they claim to get "up to" 41% better MT performance vs 12900K which is around 17-19% better than a hypothetical 16 P core part based on Golden Cove. They will most likely still lose the MT crown but they are going to be much closer to 7950X versus the hypothetical 16 P part.

 

[nicalandia]

So Intel can do a 34c Raptor Cove die for HEDT, but they can't do 12-16c Raptor Cove for consumer desktop? Wtf Intel.

Their 54 Core W9 has very low base clocks, and competitive with Zen3, the 34 Core is on the small size now a days..

 

[igor_kavinski]

Intel could also keep power under control by disabling hyperthreading. Then they could release a K or X series chip that does have HT enabled but with the caveat that turning it on will void warranty. That would take care of power lusting enthusiasts burning their house down

https://www.computerbase.de/2021-11/intel-core-i9-12900k-i7-12700k-i5-12600k-test/2/

Excellent testing by them. My only complaint is that they didn't indicate anywhere if they tested with HT off so I'm assuming all of those figures are with HT enabled. Anyone know how much power a P-core consumes without HT?

 

[Timmah!]

According to Computerbase, GC P-core consumes 21W at 4.9Ghz : https://www.computerbase.de/2021-11/intel-core-i9-12900k-i7-12700k-i5-12600k-test/2/
They also found that E-Core under full load consumes between 5 and 6 watts.

So if they opted to create a monolithic 16 P-core part, it would had to be clocked much lower (my guess ~11 to 15%) to keep it under the same 241W limit. 12900K with E cores is about 30% faster than without E cores (see here). Since Ryzens gain between 65 and 75% going from 8 to 16 cores in MT scenarios (average, see here for 7700X/7950X and 5800X/5950X), my guess is that 16 P core part (with ~10% clock regression and 241W limit) would have performed around ~18-21% faster than 12900K (stock) in MT.

Intel actually did good with 13900K, as they claim to get "up to" 41% better MT performance vs 12900K which is around 17-19% better than a hypothetical 16 P core part based on Golden Cove. They will most likely still lose the MT crown but they are going to be much closer to 7950X versus the hypothetical 16 P part.

They clearly cant compete 16C vs 16C against 7950x, as they cant clock as high, without drawing significantly more power. They would need more cores, which could be allowed to run at lower clocks to compete in MT.
Obviously, for them its more viable to sell these hybrid chips, as they are smaller and cheaper to produce than 20C+ P cores designs, we as customers may not like it though.

 

[inf64]

They clearly cant compete 16C vs 16C against 7950x, as they cant clock as high, without drawing significantly more power. They would need more cores, which could be allowed to run at lower clocks to compete in MT.
Obviously, for them its more viable to sell these hybrid chips, as they are smaller and cheaper to produce than 20C+ P cores designs, we as customers may not like it though.

The problem with E cores is non-uniform ISA support and lower IPC/clocks in common desktop workloads. Skylake level IPC with half the AVX throughput is behind a lot when compared to Zen 4/ GC/RC. They will probably up the IPC in next Mont core along with clocks so that should mitigate the issue somewhat. I wonder how they will handle AVX512 support as it's not going away, not now that AMD has it across the board and it brings tangible uplifts when supported.

 

[Atari2600]

Tbh Intel could have done this with Alder Lake OR Raptor Lake if they had just had the guts to sell a larger die with more Golden Cove/Raptor Cove.

What would the manuf costs have been and the price to hold margins?

 

[Carfax83]

The same thing that happens when Alder Lake or Raptor Lake can't run high frequencies that media showcases in reviews. Even you asked for Alder Lake to be tested with DDR5 6400 CL32 though you had no idea on the reliability of such settings on a wide range of ADL silicon.

Yes but Alder Lake isn't validated to run at higher memory frequencies than DDR5 4800.

This has happened to me several times in the past where I've bought an overclocked memory kit thinking it would work with a CPU at the advertised speed and timings only to have it be unstable.

That's one of the reasons why I intentionally didn't purchase an Alder Lake CPU because I knew that Raptor Lake's memory controller would be far superior as a refresh product.

My 5930K couldn't run my DDR4 3200 kit at DDR4 3400 speeds no matter how many volts I pumped into the uncore voltage but my 6900K could do it with no problem and with less voltage and more aggressive timings than the 5930K could at DDR4 3200.

Broadwell E's memory controller also fixed a write performance issue that Haswell E had, as Haswell E was Intel's first DDR4 memory controller and it had some issues. After that experience, I vowed to only buy refresh cycle CPUs.

Relax a bit, and please stop with the FUD. We have 2 nice CPU launches and we'll have ample time to compare both products inside and out, including overclocking reliability.

Dude, it's not like I'm burning down the forums about this issue. I just commented on it because I found it odd that AMD would deviate from well established policies concerning product launch review criteria.

I wouldn't be surprised if some idiot tries to file a class action lawsuit against them because his Zen 4 CPU can't use DDR5 6000 with the "optimal" configuration, that being IFCK at 2ghz and the memory clock and uncore running at 3ghz.

 

[inf64]

I wouldn't be surprised if some idiot tries to file a class action lawsuit against them because his Zen 4 CPU can't use DDR5 6000 with the "optimal" configuration, that being IFCK at 2ghz and the memory clock and uncore running at 3ghz.

AMD claims that all Expo supporting modules will run out of the box at the preset Expo settings (provided bios support of course). If some idiot tries to run it by manually tuning bios settings out of the Expo spec cannot result in a lawsuit (unless the idiot is willing to lose a lot of money).

 

[nicalandia]

New entry for a 2S 32C/64T(64C/128T Total) Intel Sapphire Rapids-SP.

Details for Result ID 2x Genuine Intel CPU 0000% 32C 64T 2.2GHz/3.9 GHz , 32x 2 MiB L2, 60 MiB L3

Details for Result ID 2x Genuine Intel(R) CPU 0000%@ (32C 64T 2.2千兆赫（GHz）/3.9千兆赫（GHz）, 32x 2兆字节（MB） L2, 60兆字节（MB） L3)

ranker.sisoftware.co.uk

 

[coercitiv]

Yes but Alder Lake isn't validated to run at higher memory frequencies than DDR5 4800.

On the day of the 7000 series reveal you were not concerned about memory validation, instead you wanted Alder Lake to be pushed "optimally" even further:

DDR5 6000 in a 1:1 ratio with Zen 4s IF speed is optimal for Zen 4 but not the 12900K. The 12900K would have been better coupled with DDR5 6400 CL32 in gear 2.

If you advocate for vendor benchmarks at validated memory speeds, that's fine by me, there's a handful of sites that test at validated JEDEC speeds, including Anandtech and Computerbse. If you want optimum overclocks on both platforms, fine as well, most reviewers today are expected to use mild memory overclocks anyway. Hardware Unboxed tested Zen 4 with DDR5 6000 because they were asked so by AMD, but used DDR5 6400 for Alder Lake. Ironically they would have tested DDR5 6400 on Zen 4 as well if it weren't for vendor recommendation. (they did and kept the info out of the main graphs).

Dude [...]
I wouldn't be surprised if some idiot tries to file a class action lawsuit against them because his Zen 4 CPU can't use DDR5 6000 with the "optimal" configuration, that being IFCK at 2ghz and the memory clock and uncore running at 3ghz.

Dude, both XMP and EXPO are considered overclocks by Intel and AMD, and they technically void warranties.

 

[Carfax83]

On the day of the 7000 series reveal you were not concerned about memory validation, instead you wanted Alder Lake to be pushed "optimally" even further:

Because I had no idea that AMD was going to do official release benchmarks using out of spec memory!

Whatever you might think, you have to admit this is without precedent.

My argument was simple, if they are going to go that far, why stop at 6000mhz? Intel can use and benefit from faster memory frequencies than AMD due to using gear 2 and having a more integrated memory controller.

This is why official launch reviews should use validated memory only, or add higher memory frequencies in conjunction with stock but under OC so that people know this doesn't represent stock performance.

The latter is more preferable actually and that is what many reviewers do of their own accord.

Hardware Unboxed tested Zen 4 with DDR5 6000 because they were asked so by AMD, but used DDR5 6400 for Alder Lake. Ironically they would have tested DDR5 6400 on Zen 4 as well if it weren't for vendor recommendation. (they did and kept the info out of the main graphs).

Yes I saw that. HWU is usually my first go to for reviews, as well as Computerbase.de.

Dude, both XMP and EXPO are considered overclocks by Intel and AMD, and they technically void warranties.

It's not just memory and the memory controller that's being overclocked though, you have the infinity fabric which is ostensibly more difficult to deal with. This is why Zen 4 will likely never use memory frequencies higher than DDR5 6400 because the CPU takes a penalty running in gear 2 mode and the IF can only go so high.

 

[Curious_Inquirer]

It remains to be seen how large this 34c HEDT monolithic die will be in comparison to the 400mm2 tiles of Sapphire Rapids. Should be interesting.

well you asked and Skyjuice of Angstronomics fame delivered.
https://www.angstronomics.com/p/monolithic-sapphire-rapids

Using a handy image captured by David Altavilla, we can do some image processing to derive the die size of this massive chip. From our edited image, we find a die size around the 770 mm² mark. This makes it Intel’s largest die ever!
2010 Tukwila: 699 mm²
2016 Knights Landing: 683 mm²
2017 Skylake-XCC: 678 mm²
2023 Sapphire Rapids-MCC: 770 mm²

what a Colossal chip Intel has been constructing to finally have some presence in the HEDT/Workstation market.

 

[nicalandia]

well you asked and Skyjuice of Angstronomics fame delivered.
https://www.angstronomics.com/p/monolithic-sapphire-rapids

Single 34C/68T die is about 30.8mm x 25.2mm and a single compute tile is about 20mm x 20mm

 

[Saylick]

Single 34C/68T die is about 30.8mm x 25.2mm and a single compute tile is about 20mm x 20mm

View attachment 68380

Seems like they could have fit in 2 more dies at the right side of the wafer if they just shifted the pattern slightly to the left.

 

[IntelUser2000]

So Intel can do a 34c Raptor Cove die for HEDT, but they can't do 12-16c Raptor Cove for consumer desktop? Wtf Intel.

Yea, but that part is 770mm2.

This is sounding like a broken record, repeating the same thing over and over again.

If you can fit 16P cores, then you can do 8P cores and 32E cores for even better performance. With 8+16 you get the advantage(little more) while being significantly smaller.

Seems like they could have fit in 2 more dies at the right side of the wafer if they just shifted the pattern slightly to the left.

No, you need bit of room at the edges. It helps with yield.

 

[dullard]

No, you need bit of room at the edges. It helps with yield.

I've always wondered, why do they bother with incomplete chips at the edges? Do they use them for design testing purposes?