But with HEDT pricing. 16c core RKL requires an abysmal die size(8c = 264sqmm). 16c RKL cannot be in the desktop chip league due to massive costs.
Dayman1225
Golden Member
- Aug 14, 2017
- 1,081
- 791
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Looks like even the AMD patch didn’t help..
No. Using 12400 CPUz I come up with 34%.
Check me here.
ST score 682 @4.4GHz, MT score 4984 @4ghz.
(4984/6)(4.4/4)=914 (Single core score @ 4.4GHz)
~34%
yeah, seems high
I've seen a few places test pre and post patch and they all showed the same or better performance, averaging around 10-12%. So it will be interesting to see their results. It's hard to imagine the performance getting worse if the L3 latency patch is actually working as shown by others.
This is the most disgustingly deceiving slide in their whole presentation. The RKL team must be fuming.This looks promising and I would like the coming reviews to take a look at it.
From Ian's article today:
"For regular users, Intel is also offering a one-click immediate overclock feature. On launch, the Core i9 will be supported and overclock the P-cores +100 MHz and the E-cores +300 MHz immediately. It sounds like Intel is confident that all CPUs will be able to do this, but they want it to be user selectable."
Does this mean with the 12900K the Coves will go all-core to 5.2GHz and preferred cores to 5.3GHz out of the box?
More importantly does this mean the Gracemonts will go from 3.9GHz to 4.2GHz out of the box?
Assuming adequate power and cooling of course. This seems to imply that the Coves are already clocked to within an inch of their lives while the Monts have a bit more headroom built in.
"For regular users, Intel is also offering a one-click immediate overclock feature. On launch, the Core i9 will be supported and overclock the P-cores +100 MHz and the E-cores +300 MHz immediately. It sounds like Intel is confident that all CPUs will be able to do this, but they want it to be user selectable."
Does this mean with the 12900K the Coves will go all-core to 5.2GHz and preferred cores to 5.3GHz out of the box?
More importantly does this mean the Gracemonts will go from 3.9GHz to 4.2GHz out of the box?
Assuming adequate power and cooling of course. This seems to imply that the Coves are already clocked to within an inch of their lives while the Monts have a bit more headroom built in.
Having had the Windows 11 issue locally, and using the patch the day it was released, I can tell you that in 99% of workloads, it was more like 3-4%. In a few select workloads, it may reach 10%, and in the 2-3 workloads widely publicized, the gap was greater.
No, they are showing progress. Nothing deceiving about it.
A lot of people are losing their minds over the power. GC has higher IPC than Zen 3. That is pretty much a known fact (unless you think they regressed from Rocket Lake. We also know that Intel has set power limits through the roof to allow the highest end chips to compete with the multicore workloads of the 5900/5950x. We know little else beyond leaked benchmarks. I've no doubt the chip will pull tons of power (if allowed) for multicore workloads. I also have no doubt that Alder Lake is Intel's most efficient chip yet. That is basically all we know right now. Wait for the reviews.
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CHADBOGA
Platinum Member
- Mar 31, 2009
- 2,135
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What is the deal with DDR4 and DDR5 based motherboards for the launch of Alderlake?
Will both types be available at launch and will all Alderlake models run on either motherboard?
Some early adopters who are buying current DDR5 modules with modest clock speeds and high latencies, might end up looking pretty silly if cheaper DDR4 options of Alderlake are the faster systems.
Will both types be available at launch and will all Alderlake models run on either motherboard?
Some early adopters who are buying current DDR5 modules with modest clock speeds and high latencies, might end up looking pretty silly if cheaper DDR4 options of Alderlake are the faster systems.
blckgrffn
Diamond Member
I am betting that really good DDR4 is going to out perform the DDR5 systems for a while until the promised higher speed DDR5 sticks materialize, along with chipset support for them.
I mean, what is the latency on 4000 mhz+ DDR4 kits? Like CL20? Even CL18 on cursory NewEgg review. Given that it doesn't have some weird RKL like cutoff on the upper bounds of DDR4 this seems like a given.
DDR5 is going to bring the density, I guess.
This seems like a great time to wait an entire generation on the memory front if DDR4 is competitive, at least a high end kit of that might be worth something down the road. The current DDR5 is going to be like 2133 DDR4.
You didn't understand me - you rarely seem to do so 😆 it IS deceiving. The real power efficiency test would be if you'd have limited both chips (all PLs) to 65W and then show both scores. Surely, 8 low power cores on a much more efficient node will be more efficient. But come on it's NOWHERE NEAR 4 times as efficient. The slide is as deceiving as it can be, since it only shows how much power can a 11900K use if you let it.
If you ask me, with extra 8 small cores and on a much more efficient process, getting 50% more MT performance is pretty underwhelming after so much hype.
IntelUser2000
Elite Member
- Oct 14, 2003
- 8,578
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Where did you get the information from?
I don't think so as the backside shot of the CPU shows otherwise.
CPU-Z is bit of an outlier in terms of how much it benefits from HT. On an 11800H, the single core score at 4.6 GHz is around 610 points but scores about 779 points running two threads on a single core (the 7 other cores disabled in the bios), a 27% gain and more than you would see in Cinebench.
But comparing the leaked 12400 scores vs 6 core Tiger Lake at the same clock speeds, the 12400's performance advantage does grow a bit with more threads. In CB20, the 12400's advantage goes from 19% to 22% from one thread to 12, and CPUZ 17.01.64 from 15% to 20%.
A tweet from Andreas Schilling:
That test is pitting a 250w PL1 11900k against a 241w (&125w + 65w) PL1 12900k, why must power efficiency tests be arbitrarily set at 65w baselines instead of something else?
Because the 11900K wouldn't have 1/4 the score at 1/4 the power. They must NOT be pitted against each other at any points, it's a free world after all. The test itself is also not deceiving at all. The narrative on the slide is, and very much so. I also think that was exactly what I wrote.
No kidding, but the slide never implied that it would.
Are OEMs not allowed to compare power efficiency between products?
You wrote that the test was deceiving literally several posts up.
The narrative on the aforementioned slide says "Similar MT performance at 1/4 the power", which assuming the test is legitimate, would be an accurate claim from the numbers. Nothing on the slide claims "4x power efficiency" or 4x perf at iso-power as you implied.
AtenRa
Lifer
- Feb 2, 2009
- 13,835
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I dont thing so, there is nothing deceiving at all with this slide.
What the slide shows is that you get the TOP performance at PL2 250W of last year chip at 1/4 the power this year (power at iso perf).
It also shows you that at iso PL2 power you get 55% efficiency (50% more performance at 241W vs 250W)
Yes it doesnt show the efficiency at 65W iso between the two chips but that doesnt make it deceiving.
Here’s some info. Looks like a de-lid has been done.
Andreas Schilling (@aschilling) / Twitter
Hm...Now we can actually see the size of Gracemont clusters. The effective area used per Gracemont core is almost 1/3 of Golden Cove. It seems that further layout optimization might reduce dark silicon there or might give Gracemont more L3 cache memory(breaking symmetry)?
Hm...Now we can actually see the size of Gracemont clusters. The effective area used per Gracemont core is almost 1/3 of Golden Cove. It seems that further layout optimization might reduce dark silicon there or might give Gracemont more L3 cache memory(breaking symmetry)?
AFAIK, The size of Tiger Lake H 32EU was like ~190mm2. Sounds like an ADL-P is a real deal. Almost the same die size, similar manufacturing process but much more powerful and power-efficient. Tiger Lake H wasn't that bad either BTW.
AtenRa
Lifer
- Feb 2, 2009
- 13,835
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Hell from the picture it seams the P-cores take an enormous die size since the 10 core 14nm Core i9 10900K has the same die size as the 10nm 12900K with just 8+8 cores.
Not particularly, 8C GC cluster with 24MB L3 is "only" around 10% larger than 8C TKL with 24MB L3, way smaller than Rocket Lake by any measure.
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