Discussion Intel current and future Lakes & Rapids thread

[jpiniero]

"flogging good ol 14nm for all it's worth"...

It's going to be fine for chipsets for the next few years, of course. If Intel decided to do a sort of "half Rocket Lake" part for low end products, they could probably get good mileage out of it in a late 11th gen i3/Celeron/Pentium stack, and even push a mild update into 12th gen for Celeron and Pentium. That's enough for a couple of years worth of product at least.

There is talk about the small 6+0 Alder Lake die being cancelled and replaced by Rocket Lake. Which would be i3 and below. Depending on the core count, they could maybe do the lower end i5 too. This would be on LGA 1700 presumably.

 

[eek2121]

"flogging good ol 14nm for all it's worth"...

It's going to be fine for chipsets for the next few years, of course. If Intel decided to do a sort of "half Rocket Lake" part for low end products, they could probably get good mileage out of it in a late 11th gen i3/Celeron/Pentium stack, and even push a mild update into 12th gen for Celeron and Pentium. That's enough for a couple of years worth of product at least.

14nm would be fine if they weren't continually turning the dial up to 11 when it comes to power usage on 14nm products.

 

[maddie]

14nm would be fine if they weren't continually turning the dial up to 11 when it comes to power usage on 14nm products.

Strange statement. Why do you think they do as they do?

 

[Abwx]

Intel has stated a greater than 2X improvement in density vs. 10nm. We will see.

Intel s 10nm has 100M/mm2 transistors density while TSMC 7FF+ is at 113M/mm2, that s 15-20% better that their first 7nm iteration.

TSMC s 5nm is at a theorical 175M/mm2 and expect a 5nm+ to provide the same density gain as above and thus get to 200M/mm2.

That being said that s max density for some parts of a chip, in practice their 5nm is at 130M/mm2 in Apple s SoC, so expect a comparable limitation for Intel s 7nm once it is used in real chips.

 

[Saylick]

Intel s 10nm has 100M/mm2 transistors density while TSMC 7FF+ is at 113M/mm2, that s 15-20% better that their first 7nm iteration.

TSMC s 5nm is at a theoretical 175M/mm2 and expect a 5nm+ to provide the same density gain as above and thus get to 200M/mm2.

That being said that s max density for some parts of a chip, in practice their 5nm is at 130M/mm2 in Apple s SoC, so expect a comparable limitation for Intel s 7nm once it is used in real chips.

AMD only gets about 50 MT/mm2 for the Zen 2/3 CCD and Navi 21, but both of these die have a significant portion of the die as cache. Navi 10 is closer to 40 MT/mm2. I'd expect these numbers to get closer to 80 MT/mm2 when they move to N5P, a far cry from the published max densities. A mobile-oriented die like the ones Apple designs will naturally be closer to the published max density due to the more prolific use of denser libraries. I'd expect Intel to be more in line with AMD for the densities they can reasonably achieve, and less so if they go with designs that have a smaller cache-to-logic ratio. With that said, cache scales less easily than logic these days so AMD might keep the cache amount the same and add more logic for their future designs.

 

[Hulk]

Intel can certainly be very competitive/lead again. But it will require a leadership course change from marketing/finance/short-term "paper profits" as a priority to leading edge technology as a priority. They have fabs and billions of dollars so it CAN be done.

The marketing guys will fight this. The older guys who want to grab as much money as possible before leaving will fight this. And the finance guys fighting to show growth from quarter-to-quarter will fight this. It's a long-term strategy not well-suited for giant corporations with thousands of independently moving tentacles. It will require a firm hand at the top to accomplish.

Seems to me like they have too many pilots trying to steer the ship.

 

[IntelUser2000]

In a previous post, I had this.
2023 production for nodes using EUV
TSMC = 370 Kwpm
Intel = 20 Kwpm

You know pretty much the only volume 7nm chip in 2023 will be Meteor Lake right? Ponte Vecchio only needs to be made in miniscule numbers to win few contracts. I'd be really worried if that's the 2024 number, but it's not. Meteor Lake is a very late 2023, early 2024 product.

TSMC's number includes 7nm as well, and 6, and 5, most of which need EUV. None of Intel's products until 7nm requires EUV. ZERO.

They said they got it fixed recently and I believe them. I remember the "10nm is in trouble" belief went as so far as saying they'll never ever deliver it. Because beliefs are not logical and always swing from one extreme to the other. I also knew that Intel was pushing the technical boundaries not just process-wise, but by skipping a pipe-cleaner entirely and going for a complex chip like Icelake.*

But they eventually did deliver a pipe-cleaner. The limited Cannonlake parts. No matter what you put on paper, how much you discuss among the engineers, nothing, I mean nothing compares to real world experience. Soon after CNL was delivered a functional 10nm was delivered in the product known as Icelake.

And they do have pipecleaners on 7nm. Ponte Vecchio and the RISC-V parts.

*That was the whole point behind Tick Tock. And it gets harder so you need proper simple chips to work out the kinks. I don't mean in the labs, but in products to actual customers.

 

[LightningZ71]

14nm would be fine if they weren't continually turning the dial up to 11 when it comes to power usage on 14nm products.

But that's just it, they won't need to do that with Celeron, Pentium and i3. They can afford to dial back the clocks a little and, as a result, tweak the node rules slightly to take better advantage of the more modest clock goals.

 

[Exist50]

You know pretty much the only volume 7nm chip in 2023 will be Meteor Lake right?

That, I wonder about. Isn't Granite Rapids supposed to be 7nm in 2023? Because all of the alternative situations would be disastrous for their server biz. Even 2023 is late when it'll realistically be competing against Genoa (2022) and almost certainly beaten by Genoa's successor in ~2023-24.

 

[coercitiv]

I remember the "10nm is in trouble" belief went as so far as saying they'll never ever deliver it. Because beliefs are not logical and always swing from one extreme to the other. I also knew that Intel was pushing the technical boundaries not just process-wise, but by skipping a pipe-cleaner entirely and going for a complex chip like Icelake.*

Agree with one caveat: there was also the counter-belief that they would fix it fast. With every new product announcement "10nm is fixed" was back on the forum, only to be shut down by availability or performance numbers. Happened with ICL mobile, early ICL server announcements, happened with TGL hype. I felt like Shrek repeatedly hearing Donkey from the back seat: Did they fix it yet?!?!.

Intel lied one too many times about 10nm and now people expect the worst of them in the absence of good news. This won't change until they start delivering the goods on time again.

 

[mohit9206]

Can someone explain me a bit about Alder Lake as I'm quite confused. Is Alder Lake the successor of Tiger Lake or Jasper Lake?
Like I see some cheap $300-400 laptops have Pentium N6000 which is Jasper Lake, so can Alder Lake be expected in these low budget laptops? Or it will also be on desktops anf gaming laptops as Tiger Lake successor as 12th gen Core i3, i5 and i7?

 

[exquisitechar]

Can someone explain me a bit about Alder Lake as I'm quite confused. Is Alder Lake the successor of Tiger Lake or Jasper Lake?
Like I see some cheap $300-400 laptops have Pentium N6000 which is Jasper Lake, so can Alder Lake be expected in these low budget laptops? Or it will also be on desktops anf gaming laptops as Tiger Lake successor as 12th gen Core i3, i5 and i7?

It's the TGL successor.

 

[lobz]

Intel 7nm will almost certainly leapfrog TSMC N5 but fall short of N3. We can expect the first volume products on TSMC N3 to be announced in Sep or Oct 2022, and Intel to launch Meteor Lake somewhere in the Aug 2023 - Apr 2024 range, so roughly a year later.

Even if yields are within reason at this point, the heavy use of multi-patterning for Intel 10nm most likely results in brutal cycle times which would make it a perpetually low-margin node. I would imagine Intel wants to move all of their 10nm products to 7nm ASAP while continuing to flog good ole' 14nm for all it's worth. 10nm will probably live on at Fab 28 and Fab 42 in some capacity though, while D1X (including the new Mod 3) and Fab 34 (or whatever they're calling the new one in Leixlip) will be the first on 7nm. Kiryat Gat will probably get EUV equipment to fit out their allegedly underway $11B expansion, followed by Chandler, but those projects are still at least a few years out (as in there's no way they would be ready for HVM prior to 2024).

I wanted to concur but you did it yourself in the same sentence. I mean, leapfrogging is really hard when there's an even bigger obstacle right where you wanted to land.

 

[lobz]

You know pretty much the only volume 7nm chip in 2023 will be Meteor Lake right? Ponte Vecchio only needs to be made in miniscule numbers to win few contracts. I'd be really worried if that's the 2024 number, but it's not. Meteor Lake is a very late 2023, early 2024 product.

TSMC's number includes 7nm as well, and 6, and 5, most of which need EUV. None of Intel's products until 7nm requires EUV. ZERO.

They said they got it fixed recently and I believe them. I remember the "10nm is in trouble" belief went as so far as saying they'll never ever deliver it. Because beliefs are not logical and always swing from one extreme to the other. I also knew that Intel was pushing the technical boundaries not just process-wise, but by skipping a pipe-cleaner entirely and going for a complex chip like Icelake.*

But they eventually did deliver a pipe-cleaner. The limited Cannonlake parts. No matter what you put on paper, how much you discuss among the engineers, nothing, I mean nothing compares to real world experience. Soon after CNL was delivered a functional 10nm was delivered in the product known as Icelake.

And they do have pipecleaners on 7nm. Ponte Vecchio and the RISC-V parts.

*That was the whole point behind Tick Tock. And it gets harder so you need proper simple chips to work out the kinks. I don't mean in the labs, but in products to actual customers.

Let's just say: I don't think they'll ever deliver on their originally planned 10nm design.

 

[DrMrLordX]

In other words, I don't see any problem here.

I think your analysis is flawed. Intel serviced their entire CPU lineup in 2018 with 14nm (Cascade Lake, CoffeeLake, Goldmont Plus). And by "entire product lineup" I mean everything from server to workstation to desktop to laptop. Remember the CPU shortages at the time that made it difficult to get i3s, Pentiums, and Celerons? And remember the delays in getting 9900k CPUs to market in quantity?

According to Mizuho, I think the 14nm capacity at that time was around 80 kwpm? 7nm in 2023 will be 1/4 that capacity. There is no way Intel can ship area-equivalent dice in the same quantity that they did in 2018.

On top of that, both Intel 10nm (and variants) and 7nm will be dated nodes by 2023. Intel's 10nm is roughly competitive with TSMC nodes from 2018. Intel's 7nm will be roughly competitive with TSMC nodes from 2020. Not just in density but in perf/watt and perf/area.

You know pretty much the only volume 7nm chip in 2023 will be Meteor Lake right?

That's a big problem for Intel.

 

[eek2121]

Strange statement. Why do you think they do as they do?

Because of 10nm delays, of course.

Intel s 10nm has 100M/mm2 transistors density while TSMC 7FF+ is at 113M/mm2, that s 15-20% better that their first 7nm iteration.

TSMC s 5nm is at a theorical 175M/mm2 and expect a 5nm+ to provide the same density gain as above and thus get to 200M/mm2.

That being said that s max density for some parts of a chip, in practice their 5nm is at 130M/mm2 in Apple s SoC, so expect a comparable limitation for Intel s 7nm once it is used in real chips.

7nm is rumored to be north of 205M/mm2, possibly up to 250M/mm2. It will be interesting to see how it competes with TSMC N3.

Intel needs a new design to tale advantage of it, however, and they really need to give up on the 5+ ghz clocks.

 

[LightningZ71]

While their 7mm process may be able to, theoretically, achieve those lofty transistor counts per mm^2 on specific test chips that are designed for those densities, actual shipping chips for commercial sale that are more than special purpose, one trick ponies, will, just as have all their past products, and the competition's products, use far lower transistor densities that trade transistor count for clock frequency. IMHO, what matters most is, what kind of performance can they achieve, and at what power consumption, in a relatively similar die size to their competition. In this area, we know next to nothing about their 7mm process node. It may be a big step forward for them, or, it could also be lackluster like 10og, 10, and 10sf have been with respect to competing leading edge nodes at the time of their reaching volume production. I suspect that it will be more competitive than 10sf was at the moment of it's introduction, but, that's just speculation on my part.

 

[maddie]

Because of 10nm delays, of course.


7nm is rumored to be north of 205M/mm2, possibly up to 250M/mm2. It will be interesting to see how it competes with TSMC N3.

Intel needs a new design to tale advantage of it, however, and they really need to give up on the 5+ ghz clocks.

Correct, but, Intel is being forced to use higher clocks & power because they are behind in node development. That's why I found it strange that you're wondering why they clock their designs so high up the V/F curve.

Do you really think this is Intel's 1st choice? They need that to stay competitive. They are being forced to make certain decisions. In other words, they can't clock less in the present circumstances, for top performing SKUs.

 

[IntelUser2000]

Let's just say: I don't think they'll ever deliver on their originally planned 10nm design.

On what metric? Density? Because Tremont and Xe delivers there.

The Core line of cores(actually it's true with older cores) always had 50% size reduction(2x density) from a new process. Nothing changed with 14nm and 10nm. The Atom-based cores are 2.7x denser on the 14nm process and about the similar level smaller on the 10nm process.

I doubt performance is worse than their original plans either. It was supposed to succeed the original 14nm process after all, not the 14nm with endless plusses.

 

[moinmoin]

On what metric?

On all metrics combined, the whole package, with whatever compromises applied to focus just on a single metric.

Maybe that was never Intel's goal to begin with, in which case Intel's PR just made its nodes look better in relation to the competition than they actually are. Which would again be a bad thing for Intel as it unnecessarily keeps rising expectations regarding features and scheduling it then can't fulfill.

 

[Ajay]

Correct, but, Intel is being forced to use higher clocks & power because they are behind in node development. That's why I found it strange that you're wondering why they clock their designs so high up the V/F curve.

Do you really think this is Intel's 1st choice? They need that to stay competitive. They are being forced to make certain decisions. In other words, they can't clock less in the present circumstances, for top performing SKUs.

Link?

Anything on electrostatic performance? Contacted gate and metal pitches?

 

[Ajay]

You know pretty much the only volume 7nm chip in 2023 will be Meteor Lake right? Ponte Vecchio only needs to be made in miniscule numbers to win few contracts. I'd be really worried if that's the 2024 number, but it's not. Meteor Lake is a very late 2023, early 2024 product.

Meteor Lake may be put off till 2024??

 

[jpiniero]

Meteor Lake may be put off till 2024??

End of 2023 most likely. Basically 2024.

 

[IntelUser2000]

Anything on electrostatic performance? Contacted gate and metal pitches?

What do you mean? maddie is responding to eek talking about 14nm. 14nm is behind in all metrics, and that's the point. They had to ramp up clocks and power because they were stuck on 14nm. Look how much better the Tigerlake-SFF desktop fares compared to Rocketlake. It's almost at half the TDP for pretty much the same clocks.

And 10nm is twice as dense for Core cores and 2.5x+ dense for Atom/Graphics.

Could you imagine the disaster if we had Rocketlake-U and -H? They'd never calm the crowd after that.

 

[eek2121]

Correct, but, Intel is being forced to use higher clocks & power because they are behind in node development. That's why I found it strange that you're wondering why they clock their designs so high up the V/F curve.

Do you really think this is Intel's 1st choice? They need that to stay competitive. They are being forced to make certain decisions. In other words, they can't clock less in the present circumstances, for top performing SKUs.

Intel has had an addiction to high clocks since the Core 2 came out.

It got even worse with Haswell.

That is why I suspect the gracemont cores in ADL-S will be pushed well past the point of being efficient.