• Guest, The rules for the P & N subforum have been updated to prohibit "ad hominem" or personal attacks against other posters. See the full details in the post "Politics and News Rules & Guidelines."

Discussion Intel current and future Lakes & Rapids thread

Page 425 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Exist50

Senior member
Aug 18, 2016
276
304
136
But you should know that iterative designs are generally 2-3 years from paper to production, while clean sheet designs are more like 5 years?
As mentioned, these aren't "clean sheet" designs. Moreover, SoC vs IP development works on different time tables.

Do you think Intel only has one project in the works at any given time?
I already described the timetable. In 2016, those two projects were Ice Lake and Broxton. And the Skylake derivatives, if you want to include those.

In order to meet its previous iterative release schedule (tick tock), Intel would have to have started:
Tick tock was already dead by this point. Again, in addition to Broxton (which you shouldn't leave off), Cannonlake and Ice Lake development stretched well beyond what it should have. Ice Lake is what? D step? E step?

There may once have been a slide with the Tiger Lake name in 2015, but in terms of actual execution, a name on a roadmap is nothing.

Not if Intel couldn't hit the clock/voltage targets they wanted with 10nm+.
You don't delay a product a full generation for a little more performance from the process. Tiger Lake IPs with Ice Lake clocks/process would have been a strictly better product than Ice Lake.
 

IntelUser2000

Elite Member
Oct 14, 2003
7,497
2,276
136
Yeah. They had all the time in the world to tweak their databases while 10nm was unusable. Even back in 2016 when I was still wasting my time at Intel, Tigerlake was already months old.
This is so silly that it's almost childish.

And you don't think Icelake was older than that? If they were ready with Tigerlake before Icelake that's what would have came instead. Just like Exist50 said.

Cannonlake in 2011-2013
IceLake in 2014
TigerLake in 2015
Yes and dmens made the point that Tigerlake had much longer to refine. Which is ridiculous. Of course it did, since it came out a year later and is a successor to Icelake.
 
Last edited:

itsmydamnation

Platinum Member
Feb 6, 2011
2,210
1,817
136
This is so silly that it's almost childish.

And you don't think Icelake was older than that? If they were ready with Tigerlake before Icelake that's what would have came instead. Just like Exist50 said.
I dont think it is and your logic is flawed, your using hind sight to say what they would have done at X point ignoring things like politics , projections , sunk cost fallacy.
 

DrMrLordX

Lifer
Apr 27, 2000
17,268
6,265
136
@Exist50

I think we are going off-topic here, but if you think that IceLake was still a new project in 2016, you are mad. IceLake was meant to launch in 2017. And had it not been for the 14nm delays, it would have launched earlier than that.
 

Exist50

Senior member
Aug 18, 2016
276
304
136
@Exist50

I think we are going off-topic here, but if you think that IceLake was still a new project in 2016, you are mad. IceLake was meant to launch in 2017. And had it not been for the 14nm delays, it would have launched earlier than that.
I agree that this conversation isn't going anywhere, yes, but the claim was Tiger Lake, not Ice Lake. Ice Lake was both in development first and for much longer than Tiger Lake. Look at the number of steppings for each.
 

dmens

Platinum Member
Mar 18, 2005
2,183
727
136
This is so silly that it's almost childish.

And you don't think Icelake was older than that? If they were ready with Tigerlake before Icelake that's what would have came instead. Just like Exist50 said.



Yes and dmens made the point that Tigerlake had much longer to refine. Which is ridiculous. Of course it did, since it came out a year later and is a successor to Icelake.
Sigh. When I say months old, that means engineering development. Not product ready for market. I deal with the former, not the latter.

Look at the number of steppings for each.
You do know a stepping is only recorded when a tapeout actually occurs, right? You can hammer and tweak on a design for a decade and tape out once and it will still be A0.

Anyways, enough with dealing with roadmap diviners pretending to know things. Peace out.
 

eek2121

Senior member
Aug 2, 2005
990
1,070
136
You guys. 🤣

FYI a top SKU Tiger Lake has a base frequency of 3.00 ghz @ 28W. An Ice Lake SKU @28W has a base frequency of 2.30 GHz.
 

IntelUser2000

Elite Member
Oct 14, 2003
7,497
2,276
136
I dont think it is and your logic is flawed, your using hind sight to say what they would have done at X point ignoring things like politics , projections , sunk cost fallacy.
I'm going to stop with this post as well, but others are saying Tigerlake mostly clocks higher not because the process used in Icelake was crap but because Tigerlake had much more time to refine than Icelake.

It starts at post #10585.

Considering Tigerlake came out a year after Icelake that means Intel for some reason chose to release Icelake when Tigerlake could have been released instead.

As design it older by few more years, It was released in 2015, but taped out in 2014 and probably has ideas from ~2012 timeframe. The fact that it took AMD almost 8 years to beat it with ZEN3 is just mind boggling. And it highlights Intel's failures even more.
You know what I meant. :p

You can't say 8 years since Zen 3 was available to buy in 2020. I absolutely don't care about taping out and when designs were first made up since it doesn't count until it's out. Still 5 years isn't a short time but Zen 3 absolutely crushes everything Intel so.
 
Last edited:

dullard

Elite Member
May 21, 2001
22,792
1,031
126
It is not. Just stop.
I think you are confusing this graph with a graph of CPU voltage vs frequency. This is a graph of microarchitecture capabilities. Yes, Intel CPUs have threshold voltages that are much higher. CPUs have mixed transistors and other circuitry. As I type this, my CPU is at 0.67 V, since it is mostly idle. If we were talking CPUs, then I'd agree with you.

But, this is NOT a graph of a CPU. It is a graph showing the microarchitecture and what it can do. In that case, yes, the paper that I linked shows 0.24 V for the most basic Intel 10 nm transistor.
 

eek2121

Senior member
Aug 2, 2005
990
1,070
136
I'm going to stop with this post as well, but others are saying Tigerlake mostly clocks higher not because the process used in Icelake was crap but because Tigerlake had much more time to refine than Icelake.

It starts at post #10585.

Considering Tigerlake came out a year after Icelake that means Intel for some reason chose to release Icelake when Tigerlake could have been released instead.



You know what I meant. :p

You can't say 8 years since Zen 3 was available to buy in 2020. I absolutely don't care about taping out and when designs were first made up since it doesn't count until it's out. Still 5 years isn't a short time but Zen 3 absolutely crushes everything Intel so.
It has nothing to do with the architecture. Intel themselves have stated that there was a significant improvement multiple times. Anandtech has found there to be a 15% improvement. I question anyone that claims this comes from willow cove vs. sunny cove. That flies in the face of statements made by Intel. Anyone making such a statement should provide evidence Intel is misleading everyone.

Zen 3 does not crush Tiger lake H from what we have seen. Cezanne and TGL-H appear to have similar IPC, but TGL-H clocks higher. This gives it a tiny lead in overall performance.

Intel’s biggest issue is that they are releasing it half a year after Cezanne. Note that TGL-H (finally) launches in 3 days.
 

IntelUser2000

Elite Member
Oct 14, 2003
7,497
2,276
136
Zen 3 does not crush Tiger lake H from what we have seen. Cezanne and TGL-H appear to have similar IPC, but TGL-H clocks higher. This gives it a tiny lead in overall performance.
AMD gets double the amount of cores in the same U lineup. I am inclined to believe it's the cores being power hungry that makes overall gaming performance worse in the 15W envelope but do better at 25W.

It can't be just the process being behind, especially with 10SF. I think cores are deficient as well.
 

Exist50

Senior member
Aug 18, 2016
276
304
136
AMD gets double the amount of cores in the same U lineup. I am inclined to believe it's the cores being power hungry that makes overall gaming performance worse in the 15W envelope but do better at 25W.

It can't be just the process being behind, especially with 10SF. I think cores are deficient as well.
Multiple things, probably. Zen 3 is a better core than Willow Cove, but 6c CML was a thing. Seems reasonable to believe that they could have done a 6c TGL-U chip as well. Perhaps a resourcing problem.

At least Alder Lake seems to have a more useful distribution of core configs.
 

IntelUser2000

Elite Member
Oct 14, 2003
7,497
2,276
136
Multiple things, probably. Zen 3 is a better core than Willow Cove, but 6c CML was a thing. Seems reasonable to believe that they could have done a 6c TGL-U chip as well. Perhaps a resourcing problem.

At least Alder Lake seems to have a more useful distribution of core configs.
I expected more for Tigerlake. The battery life hasn't increased. Now manufacturers are showing slightly increased times on AMD laptops. Oh how times change!

And the frequency vs. power graph shows it can easily be clocked to be made really power hungry. Based on the controversial graph I was thinking 30-40% gains in MT were possible, but really it was half that. The really needed that, because people are making excuses for why Renoir is 50%+ faster.

The humongous die area is an issue. Now big die is fine if the performance is up to par. But two core pairs with it's caches take full width of the die. By also opting for clocks over wider/faster architecture, they let competition get ahead of them further.

But like almost everything that's overhyped, things fall short of expectations. What happened to shut up and just work?
 

jpiniero

Diamond Member
Oct 1, 2010
9,337
1,884
136
Multiple things, probably. Zen 3 is a better core than Willow Cove, but 6c CML was a thing. Seems reasonable to believe that they could have done a 6c TGL-U chip as well. Perhaps a resourcing problem.
Didn't want to spend any resources on anything other than trying to improve yields, I'm guessing. They did do Rocket Lake U, but of course that was cancelled.
 

coercitiv

Diamond Member
Jan 24, 2014
4,363
5,696
136
Multiple things, probably. Zen 3 is a better core than Willow Cove, but 6c CML was a thing. Seems reasonable to believe that they could have done a 6c TGL-U chip as well. Perhaps a resourcing problem.
Both ICL and TGL dies were designed by Intel with iGPU performance in mind. Between the larger cores and the considerably higher GPU budget, there wasn't any room left for another 2 cores. It seems both Intel and AMD feel that 150mm2 is the sweet spot in terms of mobile APU die area, hence both designed their chips with obvious limitations in order to meet this target.

At least Alder Lake seems to have a more useful distribution of core configs.
Mobile ADL looks like a much more balanced approach over ICL/TGL half-hearted attempts, lots more potential too. That being said, in terms of overall perception it will be weighed and measured against a very tough competition. Apple's Q3 announcements alone may shrink ADL achievements even before launch. At least Rembrandt looks like it may launch after ADL, which is a relief of sorts.
 
  • Like
Reactions: Tlh97

andermans

Member
Sep 11, 2020
71
65
51
Mobile ADL looks like a much more balanced approach over ICL/TGL half-hearted attempts, lots more potential too. That being said, in terms of overall perception it will be weighed and measured against a very tough competition. Apple's Q3 announcements alone may shrink ADL achievements even before launch. At least Rembrandt looks like it may launch after ADL, which is a relief of sorts.
Originally yes, but I think things are looking more and more like ADL mobile could be launched at CES 2022, which would likely be at the same time as Rembrandt. Unless they're doing an early launch without retail laptops being ready.
 

jpiniero

Diamond Member
Oct 1, 2010
9,337
1,884
136
It seems both Intel and AMD feel that 150mm2 is the sweet spot in terms of mobile APU die area, hence both designed their chips with obvious limitations in order to meet this target.
Actually historically the U parts have been much smaller than that. Yet ADL-P is going to be way bigger.
 

itsmydamnation

Platinum Member
Feb 6, 2011
2,210
1,817
136
Considering Tigerlake came out a year after Icelake that means Intel for some reason chose to release Icelake when Tigerlake could have been released instead.
That is exactly what I am contesting , it assuming a clear line in the sand early enough to make that decision with leadership willing to make the call.

But if 10nm is always just around the corner you could be stuck in sunk cost falacy and the "extra" time taken to stop the bring to market work on ice lake and move to tigerlake might look like a bigger Schedule slip because it will take longer from that exact point to get to market if the just around the corner fix actually happened.
 
Last edited:

coercitiv

Diamond Member
Jan 24, 2014
4,363
5,696
136
Actually historically the U parts have been much smaller than that. Yet ADL-P is going to be way bigger.
Historically the U parts have mostly been GT2, whereas my understanding is ICL/TGL were built as "GT3 class". Haswell ULT 2+3 was ~181mm2, Broadwell 2+3 was ~133mm2 while 4+3 jumped back to ~182mm2.
 
  • Like
Reactions: Tlh97

eek2121

Senior member
Aug 2, 2005
990
1,070
136
AMD gets double the amount of cores in the same U lineup. I am inclined to believe it's the cores being power hungry that makes overall gaming performance worse in the 15W envelope but do better at 25W.

It can't be just the process being behind, especially with 10SF. I think cores are deficient as well.
I expected more for Tigerlake. The battery life hasn't increased. Now manufacturers are showing slightly increased times on AMD laptops. Oh how times change!

And the frequency vs. power graph shows it can easily be clocked to be made really power hungry. Based on the controversial graph I was thinking 30-40% gains in MT were possible, but really it was half that. The really needed that, because people are making excuses for why Renoir is 50%+ faster.

The humongous die area is an issue. Now big die is fine if the performance is up to par. But two core pairs with it's caches take full width of the die. By also opting for clocks over wider/faster architecture, they let competition get ahead of them further.

But like almost everything that's overhyped, things fall short of expectations. What happened to shut up and just work?
Intel went with 4 cores for the U lineup for a number of reasons. The decision was made before AMD even released an 8-core part.

Also, the H series is 8 cores and launches this week.
 

jpiniero

Diamond Member
Oct 1, 2010
9,337
1,884
136
Historically the U parts have mostly been GT2, whereas my understanding is ICL/TGL were built as "GT3 class". Haswell ULT 2+3 was ~181mm2, Broadwell 2+3 was ~133mm2 while 4+3 jumped back to ~182mm2.
Die space % wise it isn't that bad to be compared to GT3.
 

tomatosummit

Member
Mar 21, 2019
55
29
61
Actually historically the U parts have been much smaller than that. Yet ADL-P is going to be way bigger.
This was before competition, intel was happy to sell sub 100mm^2 dies for 2c/4t laptops until the end of time.
I think skylake-u was around 90mm^2 and I can't find the figures but cannonlake (rip) was a decent amount smaller again, probably with old 10nm and it's full density targets.
 
  • Like
Reactions: Tlh97 and majord

ondma

Platinum Member
Mar 18, 2018
2,160
809
106
Intel went with 4 cores for the U lineup for a number of reasons. The decision was made before AMD even released an 8-core part.

Also, the H series is 8 cores and launches this week.
Yea, but will the chips actually be available?
 

ASK THE COMMUNITY