Discussion Intel current and future Lakes & Rapids thread

[coercitiv]

For MT loads? Such as Distributed Computing?

Are you asserting DC does not scale with ST performance?

 

[IntelUser2000]

If true, then I really hope that Intel improves their HT implementations, as Ryzen's SMT seems to be a much greater efficiency improvement compared to Intel's HT, as far as performance gained when it is enabled.

Is that really true? I've been trying to find comparisons after reading your post and I could find a handful. One good one is here: http://www.hardware.fr/articles/964-7/impact-smt-ht.html

According to the application and game average, the losses/gains for SKL-X/BDW-E/Ryzen are about the same.

If what you are saying is true, then there can be few reasons:

1. First of all, Skylake X and Broadwell E both perform significantly better in absolute application performance, due a little to the uarch advantage, but mostly because it has more cores. If you take the applications that Ryzen has an "advantage" in SMT gain, you'll see that Intel chips are performing quite a bit better. It's because bottlenecks start shifting.

It's also demonstrated here: http://www.hardware.fr/focus/121/influence-nombre-coeurs-smt-ryzen.html

The lower core Ryzen chips gain lot more because the rest of the platform is less of a bottleneck.

Possible conclusion: The higher performance system could be I/O bound

2. Architectures that perform better naturally gain less from SMT. It makes sense, because SMT takes advantage of bubbles in the pipeline. If the uarch is better at filling those bubbles, with similar implementation detail, the gain from SMT would be less.

3. Thread bound. You can see from the second link's gaming results the the lower core chips actually gain from having SMT enabled. Even so-called very multi-threaded programs run into maximum thread count, or what could be thought as very diminishing returns.

 

[Lovec1990]

https://wccftech.com/intel-core-i7-9700k-9th-gen-8-cores-16-threads-rumor/

intresting

 

[beginner99]

If true, then I really hope that Intel improves their HT implementations, as Ryzen's SMT seems to be a much greater efficiency improvement compared to Intel's HT, as far as performance gained when it is enabled.

Better HT / SMT scaling actually means that you are worse at using all the cores resources with just 1 thread.

Think about how HT works. The additional thread uses a cores resources the other thread currently doesn't need. If your core design is very good and balanced, the first thread will use most of the cores resources and hence the additional thread only gives a small gain. And vice-versa a large HT gain means there are a lot of unused resources. So low HT / SMT scaling isn't necessarily a bad thing. Therefore when AMD improves Zen, SMT scaling might actually go down.

 

[raghu78]

https://wccftech.com/intel-core-i7-9700k-9th-gen-8-cores-16-threads-rumor/

intresting

The funny part is hkepc refers to 9th gen core as cannonlake which we know is not true. Cannonlake will never appear on desktop. Its CFL in 2018 and then ICL in 2019.

 

[mikk]

Additional speculation from someone with industry contacts (David Schor, WikiChip): https://fuse.wikichip.org/news/484/8th-gen-coffee-lake-and-9th-gen-lineup/

9th generation Core is Ice Lake. Core i3 has 4 cores, i5 has 6, and i7 has 8, all with Hyper-threading.

It sounds legit from him. But there is room for a Core i9 lineup imho considering that Intel is starting to use the i9 brand for mainstream as well with i9-8950HK.

 

[Dayman1225]

HWInfo update!

 

[Glo.]

Which also would suggest that Z390 is compatible with IceLake CPUs.

 

[Ajay]

Which also would suggest that Z390 is compatible with IceLake CPUs.

Which I guess means no update for DMI - too bad (though, if Ice Lake has 4 more PCIe lanes on the CPU, OK then).

 

[jpiniero]

It sounds legit from him. But there is room for a Core i9 lineup imho considering that Intel is starting to use the i9 brand for mainstream as well with i9-8950HK.

Well Intel used to have mobile i7 Extreme models as late as Haswell, could be the return of that. It would be rather pricey though - the Ivy Bridge models were over a grand.

 

[IntelUser2000]

Which also would suggest that Z390 is compatible with IceLake CPUs.

The fact that there's evidence of a 8 core Coffeelake part existing makes this unlikely. Z390 probably supports that.

I think there's a good chance their 10nm can be in serious volume by 2019, but not in 2018. The Eurocom leak was talking H2 2018, which probably means Back-to-School season. Then by this logic we're expecting full Icelake lineup by the holiday season?!?

What makes it even more unlikely is that just like the earlier roadmap, we'll actually get to see Coffeelake-U and -H parts. And that's well into 2018.

 

[Glo.]

The fact that there's evidence of a 8 core Coffeelake part existing makes this unlikely. Z390 probably supports that.

I think there's a good chance their 10nm can be in serious volume by 2019, but not in 2018. The Eurocom leak was talking H2 2018, which probably means Back-to-School season. Then by this logic we're expecting full Icelake lineup by the holiday season?!?

What makes it even more unlikely is that just like the earlier roadmap, we'll actually get to see Coffeelake-U and -H parts. And that's well into 2018.

If IceLake is 9th Generation of Intel Core CPUs - it is not that unlikely, as you think. It would be whole 1 year AFTER initial Coffee Lake launch.

 

[PeterScott]

The fact that there's evidence of a 8 core Coffeelake part existing ...

Evidence? You mean one off hand comment in another forum?

 

[IntelUser2000]

Evidence? You mean one off hand comment in another forum?

Evidence: https://cdn.segmentnext.com/wp-content/uploads/2017/09/Intel-Coffee-Lake-S-8C-620x432.png

G-o-o-g-l-e.

If IceLake is 9th Generation of Intel Core CPUs - it is not that unlikely, as you think. It would be whole 1 year AFTER initial Coffee Lake launch.

The problems they are having with 10nm are often overblown, but it shouldn't be understated either. I just think they won't be ready.

 

[beginner99]

Just a thought: Given the have known about the 10 nm issues for at least couple years, is it possible that Intel will backport ice lake to 14 nm++? Not an EE so not sure how feasible that is. To fix die size issues, easiest would be to make the iGPU smaller than in original design.

 

[PhonakV30]

So Z370 won't support 8C/16T ?

 

[VirtualLarry]

Better HT / SMT scaling actually means that you are worse at using all the cores resources with just 1 thread.

Think about how HT works. The additional thread uses a cores resources the other thread currently doesn't need. If your core design is very good and balanced, the first thread will use most of the cores resources and hence the additional thread only gives a small gain. And vice-versa a large HT gain means there are a lot of unused resources. So low HT / SMT scaling isn't necessarily a bad thing. Therefore when AMD improves Zen, SMT scaling might actually go down.

How does that jive with examples such as recent (OPEN)Power-architecture CPUs? That are tuned for maximum MT throughput, and support more than two SMT threads per core. (4? 8? I forget.)

Does that mean that Intel's Core is a more efficient architecture, because it gains the least in terms of MT throughput from HT, among Core, Zen, and Power?

 

[coercitiv]

Does that mean that Intel's Core is a more efficient architecture, because it gains the least in terms of MT throughput from HT, among Core, Zen, and Power?

For consumer workloads? Definitely.

Bellow you can find IPC results published by The Stilt on this forum. First graph is relative ST IPC @ 3.5Ghz, second is throughput of 4c/8t at the same speed of 3.5Ghz. You tell me which is the more efficient architecture in terms of balance between ST and MT performance.

Spoiler: Relative IPC

Hint: just because KBL is at worst 12% faster in ST and at worst only 9% faster in MT doesn't change the fact that it's faster even in the least favorable circumstances.

 

[IntelUser2000]

How does that jive with examples such as recent (OPEN)Power-architecture CPUs? That are tuned for maximum MT throughput, and support more than two SMT threads per core. (4? 8? I forget.)

Does that mean that Intel's Core is a more efficient architecture, because it gains the least in terms of MT throughput from HT, among Core, Zen, and Power?

The version of SMT used in Power CPUs take lot more die and power than on AMD and Intel chips. In turn, they get bigger benefit out of it. The core size increase on Hyperthreading is said to be under 5%, the SMT on Power 5 increased core size by 24%. They claim that allows performance to improve by 40%. While the gain doesn't seem far from Intel's 30% gain, IBM's enhancements to SMT allows for far greater average gain, and in more applications.

http://slideplayer.com/slide/7577746/24/images/40/Initial+Performance+of+SMT.jpg
https://images.anandtech.com/reviews/cpu/intel/nehalem/uarch/HTperformance.jpg

Pentium 4 SMT: 1% for SpecInt_Rate, and 7% for SpecFP_Rate
Power 5 SMT: 23% for Integer, and 16% for FP

The gap isn't as big for SMT2 on the latest architectures(because Pentium 4 sucked with SMT), but average gains for IBM's SMT, are still 2x Intel's SMT.

 

[beginner99]

How does that jive with examples such as recent (OPEN)Power-architecture CPUs? That are tuned for maximum MT throughput, and support more than two SMT threads per core. (4? 8? I forget.)

Does that mean that Intel's Core is a more efficient architecture, because it gains the least in terms of MT throughput from HT, among Core, Zen, and Power?

IBM Power-CPUSs target a completely different market than Intel Core / AMD Zen. So it hence is hard to draw comparisons. Both for Intel and AMD latency also matters. SMT can impact latency which is terrible for GUI and probably also why some games lose performance with HT. IBM Power doesn't need to worry about gaming or GUI. All they care about is throughput and hence that design.

 

[DrMrLordX]

IBM Power-CPUSs target a completely different market than Intel Core / AMD Zen. So it hence is hard to draw comparisons. Both for Intel and AMD latency also matters. SMT can impact latency which is terrible for GUI and probably also why some games lose performance with HT. IBM Power doesn't need to worry about gaming or GUI. All they care about is throughput and hence that design.

I would really like to see how a 1c/8t or 1c/10t (not sure how far SMT scales on POWER9) POWER chip running a Linux desktop or something along those lines. Because AMD and Intel are totally selling chips that can handle 8 or more threads.

I realize that due to economy of scale etc., a hypothetical POWER chip like that would be hella expensive, but it would still be interesting to see how it would work out.

 

[Lovec1990]

^^ im not sure this would work out becouse one core would not be able too handle 10 threads

 

[LTC8K6]

https://en.wikipedia.org/wiki/POWER9

Power 9 can be SMT4 or SMT8, 4 or 8 threads per core. Either way, the chip runs 96 threads with either 12 SMT8 cores or 24 SMT4 cores.

 

[jpiniero]

Just a thought: Given the have known about the 10 nm issues for at least couple years, is it possible that Intel will backport ice lake to 14 nm++? Not an EE so not sure how feasible that is.

They could have done that but the decision would have had to been made a long time ago. So it's not happening.

Will say that especially with the news that they are releasing a Skylake-SP version of Xeon D it seems more likely now that Icelake uses the mesh. Intel of course is now a server first company, and the mesh is better at larger core counts. Even if they never end up releasing an Icelake Xeon-D they clearly would have planned for it.

 

[Dayman1225]

They could have done that but the decision would have had to been made a long time ago. So it's not happening.

Will say that especially with the news that they are releasing a Skylake-SP version of Xeon D it seems more likely now that Icelake uses the mesh. Intel of course is now a server first company, and the mesh is better at larger core counts. Even if they never end up releasing an Icelake Xeon-D they clearly would have planned for it.

Desktop Icelake will almost certainly not use mesh. That just doesn't make sense... The whole server first stuff starts with 10nm++ products afaik.