Discussion Intel current and future Lakes & Rapids thread

[jpiniero]

And yes, if you increase the power the CPU's allowed to draw, you need motherboards (and cooling solutions) capable of handling that.

OEMs don't have to increase the PL2 to 250 W if they don't want to. Boards have a lot of control over the power draw. Rocket Lake will happily run at 65 W or even 35 W but it will surely be at a lot lower clock than the similar Comet Lake.

 

[DrMrLordX]

Oh my, the 1800+ ST score in GB is really high! Actually points to Cypress Cove having slightly higher IPC than Willow Cove, which is truly perplexing 😂 here's me eagerly waiting for comprehensive testing.

To add to what @Hulk said, let's remember that GB5 isn't the end-all, be-all performance benchmark. There are any number of factors (including cache hierarchy) that can affect scores without necessarily harming actual application performance. It's unfortunate that GB numbers are some of the first data we receive these days from ES and QS samples prior to product launches. It can skew our perception of these CPUs before they're properly reviewed.

 

[Bam360]

As unfortunate as Cinebench would be as a first data point, because Geekbench is not worse, just different.

 

[shady28]

As unfortunate as Cinebench would be as a first data point, because Geekbench is not worse, just different.

If you had to pick a single benchmark as a frame of reference, Geekbench would be among the best. It is like a mini SPEC. Main weakness is that it only tests small data sets, so memory performance does not much factor in.

But there's a whole mess of varied tests there. SQL, HTML5, Gaussian Blur, Ray Tracing, Text and PDF rendering, AI, Crypto, and so on.

Interpreting Geekbench 5 Scores / Geekbench / Knowledge Base - Primate Labs Support

support.primatelabs.com

 

[LightningZ71]

Having used an el cheapo i3-1035-g1 as my throw away laptop that I take everywhere with me, I am of the opinion that most any processor from a modern architecture and node is plenty fast enough for the day to day stuff. For my purposes, it's the various geekbench subscores and the other benchmarks out there that test specific functions that mean the most to me.

 

[Thala]

MESI-protocol can also make direct L1-L1 via migratory optimizations- by moving that dirty line from core to core. ARM also did that with MESI-states, so far only AMD does have used O-state commonly and in Zen they can do both, copy dirty line (O) and move that dirty line (D in their case as they also support O-state). Doing both obviously needs some kind of tracking of dirty lines behavior but complex schemes are nowadays doable.....
But in either case line transfer from L1 to other cores L1 is by through their core-to-core interconnection - so basically through L2 and L3 caches in case of cpu's that have core-to-core connections handled by lower cache levels.

Not sure if this was supposed to be a counter argument? I never claimed anything contradicting...
Besides almost all Cortex-A Cores - including really low-end cores like the Cortex A5 - do support MOESI, do have an O-state and do direct L1-to-L1 communication within a cluster (either classical SCU-cluster or DynamIQ cluster) Exceptions are Cortex A9, R8 and older cores - which are MESI without L1-to-L1 communication.

But this was not even my point - my point was that even if you have an inclusive (write-back) cache, there is no guarantee at all, that the most recent update is visible in all inclusive cache hierarchies, nor that a cache-line is present in all inclusive cache hierarchies.

 

[Det0x]

I realize there are a lot of "garbage" leaked benchmarks out there but do you think this one has any validity?

Intel Core i7-11700K Rocket Lake 8 Core CPU Benchmarks Leak Out in Geekbench, Faster Than AMD Ryzen 7 5800X In Both Single & Multi-Threaded Performance

The latest benchmarks of Intel's Core i7-11700K 8 Core & 11th Gen Rocket Lake Desktop CPU have leaked out within Geekbench.

wccftech.com

I did some quick calcs for fun.

CPU Name	Geekbench Single-Thread (1T)	Clock	MHz/Geekbench Point	Geekbench Multi-Thread (nT)	Performance Difference Vs (1T)	Performance Difference Vs (nT)
Intel Core i7-11700K	1810	5000	2.76	11304	100%	100%
AMD Ryzen 9 5950X	1672	4900	2.93	16515	108%	68%
AMD Ryzen 7 5800X	1663	4700	2.83	10361	109%	109%
Intel Core i9-10900K	1405	5300	3.77	10967	129%	103%
Intel Core i7-10700K	1349	5100	3.78	8973	134%	126%
Comet Lake vs Comet Lake	10700k	10900k
Geekbench 1T	3.78	3.77	100.2%
10700k +0.2% (Should be a tie)
Zen 3 vs Zen 3	5950x	5800x
Geekbench 1T	2.93	2.83	103.7%
5800x +3.7% (Should be a tie)
Rocket Lake vs Zen 3	11700k	5800x
Geekbench 1T	2.76	2.83	102.3%
10700k +2.3%
Rocket Lake vs Comet Lake	11700k	10700k
Geekbench 1T	2.76	3.77	136.6%
11700k +36.6%

Where are you getting the zen 3 numbers ?
This is my geekbench5 run: https://browser.geekbench.com/v5/cpu/5371496 (.gb5 tho effective clock was ~5050mhz)

 

[uzzi38]

Where are you getting the zen 3 numbers ?
This is my geekbench5 run: https://browser.geekbench.com/v5/cpu/5371496 (.gb5 tho effective clock was ~5050mhz)

I think from Geekbench's list of average results.

The problem is that the average for Zen 3 is lowered thanks to VAES256 support only landing in GB5.3. Most people tested Zen 3 with earlier versions where it scored sub 1700 on average.

VAES256 support massively boosted Crypto scores on Zen 3 which provided a decent lift to overall scores. But it's also why why normally suggest not to look at the overall score but rather INT and FP ones instead to more accurately guage performance.

 

[naukkis]

Not sure if this was supposed to be a counter argument? I never claimed anything contradicting...
Besides almost all Cortex-A Cores - including really low-end cores like the Cortex A5 - do support MOESI, do have an O-state and do direct L1-to-L1 communication within a cluster (either classical SCU-cluster or DynamIQ cluster) Exceptions are Cortex A9, R8 and older cores - which are MESI without L1-to-L1 communication.

But this was not even my point - my point was that even if you have an inclusive (write-back) cache, there is no guarantee at all, that the most recent update is visible in all inclusive cache hierarchies, nor that a cache-line is present in all inclusive cache hierarchies.

I do agree with your points, just argue on little details.

Inclusive cache means that line in lower cache levels are also visible in upper levels - it might not be valid but it still known that cache line is in cache hierarchy, needing only write-back from lover levels. Or that inclusive cache could been organized so that upper levels only have tags from lover levels and data cache for those lines in lower cache level are physically just that lower cache level. So when hit in upper cache level happens it reads valid data from lover cache level without writebacks. So lower cache level is just a subset from higher cache level.

Modern designs do have tags from lover cache levels in their last level cache even when cache structure isn't inclusive - so difference between inclusive and non-inclusive cache systems isn't that big.

Moesi was that original University designed cache-coherence protocol, but as I know most of designs use MESI instead as it's usually more efficient to move dirty cache line to other core instead of copying it, moving it gives exclusive access to that line to requesting core giving it also write permissions. As I see ARM is implemented migratory optimizations simply by that L1-cache has only MESI-states and MOESI is supported from L2 level.

And I suppose you mean by direct L1 to L1 communication that L1 cache is also coherent? As those old ARM cores didn't have coherent L1-(data)caches. Coherent L1-cache doesn't mean that L1-caches communicate directly, they aren't directly connected to each other but only to upper cache levels. But as they are coherent write access to L1-cache line is allowed only after that cache line is invalidated from other caches. That's a store-allocate scheme, memory is always 100% coherent to all cores in coherent cluster.

 

[yuri69]

But there's a whole mess of varied tests there. SQL, HTML5, Gaussian Blur, Ray Tracing, Text and PDF rendering, AI, Crypto, and so on.

Interpreting Geekbench 5 Scores / Geekbench / Knowledge Base - Primate Labs Support

support.primatelabs.com

There are hidden caveats. The today's hot topic is usage of VAES x86 extension under the "Crypto" subtest. It gives Intel AVX512 a nice boost.

The question is, is really a meaningful 512b VAES software in the wild? Is it really general purpose that it can be represented in the GB overall score?

 

[mikk]

Alder Lake Hybrid does not support AVX512. It's limited to AVX2.

 

[uzzi38]

Alder Lake Hybrid does not support AVX512. It's limited to AVX2.

Yes and no.

Out of the box you're correct. You'll be able to disable the little cores in BIOS with a single toggle which will re-enable AVX512 support again.

Intel are the biggest hurdle to AVX512 adoption on the desktop I swear.

 

[shady28]

There are hidden caveats. The today's hot topic is usage of VAES x86 extension under the "Crypto" subtest. It gives Intel AVX512 a nice boost.

The question is, is really a meaningful 512b VAES software in the wild? Is it really general purpose that it can be represented in the GB overall score?

If you look at the weightings on GB, Crypto is 5%. This will not significantly alter the overall results, which are heavily weighted towards integer benchmarks.



Edit: To note, if you want to discount AES in a Zen 3 vs Rocket Lake comparison, I would assume you'd want to do the same for Zen 3 vs Comet Lake. You may not like the results of that discounting.

The performance delta between Comet Lake and Zen 3 shrink significantly when you discount AES, where Zen 3 is more than 2X faster than Comet Lake. This is a fast 5800X vs a fast 10700K :

 

[mikk]

Yes and no.

Out of the box you're correct. You'll be able to disable the little cores in BIOS with a single toggle which will re-enable AVX512 support again.

This is not confirmed and speculation at this point. I believe it won't work entirely on Alder Lake Hybrid SKUs, Intel clearly said it is not supported. The only question for me is what about Alder Lake SKUs without little cores, I'm not sure they would like such a ISA segmentation with an advantage over the big ones. So a lower 6+0 SKU has AVX512 while a big 8+8 can't use it, not sure if Intel would like this.

 

[uzzi38]

This is not confirmed and speculation at this point. I believe it won't work entirely on Alder Lake Hybrid SKUs, Intel clearly said it is not supported. The only question for me is what about Alder Lake SKUs without little cores, I'm not sure they would like such a ISA segmentation with an advantage over the big ones. So a lower 6+0 SKU has AVX512 while a big 8+8 can't use it, not sure if Intel would like this.

Treat it as a rumour if you wish, but it's not speculation.

 

[Zucker2k]

If you look at the weightings on GB, Crypto is 5%. This will not significantly alter the overall results, which are heavily weighted towards integer benchmarks.

View attachment 36603

Edit: To note, if you want to discount AES in a Zen 3 vs Rocket Lake comparison, I would assume you'd want to do the same for Zen 3 vs Comet Lake. You may not like the results of that discounting.

The performance delta between Comet Lake and Zen 3 shrink significantly when you discount AES, where Zen 3 is more than 2X faster than Comet Lake. This is a fast 5800X vs a fast 10700K :

View attachment 36605

Back to hair-splitting. Hehe

 

[Gideon]

If you look at the weightings on GB, Crypto is 5%. This will not significantly alter the overall results, which are heavily weighted towards integer benchmarks.

View attachment 36603

Edit: To note, if you want to discount AES in a Zen 3 vs Rocket Lake comparison, I would assume you'd want to do the same for Zen 3 vs Comet Lake. You may not like the results of that discounting.

The performance delta between Comet Lake and Zen 3 shrink significantly when you discount AES, where Zen 3 is more than 2X faster than Comet Lake. This is a fast 5800X vs a fast 10700K :

View attachment 36605

You can't have it both ways. It either doesn't change much or it does.

See Geekbench 5.2.5 for Zen 3 scores without new AES instructions. Here is a comparison between the same users 5600X between v5.2.5 and v5.3.0
MT score doesn't really change (as it's cache/memory bound probably) ST AES improves roughly 35% (the overall ST score improves by ~30 points here)

It's a small bump to the overall score, but nothing major. In your own example, even if Crypto perf would be cut in half (which it won't), the Zen 3 would still score ~1635 points. I'd still call it a noticeable win.

Regardless Judging from the i7 scores, it does appear that the main differentiator for Intel is the extra clocks and AVX-512 support. INT/FP IPC might be better but it's within margin of error. Still i9 will have even higher clocks, so there should be no doubt what will overall be faster.

I'd be really interested to see gaming results. I have no doubt Intel will win with extremely tuned memory and OC in all but most AMD cache-friendly titles (CS:GO, etc). At Stock and XMP would probably be more relevant to most users.

 

[exquisitechar]

If you look at the weightings on GB, Crypto is 5%. This will not significantly alter the overall results, which are heavily weighted towards integer benchmarks.

View attachment 36603

Edit: To note, if you want to discount AES in a Zen 3 vs Rocket Lake comparison, I would assume you'd want to do the same for Zen 3 vs Comet Lake. You may not like the results of that discounting.

The performance delta between Comet Lake and Zen 3 shrink significantly when you discount AES, where Zen 3 is more than 2X faster than Comet Lake. This is a fast 5800X vs a fast 10700K :

View attachment 36605

It's weighted as 5%, but the crypto score is huge compared to the int and FP scores. The crypto score of the leaked 11700k is around 5400 while the int and FP scores are around 1500 and 1800, respectively. So its effect on the overall score is significant.

Anyway, regardless of the crypto score, Rocket Lake-S is competitive with Vermeer. As I've said previously, the leaked single-core int score, compared to a 5800x at 5GHz, is a few percent higher, while the FP score is lower. Since the 11900k will reach 5.3GHz, it seems that it will have the ST performance crown.

 

[shady28]

You can't have it both ways. It either doesn't change much or it does.

See Geekbench 5.2.5 for Zen 3 scores without new AES instructions. Here is a comparison between the same users 5600X between v5.2.5 and v5.3.0
MT score doesn't really change (as it's cache/memory bound probably) ST AES improves roughly 35% (the overall ST score improves by ~30 points here)

It's a small bump to the overall score, but nothing major. In your own example, even if Crypto perf would be cut in half (which it won't), the Zen 3 would still score ~1635 points. I'd still call it a noticeable win.

Regardless Judging from the i7 scores, it does appear that the main differentiator for Intel is the extra clocks and AVX-512 support. INT/FP IPC might be better but it's within margin of error. Still i9 will have even higher clocks, so there should be no doubt what will overall be faster.

I'd be really interested to see gaming results. I have no doubt Intel will win with extremely tuned memory and OC in all but most AMD cache-friendly titles (CS:GO, etc). At Stock and XMP would probably be more relevant to most users.

It is not contradictory in the context of the two sets of comparisons.

In Zen 3 vs Comet Lake AES, Zen 3 is 2.1X the Comet Lake score in AES. With a weighting of 5%, this will affect the overall score by 5.25% in favor of Zen 3 vs if AES was not part of the comparison at all. This would change the Geekbench score by around 85 points if it were 1600.

In Zen 3 vs 11700K, the difference is the 11700K is 1.4X faster. This would affect the overall score by 2% vs if it was not in the benchmarks at all. This would be 32 points if the overall were 1600.

So in the case of Zen 3 vs 11700K, it's not much difference - 32 points(ish) on higher scores. In the case of Comet Lake, its 85 points of lower scores.

So yeah, if you get AES a whole ton higher on one platform than the other, it starts to have an effect even with a crypto 5%.

The base case pro-amd manipulation is to say 5800X vs 11700K is about equal if you exclude AES. But if you do that, you'd also have to say that 11700K is a lot closer to 5800X single core ex-AES.

Reality is that much of the Zen 3 lead vs Comet Lake was powered up by AES. Now Intel is better there, but they have also greatly improved every single area as shown by this comparison of the 11700K vs 10700K - 11700K wins every sub-test :

 

[shady28]

It's weighted as 5%, but the crypto score is huge compared to the int and FP scores. The crypto score of the leaked 11700k is around 5400 while the int and FP scores are around 1500 and 1800, respectively. So its effect on the overall score is significant.

Anyway, regardless of the crypto score, Rocket Lake-S is competitive with Vermeer. As I've said previously, the leaked single-core int score, compared to a 5800x at 5GHz, is a few percent higher, while the FP score is lower. Since the 11900k will reach 5.3GHz, it seems that it will have the ST performance crown.

And were you guys saying this when Zen 3 Crypto was 2.1X Comet Lake? Nope. The crypto score for Rocket Lake vs Zen 3 is actually closer than it was for Zen 3 vs Comet Lake.

The only difference is that Intel is winning that now by a big margin, so now it must be excluded....

 

[SAAA]

Alder Lake Hybrid does not support AVX512. It's limited to AVX2.

Yes and no.

Out of the box you're correct. You'll be able to disable the little cores in BIOS with a single toggle which will re-enable AVX512 support again.

Intel are the biggest hurdle to AVX512 adoption on the desktop I swear.

Beside the hybrid CPUs I wonder if we'll see also a proper Rocket Lake successor with only big cores, a HEDT part with AVX512 enabled by default. The doubt comes from this picture:

If Alder is the hybrid there might be (Sapphire Rapids?) parts for HEDT with golden coves only?

Hybrid is fine if both the small and big cores can do the same things, just at different speed and power, but with Gracemont having less features it feels sort of a waste… also another step into messy software compatibility.

 

[exquisitechar]

And were you guys saying this when Zen 3 Crypto was 2.1X Comet Lake? Nope. The crypto score for Rocket Lake vs Zen 3 is actually closer than it was for Zen 3 vs Comet Lake.

The only difference is that Intel is winning that now by a big margin, so now it must be excluded....

My stance on Zen 3 and Comet comparisons in GB5 is the same (though I haven't payed attention to that comparison, but Zen 3, Tiger Lake and now Rocket Lake instead). I pretty much always focus on the int and FP scores since they're much, much more relevant to me and most people.

 

[ondma]

Beside the hybrid CPUs I wonder if we'll see also a proper Rocket Lake successor with only big cores, a HEDT part with AVX512 enabled by default. The doubt comes from this picture:

If Alder is the hybrid there might be (Sapphire Rapids?) parts for HEDT with golden coves only?

Hybrid is fine if both the small and big cores can do the same things, just at different speed and power, but with Gracemont having less features it feels sort of a waste… also another step into messy software compatibility.

Yea, I dont get the hybrid architecture for desktop. I mean AMD had 16 big core desktop chips 3 years ago, and after still another year, Intel can match that? Sad really.

 

[jpiniero]

If Alder is the hybrid there might be (Sapphire Rapids?) parts for HEDT with golden coves only?

There's been some talk of a Sapphire Rapids-X. If it does get released you are looking at least 15 months from now.

 

[jpiniero]

Yea, I dont get the hybrid architecture for desktop. I mean AMD had 16 big core desktop chips 3 years ago, and after still another year, Intel can match that? Sad really.

Until Intel moves their desktops to a multi CPU chiplet architecture, this is how it's going to be.