Discussion Intel current and future Lakes & Rapids thread

[dmens]

You've repeatedly insisted that all the leakers are wrong about Rocket Lake performance, power, etc. It's increasingly apparent that you are wrong, and with that goes any ability to pretend you have insider or professional insight.

Apparent how? Oh right, your preferred leaks. Has there been a single leak with power measurement? No? Guess it's just faith on your part then.

 

[Exist50]

Apparent how? Oh right, your preferred leaks. Has there been a single leak with power numbers?

Lol, fine, dig yourself even deeper. And yes, there have been leaks.

Intel Core i9-11900 Rocket Lake-S engineering sample tested on B560 motherboard - VideoCardz.com

Another Intel Core i9-11900 engineering sample tested. Intel Core i9-11900 Rocket Lake-S Sample tested on B560 motherboard Intel is set to announce its new Core CPU series new 500-series motherboards at CES 2021. The company allegedly decided to launch the new motherboards before Rocket Lake-S...

videocardz.com

Intel Rocket Lake-S Core i9-11900K CPU allegedly boost up to 5.3 GHz - VideoCardz.com

Intel’s Core i9-11900K specifications The flagship Rocket Lake-S CPU has already leaked earlier this month through Ashes of the Singularity benchmark website. It was revealed back then that the CPU carries a base clock of 3.5 GHz. Unfortunately, the software does not report on maximum turbo...

videocardz.com

Pretty much identical PL2 values as Comet Lake. Which is to be expected given that it's platform compatible. If you actually had relevant experience, you'd know the OEMs wouldn't tolerate needing to design new motherboards to use Rocket Lake.

 

[dmens]

Lol, fine, dig yourself even deeper. And yes, there have been leaks.

Intel Core i9-11900 Rocket Lake-S engineering sample tested on B560 motherboard - VideoCardz.com

Another Intel Core i9-11900 engineering sample tested. Intel Core i9-11900 Rocket Lake-S Sample tested on B560 motherboard Intel is set to announce its new Core CPU series new 500-series motherboards at CES 2021. The company allegedly decided to launch the new motherboards before Rocket Lake-S...

videocardz.com

Intel Rocket Lake-S Core i9-11900K CPU allegedly boost up to 5.3 GHz - VideoCardz.com

Intel’s Core i9-11900K specifications The flagship Rocket Lake-S CPU has already leaked earlier this month through Ashes of the Singularity benchmark website. It was revealed back then that the CPU carries a base clock of 3.5 GHz. Unfortunately, the software does not report on maximum turbo...

videocardz.com

Pretty much identical PL2 values as Comet Lake. Which is to be expected given that it's platform compatible. If you actually had relevant experience, you'd know the OEMs wouldn't tolerate needing to design new motherboards to use Rocket Lake.

LOL. That's a power recommendation, not a measurement. Learn the difference.

As for motherboards, are you implying a higher powered core would always need a new motherboard? Really?

 

[mikk]

https://twitter.com/x/status/1343713561193963526

Maximum frequency report is flawed, I wonder if it's 1.76 Ghz instead of 17.6 Ghz.

 

[Exist50]

LOL. That's a power recommendation, not a measurement. Learn the difference.

As for motherboards, are you implying a higher powered core would always need a new motherboard? Really?

I really should stop feeding the trolls, but "PL" stands for "power limit". It's not a recommendation. Again, if you actually had the experience you claim to, I would not have to explain this.

And yes, if you increase the power the CPU's allowed to draw, you need motherboards (and cooling solutions) capable of handling that. For OEMs, who generally design as close to the minimum as possible, that translates to new motherboards. They don't like that.

 

[Exist50]

https://twitter.com/x/status/1343713561193963526

Maximum frequency report is flawed, I wonder if it's 1.76 Ghz instead of 17.6 Ghz.

Possibly also an issue with the Gracemont modules. 17.6GHz/4 = 4.4GHz. No idea if Gracemont can clock that high, but it seems within the realm of possibility.

 

[mikk]

I really doubt this early sample clocks that high, the base is super low as well considering this is a future big desktop chip. Also the Integer ST score seems too low even for Gracemont compared to Tremont and Skylake if it's 4.4 Ghz.

 

[Bouowmx]

Alder Lake on DDR4
One fewer early-adopter technology to worry about

 

[mikk]

Alder Lake-S supports both DDR4 and DDR5.

 

[Hulk]

I realize there are a lot of "garbage" leaked benchmarks out there but do you think this one has any validity?

Intel Core i7-11700K Rocket Lake 8 Core CPU Benchmarks Leak Out in Geekbench, Faster Than AMD Ryzen 7 5800X In Both Single & Multi-Threaded Performance

The latest benchmarks of Intel's Core i7-11700K 8 Core & 11th Gen Rocket Lake Desktop CPU have leaked out within Geekbench.

wccftech.com

I did some quick calcs for fun.

CPU Name	Geekbench Single-Thread (1T)	Clock	MHz/Geekbench Point	Geekbench Multi-Thread (nT)	Performance Difference Vs (1T)	Performance Difference Vs (nT)
Intel Core i7-11700K	1810	5000	2.76	11304	100%	100%
AMD Ryzen 9 5950X	1672	4900	2.93	16515	108%	68%
AMD Ryzen 7 5800X	1663	4700	2.83	10361	109%	109%
Intel Core i9-10900K	1405	5300	3.77	10967	129%	103%
Intel Core i7-10700K	1349	5100	3.78	8973	134%	126%
Comet Lake vs Comet Lake	10700k	10900k
Geekbench 1T	3.78	3.77	100.2%
10700k +0.2% (Should be a tie)
Zen 3 vs Zen 3	5950x	5800x
Geekbench 1T	2.93	2.83	103.7%
5800x +3.7% (Should be a tie)
Rocket Lake vs Zen 3	11700k	5800x
Geekbench 1T	2.76	2.83	102.3%
10700k +2.3%
Rocket Lake vs Comet Lake	11700k	10700k
Geekbench 1T	2.76	3.77	136.6%
11700k +36.6%

 

[shady28]

I realize there are a lot of "garbage" leaked benchmarks out there but do you think this one has any validity?

Intel Core i7-11700K Rocket Lake 8 Core CPU Benchmarks Leak Out in Geekbench, Faster Than AMD Ryzen 7 5800X In Both Single & Multi-Threaded Performance

The latest benchmarks of Intel's Core i7-11700K 8 Core & 11th Gen Rocket Lake Desktop CPU have leaked out within Geekbench.

wccftech.com

I did some quick calcs for fun.

CPU Name	Geekbench Single-Thread (1T)	Clock	MHz/Geekbench Point	Geekbench Multi-Thread (nT)	Performance Difference Vs (1T)	Performance Difference Vs (nT)
Intel Core i7-11700K	1810	5000	2.76	11304	100%	100%
AMD Ryzen 9 5950X	1672	4900	2.93	16515	108%	68%
AMD Ryzen 7 5800X	1663	4700	2.83	10361	109%	109%
Intel Core i9-10900K	1405	5300	3.77	10967	129%	103%
Intel Core i7-10700K	1349	5100	3.78	8973	134%	126%
Comet Lake vs Comet Lake	10700k	10900k
Geekbench 1T	3.78	3.77	100.2%
10700k +0.2% (Should be a tie)
Zen 3 vs Zen 3	5950x	5800x
Geekbench 1T	2.93	2.83	103.7%
5800x +3.7% (Should be a tie)
Rocket Lake vs Zen 3	11700k	5800x
Geekbench 1T	2.76	2.83	102.3%
10700k +2.3%
Rocket Lake vs Comet Lake	11700k	10700k
Geekbench 1T	2.76	3.77	136.6%
11700k +36.6%

I'm beginning to think someone is overclocking their 11700K (seriously).

 

[tamz_msc]

We finally got a Willow Cove score in the Handbrake bench.
Pretty interesting. Yes it's mobile and yes it's showing considerable improvement over Skylake desktop. That Kaby Lake score is from my Surface Laptop 2, it's a bit of an outlier but I checked it 4 times? If there is more than one score for a core in the chart I averaged them. I didn't average the kaby lake with the other Skylakes because it seemed out of sorts.

Average by core - fps/core/GHz (fps per available GHz)
Zen 3 (Vermeer)	0.241​	100%​
Tiger Lake (Willow Cove)	0.217​	90%​
Zen 2 (Rome)	0.216​	90%​
Kaby Lake R (Skylake)	0.177​	73%​
Haswell	0.156​	65%​
Comet Lake (Skylake)	0.155​	64%​
Zen+ (Summit Ridge)	0.149​	62%​

I think it can go higher. I was probably held back by the 2666MHz CL19 memory which went down to 2133MHz CL15 dynamically during the benchmark. With LPDDR4x Tiger Lake can match if not beat ZEN 3 probably.

 

[Bouowmx]

I realize there are a lot of "garbage" leaked benchmarks out there but do you think this one has any validity?

For Geekbench, it's more helpful to pay attention to the integer and floating-point scores, rather than the overall score.

 

[dmens]

I really should stop feeding the trolls, but "PL" stands for "power limit". It's not a recommendation. Again, if you actually had the experience you claim to, I would not have to explain this.

And yes, if you increase the power the CPU's allowed to draw, you need motherboards (and cooling solutions) capable of handling that. For OEMs, who generally design as close to the minimum as possible, that translates to new motherboards. They don't like that.

Heh. The limit is a cooling recommendation because that is the power level the PCU attempt to turbo towards during the time spent in PL2. It does not mean every part will actually reach that limit, nor does it actually say anything about the performance achieved while attempting to reach that limit, which is half the equation on power efficiency. Duh.

By the way, the fact that the motherboard can deliver adequate amperage to the socket for one CPU as another says absolutely nothing about the relative power efficiency the two different devices. It merely means neither CPU exceeded that spec with guardbanding. If your conclusion is that not requiring a new power delivery spec means it is just as power efficient, or even consumes the same amount of power, that is 100% incorrect.

 

[Gideon]

Why are we even having this power discussion? Thet Have the same PL2 of 250W, almost exactly the same (all core) turbo frequencies and 2 less cores. All seems to point to Rocket Lake having roughly the same power draw for 8 core (AVX-512 workloads) that 10 core Comet Lake has (for AVX2 workloads).

 

[cortexa99]

RKL Q2 availability?

https://twitter.com/x/status/1343596463717289984

 

[coercitiv]

RKL Q2 availability?

I'm not optimistic about RKL availability but I wouldn't trust wccftech with any leak whatsoever. If we don't get something from a half decent source I'd rather consider availability an unknown variable at this point.

 

[uzzi38]

I'm not optimistic about RKL availability but I wouldn't trust wccftech with any leak whatsoever. If we don't get something from a half decent source I'd rather consider availability an unknown variable at this point.

Hassan has good sources amongst mobo OEMs. There's a good possibility he's correct.

 

[coercitiv]

Hassan has good sources amongst mobo OEMs. There's a good possibility he's correct.

He's also willing to lend his ear to anything, so I'd rather take my chance with somebody holding a better track record.

 

[lobz]

Let's just say I'm happy you were a low tier employee at Intel and weren't in charge of any real decisions involving architecture back-porting. Otherwise, RKL-S would've been toast. So, just be content doing what you do and stop bad-mouthing people with real decisions to make. Truce?

Why are you trying so hard to embarrass yourself?

 

[lobz]

Oh my, the 1800+ ST score in GB is really high! Actually points to Cypress Cove having slightly higher IPC than Willow Cove, which is truly perplexing 😂 here's me eagerly waiting for comprehensive testing.

 

[Hulk]

Oh my, the 1800+ ST score in GB is really high! Actually points to Cypress Cove having slightly higher IPC than Willow Cove, which is truly perplexing 😂 here's me eagerly waiting for comprehensive testing.

I was confused about this as well. I was educated about this earlier in this thread. I learned that Willow has a larger but higher latency cache structure vs Cyprus. While it can be beneficial in some applications, there are many where the smaller, lower latency cache structure provides better IPC.

 

[AMDK11]

It should also be added that CypressCove has an inclusive cache, i.e. L1 is copied to L2 and L2 to L3 so that, for example, if any of the cores asks for the currently performed L1 core data, e.g. a) it is enough to check L3 instead of directly sending a request to L1 which causes downtime in operations on the L1 core, e.g. a). Additionally, if the core needs to re-need data that has been processed, it will most likely find it in L2 or L3 instead of reaching for much slower RAM.

WillowCove has a non-inclusive cache which means that L2 does not contain a copy of L1 and L3 does not contain a copy of L2 so either core must request access to L1 or get data from RAM. The large 1.25MB L2 and 3MB L3 are supposed to compensate for this, but are much slower than the 512KB L2 and 2MB L3.

 

[Thala]

It should also be added that CypressCove has an inclusive cache, i.e. L1 is copied to L2 and L2 to L3 so that, for example, if any of the cores asks for the currently performed L1 core data, e.g. a) it is enough to check L3 instead of directly sending a request to L1 which causes downtime in operations on the L1 core, e.g. a). Additionally, if the core needs to re-need data that has been processed, it will most likely find it in L2 or L3 instead of reaching for much slower RAM.

WillowCove has a non-inclusive cache which means that L2 does not contain a copy of L1 and L3 does not contain a copy of L2 so either core must request access to L1 or get data from RAM. The large 1.25MB L2 and 3MB L3 are supposed to compensate for this, but are much slower than the 512KB L2 and 2MB L3.

Even with an inclusive cache, there is no guarantee that the most recent update is found in the L2/L3. In fact updates are only done in the L1 and only flushed to L2 on a coherency request with Intels MESI coherence protocol or provided directly L1->L1 on ARMs MOESI protocol.

 

[naukkis]

Even with an inclusive cache, there is no guarantee that the most recent update is found in the L2/L3. In fact updates are only done in the L1 and only flushed to L2 on a coherency request with Intels MESI coherence protocol or provided directly L1->L1 on ARMs MOESI protocol.

MESI-protocol can also make direct L1-L1 via migratory optimizations- by moving that dirty line from core to core. ARM also did that with MESI-states, so far only AMD does have used O-state commonly and in Zen they can do both, copy dirty line (O) and move that dirty line (D in their case as they also support O-state). Doing both obviously needs some kind of tracking of dirty lines behavior but complex schemes are nowadays doable.....

But in either case line transfer from L1 to other cores L1 is by through their core-to-core interconnection - so basically through L2 and L3 caches in case of cpu's that have core-to-core connections handled by lower cache levels.