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Discussion Intel current and future Lakes & Rapids thread

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LightningZ71

Senior member
Mar 10, 2017
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That is the rub. It’s very difficult to compare laptops that have the same cpu and dGPU because the laptops can differ drastically in configured TDP, cooling, RAM specs and settings, and even have certain reductions in dGPU capability that aren’t advertised. That’s why you have to wait for benchmarks and tests in the wild.
 

IntelUser2000

Elite Member
Oct 14, 2003
7,166
1,738
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I thought Renoir HS was 35 watts and the regular H parts were 45 watts?
That's why I said default is not relevant. The manufacturer can set it at levels way different than what the spec sheet says. The H version runs at 60W+ in some laptops.

That's not a bad thing, as it gives them design flexibility. Rather than making a design and making everything else around it, you can adjust the TDP levels to what is needed.
 

Cardyak

Member
Sep 12, 2018
33
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Intel have published an interesting paper about Focused Value Prediction and the implications it has for future improvements to CPU architecture:


Just some snippets here that I personally found interesting:

"Value Prediction was proposed to speculatively break true data dependencies, thereby allowing Out of Order (OOO) processors to achieve higher instruction level parallelism (ILP) and gain performance. State-of-the-art value predictors try to maximize the number of instructions that can be value predicted, with the belief that a higher coverage will unlock more ILP and increase performance."

"FVP significantly reduces the area, power and design complexity of implementing value prediction, while still delivering large performance gains. Detailed simulation results on 60 diverse, single threaded workloads, show that we value predict about 25% of all load instructions and deliver 3.3% performance gain over a baseline similar to the Intel Skylake processor. This performance grows substantially to 8.6% when we simulate a futuristic processor that has double the OOO resources of Skylake. "
 

jpiniero

Diamond Member
Oct 1, 2010
8,400
1,439
126

OK, this is funny. New rumor saying that the Rocket Lake i7 will be 8C12T. It's probably a typo but it is possible. Intel with Comet Lake added the ability to turn off HT on a per core basis.

The i9 would be 8C16T and i5 would be 6C12T.
 

Ajay

Diamond Member
Jan 8, 2001
7,434
2,612
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Even funnier will be CML i9 vs RKL i9 in MT loads, although if that segmentation is true then it may actually be good news for RKL performance.
Pretty sure it'll fall behind. I'm thinking Intel is just going for the highest ST possible, so that they 'may' jump ahead of Zen3.
 
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mikk

Platinum Member
May 15, 2012
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Intel is not in a position for a segmentation like 8/12 because they need everything they have, but this could be a typo.
 

DrMrLordX

Lifer
Apr 27, 2000
16,501
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Even funnier will be CML i9 vs RKL i9 in MT loads, although if that segmentation is true then it may actually be good news for RKL performance.
Let's face it, Comet Lake-S ain't all that. I mean sure it works, it's . . . quite a bit faster than Kabylake and Skylake in MT just from the core count, but Intel should be able to at least match it in MT with 8c Rocket Lake. If they can at least keep the heat flux down to equal the 10900k it won't be a terrible chip. It just will have no real value outside of premium desktop and gaming. That kind of MT performance in 2021 is just not that special anymore.
 
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ondma

Golden Member
Mar 18, 2018
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Let's face it, Comet Lake-S ain't all that. I mean sure it works, it's . . . quite a bit faster than Kabylake and Skylake in MT just from the core count, but Intel should be able to at least match it in MT with 8c Rocket Lake. If they can at least keep the heat flux down to equal the 10900k it won't be a terrible chip. It just will have no real value outside of premium desktop and gaming. That kind of MT performance in 2021 is just not that special anymore.
Isnt that what it is designed for?
 

IntelUser2000

Elite Member
Oct 14, 2003
7,166
1,738
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OK, this is funny. New rumor saying that the Rocket Lake i7 will be 8C12T. It's probably a typo but it is possible.
The gap between the two in MT is going to be less than 10%. It probably makes a lot of sense to go for the i7 part if you are going to get gaming system.
 

TheGiant

Senior member
Jun 12, 2017
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DrMrLordX

Lifer
Apr 27, 2000
16,501
5,479
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Can you elaborate? I thought your sentence " It just will have no real value outside of premium desktop and gaming " was the point you were making.
Rocket Lake-S will be Intel's non-HEDT desktop flagship until they are able to launch Alder Lake-S. It is designed for all computing tasks. Not just gaming. It is also designed to meet the needs of the entire market - DiY, various different OEMs, you name it.

If it fails in a particular market, it fails due to Intel's incompetence. Not due to it being a chip "designed for gaming". As recently as 2018, Intel had the fastest non-HEDT desktop chip on the market in the 9900k. If you wanted to encode media, render, or game, it was faster than the 2700x or anything else in the desktop market. Rocket Lake-S is tasked with nothing less than occupying the same space on the market. It will fail.
 

DrMrLordX

Lifer
Apr 27, 2000
16,501
5,479
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I still cannot wrap my head around big.Little for a desktop cpu, well, certainly not for a high performance cpu.
We'll see. Having 8c Golden Cove won't be a bad thing, and with Tremont looking kinda okay actually, Gracemont could be pretty good. It will be a change for sure, though, and it may not stack up all that well against chips coming out this year, much less those currently scheduled for 2021 . . .
 

jpiniero

Diamond Member
Oct 1, 2010
8,400
1,439
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Rocket Lake-S will be Intel's non-HEDT desktop flagship until they are able to launch Alder Lake-S. It is designed for all computing tasks. Not just gaming. It is also designed to meet the needs of the entire market - DiY, various different OEMs, you name it.
Gaming probably drove the core count decision. Well, that and the power draw.

It sounds like there's going to be Comet Lake rebrands as well so you shouldn't be surprised the bulk of the OEM desktop market use that instead.
 

IntelUser2000

Elite Member
Oct 14, 2003
7,166
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It will be a change for sure, though, and it may not stack up all that well against chips coming out this year, much less those currently scheduled for 2021 . . .
It's weird Alderlake is an 8+8 configuration. That's actually the same amount of ring stops as 10 core Cometlake, possibly meaning they see ringbus as the limiter to scaling above that, and mesh doesn't work well for client.

Alderlake update:
Targeting Alder Lake meanwhile is flipping on MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, CLDEMOTE, PTWRITE, WAITPKG and SERIALIZE instruction set support.
For Sapphire Rapids

Sapphire Rapids enables: MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE and TSXLDTRK instruction set support.
It's interesting it does not talk about AVX-512 for Alder Lake. So its very likely both Golden Cove and Gracemont supports AVX-2 but not AVX-512. AVX-512 continues to be an instruction for HPC.
 
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jpiniero

Diamond Member
Oct 1, 2010
8,400
1,439
126
It's interesting it does not talk about AVX-512 for Alder Lake. So its very likely both Golden Cove and Gracemont supports AVX-2 but not AVX-512. AVX-512 continues to be an instruction for HPC.
The target for Cannon/Ice/Tiger do mention AVX-512. As Phoronix mentions it's more likely that it's the LCD between it and Gracemont than AVX-512 being removed because Small doesn't support it. Gracemont is not mentioned at all yet.

Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,
RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,
VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and AVX512VP2INTERSECT instruction
set support.
 

DrMrLordX

Lifer
Apr 27, 2000
16,501
5,479
136
Gaming probably drove the core count decision. Well, that and the power draw.
I think it was down to power draw and die size. Transistor count per core is up with both Sunny and Willow Cove. Moving to the uh . . . whatever it is they're really using in Rocket Lake-S left them with less die real estate for cores. There is likely no realistic way for them to go beyond 8c on 14nm with their newer core designs. Gaming performance is just an excuse. They're hemmed in by process.

edit: oh also I agree that Golden Cove probably has AVX512 supported in silicon. If Gracemont doesn't, then yeah they'll just have to disable AVX512 all around. So ironically, Cannonlake; IceLake; and Tigerlake have AVX512 support but Alder Lake won't.

It's weird Alderlake is an 8+8 configuration. That's actually the same amount of ring stops as 10 core Cometlake, possibly meaning they see ringbus as the limiter to scaling above that, and mesh doesn't work well for client.
An interesting observation, though mesh can work well for client at higher mesh speeds and with cache configurations aimed at client workloads (read: not what you find on Skylake-SP and its descendants).
 
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jpiniero

Diamond Member
Oct 1, 2010
8,400
1,439
126

So Alder Lake does support AVX-512 but it gets disabled when running in hybrid mode.
 

DisEnchantment

Senior member
Mar 3, 2017
652
1,452
106
From GCC changes submitted by Intel, it seems the compiler will not generate AVX512 instructions when the -march=alderlake.
They are probably targeting the common denominator. Which then raises some other questions for those hybrid core configs.
How Intel tackles this segmentation should be interesting to follow.
‘tigerlake’
Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and AVX512VP2INTERSECT instruction set support.

‘sapphirerapids’
Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE and TSXLDTRK instruction set support.

‘alderlake’
Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, CLDEMOTE, PTWRITE, WAITPKG and SERIALIZE instruction set support.
There is going to be more dark silicon on the hybrid configs? and what is the gain then if they can't use these instructions in the first place.
This seems to be like a generic problem to be solved going forward. HSA has similar problems.

Makes me wonder if there is going to be disintegration of the frontend and backend. Would probably be messy.

On SW side, they could possibly have illegal opcode trap and migrate the thread context if it is on the smaller core, but not going to be good. Not thought through, just an idea.

EDIT:
Just some points to the post from @IntelUser2000
 
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