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Discussion Intel current and future Lakes & Rapids thread

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lobz

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Feb 10, 2017
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I'd say 8 cores max. 8 cores alone would push the die size up to 200mm^2, unless they cut out some of the bloat like Thundebolt 4 or the IPU. And this is accounting for a trimmed down iGPU.
That's why I said I can't really see it happening. ~200mm2 on 10nm is HUUUGE for a mobile CPU. Unless it's the Intel I9 11000110100000000XXE+++ in a laptop for $9,999,-
But as a whole CPU family, not realistic.
 

coercitiv

Diamond Member
Jan 24, 2014
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Does anyone have the numbers for an area comparison between Skylake, Sunny Cove and Willow Cove? (core + cache only)
 

Thala

Golden Member
Nov 12, 2014
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According to Wikichip, Skylake is 9 and Sunny Cove is 7. Willow looks like it's about 10.
It should be noted, that with these numbers Skylake is on 14nm while the Coves are on 10nm. I guess you can easily half the Skylake size when scaling to 10nm.
 

uzzi38

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Oct 16, 2019
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According to Wikichip, Skylake is 9 and Sunny Cove is 7. Willow looks like it's about 10.
A bit over 10mm^2 I'd say.

Skylake is about 8.91mm^2 per core (using the height for the 2 core group on Wikichip, because it includes L3 cache, not sure if the first does)
Ice Lake is about 6.91mm^2 per core
Tiger Lake's L2 is 2.5x that of Ice Lake and it's L3 is 1.5x that of Ice Lake, (using paint) it looks kinda like a ~20-25% increase in die space per core.
 

IntelUser2000

Elite Member
Oct 14, 2003
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Well, for now, Tiger Lake seems more real than Rocket Lake. Not really sure now if entire Rocket Lake line up is going to happen.
Well, presumably Rocket is basically Tiger Lake but 14 nm and using chiplets. From a reducing the 14 nm shortage perspective, releasing Tiger Lake makes sense.
Sigh.

Obviously I meant Tigerlake-H. For -U it'll not only release but earlier than Icelake-U did.

Skylake is about 8.91mm^2 per core (using the height for the 2 core group on Wikichip, because it includes L3 cache, not sure if the first does)
Ice Lake is about 6.91mm^2 per core
Easiest is using 4 core groups. Skylake is 50.3mm2 and Icelake is 30.7mm2. I think Tigerlake-U grows to 40mm2 for the group.

Core size excluding L3 is 8.9mm2 for SKL and 5mm2 for ICL.

We could speculate that Sunny and Willow Cove both were aiming for 5GHz operation. If they aim it for <4.5GHz, then cores can be smaller. If they aim for <3GHz like with mobile chips the core sizes should be quite competitive. Of course that requires designing the whole chip for such frequencies from the scratch.
 
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lobz

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Easiest is using 4 core groups. Skylake is 50.3mm2 and Icelake is 30.7mm2. I think Tigerlake-U grows to 40mm2 for the group.

Core size excluding L3 is 8.9mm2 for SKL and 5mm2 for ICL.

We could speculate that Sunny and Willow Cove both were aiming for 5GHz operation. If they aim it for <4.5GHz, then cores can be smaller. If they aim for <3GHz like with mobile chips the core sizes should be quite competitive. Of course that requires designing the whole chip for such frequencies from the scratch.
5 GHz operation is an accidental adverse effect of having to optimize 14nm waaaaaaaaaaaay-way-way beyond its original goals, I sincerely doubt it has ever been a core feature of either Sunny or Willow cove.

There is also obviously no separate architectural designs for <3 GHz mobile and 5 GHz desktop, so in the end I have no idea what you're implying regarding the correspondence between per core silicon area and frequencies.
 
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jpiniero

Diamond Member
Oct 1, 2010
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As for Tiger-H, I thought about it some more and came to the conclusion that if it does make it to release, it will be 8 cores and no IGP. Maybe it will include Rocket Lake's 14 nm IGP chiplet. Maybe.

I think Intel intended for Comet-H to remain on the market for some time but between the 14 nm shortage and Renoir they decided that they needed to revive it and just did the work to remove the IGP from the die.
 

SAAA

Senior member
May 14, 2014
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A bit over 10mm^2 I'd say.

Skylake is about 8.91mm^2 per core (using the height for the 2 core group on Wikichip, because it includes L3 cache, not sure if the first does)
Ice Lake is about 6.91mm^2 per core
Tiger Lake's L2 is 2.5x that of Ice Lake and it's L3 is 1.5x that of Ice Lake, (using paint) it looks kinda like a ~20-25% increase in die space per core.
I definitely hope that for a trade of 20-25% in core size from Ice to Tiger lake we get something more than 0-5% IPC like early test hint at. They will affect some tests and use cases sure but the engine running them should see other improvements.
Unless they are gone crazy and only keep all of those for Golden cove, with Tiger getting mostly larger caches beforehand.

5 GHz operation is an accidental adverse effect of having to optimize 14nm waaaaaaaaaaaay-way-way beyond its original goals, I sincerely doubt it has ever been a core feature of either Sunny or Willow cove.

There is also obviously no separate architectural designs for <3 GHz mobile and 5 GHz desktop, so in the end I have no idea what you're implying regarding the correspondence between per core silicon area and frequencies.
A core that can run 5GHz can definitely do 3GHz more efficiently on the same node. I'm not so sure of the opposite if you design it since the beginning to top at 3...
Also another hint: power efficient nodes variants exist, Intel used them for Atom cores, doing the same with core products might be a bad idea. Density optimisations too might be a bad idea for such scalable, power hungry cores, who are used from tablets to water cooled desktops.
 
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IntelUser2000

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Oct 14, 2003
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There is also obviously no separate architectural designs for <3 GHz mobile and 5 GHz desktop, so in the end I have no idea what you're implying regarding the correspondence between per core silicon area and frequencies.
Sure they can. At the architectural level, you can reduce the number of pipeline stages. On Core and Zen they are at 18-19 stages. Cortex A76 has 13 stages, and A77 at 11 stages. Each additional pipeline stages result in increased penalty from branch misprediction, but increases clocks.

Layout-wise you can optimize for high clocks too. The Zen2 core is noticeably more compact compared to the latest Intel cores. Spreading them out reduces heat concentration. Supporting this theory is the Atom cores(targetted for 3GHz) being extremely compact. In fact, they are competitive with ARM cores in perf/area.*

They may not be able to reach 5GHz right away, but doing 4.7-4.8GHz is still noticeably better than the struggles Zen2 chips are having with high frequencies.

*0.835mm2 for 14nm Airmont, 1.2mm2 for Goldmont.
 

mikk

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May 15, 2012
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As for Tiger-H, I thought about it some more and came to the conclusion that if it does make it to release, it will be 8 cores and no IGP. Maybe it will include Rocket Lake's 14 nm IGP chiplet. Maybe.
According to github Tigerlake H is an 8+1 design just like RKL-S. I don't expect a chiplet neither for TGL-H nor RKL-S.
 

lobz

Golden Member
Feb 10, 2017
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Sure they can. At the architectural level, you can reduce the number of pipeline stages. On Core and Zen they are at 18-19 stages. Cortex A76 has 13 stages, and A77 at 11 stages. Each additional pipeline stages result in increased penalty from branch misprediction, but increases clocks.

Layout-wise you can optimize for high clocks too. The Zen2 core is noticeably more compact compared to the latest Intel cores. Spreading them out reduces heat concentration. Supporting this theory is the Atom cores(targetted for 3GHz) being extremely compact. In fact, they are competitive with ARM cores in perf/area.*

They may not be able to reach 5GHz right away, but doing 4.7-4.8GHz is still noticeably better than the struggles Zen2 chips are having with high frequencies.

*0.835mm2 for 14nm Airmont, 1.2mm2 for Goldmont.
Sorry, I was not fully concrete :) I meant Intel did not design a separate Sunny and Willow for mobile and another Sunny + Willow for Desktop.
 

DrMrLordX

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Apr 27, 2000
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If Intel actually does an 8c TigerLake-H, is that the 10nm desktop chip we'll see from them this year, ala Broadwell-C?
 

jpiniero

Diamond Member
Oct 1, 2010
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Please note that CPU performance was severely throttled on battery. The multi-core score dropped from 783 to just 262 points, and the single-core score to a meager 49 points. Average clock speeds were around 2.4 to 2.5 GHz.

Not sure if this is 10 nm being 10 nm or Microsoft being Microsoft. But throttling that bad in battery mode on a tablet is hilarious.
 

Tabalan

Member
Feb 23, 2020
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If Intel actually does an 8c TigerLake-H, is that the 10nm desktop chip we'll see from them this year, ala Broadwell-C?
There is none 10nm desktop? For desktop, in 2020 you'd get Comet Lake in 14 nm. According to leaks, Rocket Lake (Willow Cove in 14 nm) should get announced this year, next year Adler Lake. Hard to tell right now, I'm not sure Intell will announce 10th gen and 11th gen desktop same year.

10 nm for now only mobile (TGL-U/Y/H).
 

uzzi38

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Oct 16, 2019
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If Intel actually does an 8c TigerLake-H, is that the 10nm desktop chip we'll see from them this year, ala Broadwell-C?
That would be the logical assumption given how -H and -S share the same dies traditionally. The only problem I have is that while TGL-H there were whispers of months ago (and also the reason I didn't rule out proper 10nm desktops fully), nobody seems to know about a -S version.

Alder Lake-S was booted off roadmaps but then necromanced once more a couple of months ago. But Tiger Lake-S? Dead silence.

At this point who knows, seriously.
 
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extide

Senior member
Nov 18, 2009
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I'd say 8 cores max. 8 cores alone would push the die size up to 200mm^2, unless they cut out some of the bloat like Thundebolt 4 or the IPU. And this is accounting for a trimmed down iGPU.
8c Coffee Lake is only ~174 mm² die size -- so even with increasing the core and gpu transistor count by quite a bit I doubt it would shoot over 200mm. BUT, even if it did Intel has put pretty large dies in laptops before, as well -- Clarksfield 4-core die was same die as desktop Lynnfield -- 296mm^2.
 

jpiniero

Diamond Member
Oct 1, 2010
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8c Coffee Lake is only ~174 mm² die size -- so even with increasing the core and gpu transistor count by quite a bit I doubt it would shoot over 200mm. BUT, even if it did Intel has put pretty large dies in laptops before, as well -- Clarksfield 4-core die was same die as desktop Lynnfield -- 296mm^2.
200 mm2 would be crazy on 10 nm.
 

uzzi38

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Oct 16, 2019
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They already sell the Agilex FPGA line on 10nm, and I would certainly expect those to be at least 200mm^2.
Those FPGAs aren't sold at the kinds of prices mobile APUs would be.

200mm^2 on 10nm isn't crazy because it's a large dies size (it's not), it's because it would be expensive as all hell because of the craptastic yields Intel'd been having on 10nm thus far. Especially when we're talking about a chip with a larger focus on CPU than iGPU (GPUs tend to be easier to cut down due to yields as they're multiple small repeating blocks).
 

extide

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Those FPGAs aren't sold at the kinds of prices mobile APUs would be.

200mm^2 on 10nm isn't crazy because it's a large dies size (it's not), it's because it would be expensive as all hell because of the craptastic yields Intel'd been having on 10nm thus far. Especially when we're talking about a chip with a larger focus on CPU than iGPU (GPUs tend to be easier to cut down due to yields as they're multiple small repeating blocks).
Sure, they do sell those for significantly more money -- but it has also been 6 months since then and when is Tiger Lake going to ship? Another 6 months from now? Getting 200mm^2 dies at consumer pricing should not be an issue at that point. It's not like the 10nm process is frozen in time, nor is a 200mm^2 die particularly large in the grand scheme of things.
 
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