Discussion Intel current and future Lakes & Rapids thread

[krumme]

Thunderbolt and the IPU does take up a ton of space. AVX-512 and bfloat and all that does take up a little bit I imagine but it can't be that much... it's not like they added the second AVX-512 unit like they did with Skylake Server.

Its pretty darn difficult to judge and its a bit of a stupid comparison in itself if TTM, designcost, sales volume, fmax and density of process is not taken into consideration. As is, its pretty meaningless.

At the end of the day i would say margins is a better indicator if any, but we dont know those specific for those new apu. Surely earlier kbl 2c 4c must have had to be a good deal superior to amd solution raven or picasso as can be indicated by overall margins. I am pretty sure the Intel design is very efficient mm2 vise, as it have always been, but its to early to tell, and the compettition and therefore benchmark is quite different this time.

 

[beginner99]

I am pretty sure the Intel design is very efficient mm2 vise, as it have always been,

This is the strange things about them putting AVX512 in consumer cores. It's not efficent die space wise and most users will never use it.

 

[JoeRambo]

It's not efficent die space wise and most users will never use it.

A bit of chicken and egg problem, once mainstream cores have AVX512 support, software will follow. Some of it might be subtle like GPU drivers having extra AVX512 path, others more obvious like some media library or software and only then it might appear in games and emulation.
Very common misconception about AVX512 is that is "wider" AVX2 (that had 256), when in fact it is much more, enabling new classes of algorithms to get vectorized, various useful instructions like VBMI2 etc.

 

[jpiniero]

At the end of the day i would say margins is a better indicator if any, but we dont know those specific for those new apu.

It's pretty obvious that Renoir has better margins than Ice/Tiger because of the bad 10 nm yields.

 

[FriedMoose]

Tiger Lake U with 128MB eDRAM? Seems like an Iris Plus version:

: SiSoftware Official Live Ranker

ranker.sisoftware.co.uk

 

[IntelUser2000]

Tiger Lake U with 128MB eDRAM? Seems like an Iris Plus version:

They are supposed to be moving to HBM2 very soon. eDRAM is a temporary solution until they can get those ready.

Whatever the latency benefits there may be with the eDRAM, its really about accelerating graphics rather than CPU. That trade off allows them to put 16x capacity dedicated VRAM if they only used the 2GB variant.

 

[tamz_msc]

Tiger Lake U with 128MB eDRAM? Seems like an Iris Plus version:

: SiSoftware Official Live Ranker

ranker.sisoftware.co.uk

How do we know that it's EDRAM?

 

[IntelUser2000]

How do we know that it's EDRAM?

eDRAM is less dense because its using the same process rules for logic.

DRAM's minimum capacity nowadays are multiples of the largest eDRAM. 128MB also happens to be the capacity of Intel's largest eDRAM.

Of course, maybe its not eDRAM but just 128MB system memory dedicated. Does make sense with 17GB/s of bandwidth.

 

[tamz_msc]

eDRAM is less dense because its using the same process rules for logic.

DRAM's minimum capacity nowadays are multiples of the largest eDRAM. 128MB also happens to be the capacity of Intel's largest eDRAM.

Of course, maybe its not eDRAM but just 128MB system memory dedicated. Does make sense with 17GB/s of bandwidth.

I think its 128MB allocated system RAM, based on the memory bandwidth number. EDRAM should be higher. Besides I don't see any added benefit of adding EDRAM when the design already supports LPDDR5. Last time around with Broadwell-C we saw its EDRAM offer the same BW as DDR4-3200.

 

[uzzi38]

It's definitely system memory.

In any case, that stuff's boring, here's something good for you lot:

https://twitter.com/i/web/status/1215704970701328384

 

[IntelUser2000]

I think its 128MB allocated system RAM, based on the memory bandwidth number. EDRAM should be higher. Besides I don't see any added benefit of adding EDRAM when the design already supports LPDDR5. Last time around with Broadwell-C we saw its EDRAM offer the same BW as DDR4-3200.

eDRAM actually offers double that, because its bi-directional. Plus being a cache there's this:

Intel Iris Pro 5200 Graphics Review: Core i7-4950HQ Tested

www.anandtech.com

ntel claims that it would take a 100 - 130GB/s GDDR memory interface to deliver similar effective performance to Crystalwell since the latter is a cache.

TigerLake LP GT3 : 0x9A52.

Maybe that's the one that'll have HBM2.

 

[RetroZombie]

eDRAM actually offers double that, because its bi-directional.

Too good to be true, intel saw with broadwell they were giving us a much better cpu than their own hedt, so L4 cache bye bye.

And also this:
- 128MB of L4 cache for the cpu great!
- 128MB of memory for the gpu, meh!

Even if that memory would give 100TB/s it's just 128MB and that's nothing for the gpu, even 1GB DDR4 with just 32bit/64bit bus would be faster and cheaper for what it is it's intent.

 

[jpiniero]

Intel: 28 W Ice Lake Core i7-1068G7 Coming Q1

www.anandtech.com

So now Intel is saying that actual products using the 1068G7 and Icelake Y will be available soon. And yet they've also claimed that Tigerlake products are coming in Summer, right?

I'm not sure I believe Intel, heh.

 

[yeshua]

Intel: 28 W Ice Lake Core i7-1068G7 Coming Q1

www.anandtech.com

So now Intel is saying that actual products using the 1068G7 and Icelake Y will be available soon. And yet they've also claimed that Tigerlake products are coming in Summer, right?

I'm not sure I believe Intel, heh.

Intel has never said a word about TGL CPUs release date/availability except for very vague roadmaps.

TGL or not, they first have to solve their 10nm node. It still doesn't work the way Intel needs it to work. I believe yield is still horrible 'cause otherwise we'd have had dozens of new ICL laptops released at CES 2020 while we had just two models. Not a single ICL Y CPU has been released so far: It speaks volumes about availability and Intel confidence in the node. I've got a feeling they've long decided to keep the 10nm node as a sort of consolation for investors and shareholders while they are hard at work trying to fast forward to the 7nm node.

That might also mean we won't see any desktop CPUs faster than the upcoming 10core CML in the next two years.

 

[jpiniero]

That might also means we won't see any desktop CPUs faster than the upcoming 10core CML in the next two years.

You still got Rocket Lake. And while the Emergency Edition memes will be glorious, it still should be a nice improvement in games. Note: should.

 

[mikk]

Errr... a Zen 2 core is 3.64 mm2 including L2 (per wikichip)... Sunny Cove is 6.91.Willow has to be bigger than that.

I'm talking about the entire chip and not just the CPU cores. And you can see that the impact from the CPU cores isn't huge, especially for AMD. The GPU is a much bigger size eater and Intels GPU should be quite a bit bigger in Tigerlake compared to 8 CU Vega.

TGL or not, they first have to solve their 10nm node. It still doesn't work the way Intel needs it to work. I believe yield is still horrible 'cause otherwise we'd have had dozens of new ICL laptops released at CES 2020 while we had just two models. Not a single ICL Y CPU has been released so far: It speaks volumes about availability and Intel confidence in the node. I've got a feeling they've long decided to keep the 10nm node as a sort of consolation for investors and shareholders while they are hard at work trying to fast forward to the 7nm node.

We will never see Icelake in high volume and Tigerlake is using a newer 10nm iteration, calling 10nm off is way too early therefore. Look in the tweakers roadmap, Icelake is labeled with "limited" early on, it's not for Tigerlake.

 

[yeshua]

We will never see Icelake in high volume and Tigerlake is using a newer 10nm iteration, calling 10nm off is way too early therefore. Look in the tweakers roadmap, Icelake is labeled with "limited" early on, it's not for Tigerlake.

I remember in the past Intel used to show working silicon up to 18 months before it was available in retail/etail - have you seen working TGL silicon? Intel desperately needs to win the minds and hearts of consumers and right now all the rage is AMD and their Zen2/Zen3 CPU/APUs.

 

[mikk]

I remember in the past Intel used to show working silicon up to 18 months before it was available in retail/etail - have you seen working TGL silicon? Intel desperately needs to win the minds and hearts of consumers and right now all the rage is AMD and their Zen2/Zen3 CPU/APUs.

Working fully enabled Tigerlake silicon is available since a long time now, there are lots of leaks in the wild, dev work is made with real hardware and Tigerlake presumably entered ES2 stage end of last year. A Computex launch seems realistic with first products in Q3.

 

[yeshua]

Working fully enabled Tigerlake silicon is available since a long time now, there are lots of leaks in the wild, dev work is made with real hardware and Tigerlake presumably entered ES2 stage end of last year. A Computex launch seems realistic with first products in Q3.

I'm not talking engineering samples. You can run ES even in a software emulator. I'm talking about complete devices like laptops or tablets.

 

[Dayman1225]

I'm not talking engineering samples. You can run ES even in a software emulator. I'm talking about complete devices like laptops or tablets.

Yes at CES. 2 Compal laptops and one folding screen concept were running TGL in Intels Keynote

 

[mikk]

Yes at CES. 2 Compal laptops and one folding screen concept were running TGL in Intels Keynote

And furthermore Intels reference vehicle platform is up and running since a long time which is used for driver and dev work, so yes there are complete devices.

 

[jpiniero]

I'm talking about the entire chip and not just the CPU cores. And you can see that the impact from the CPU cores isn't huge, especially for AMD. The GPU is a much bigger size eater and Intels GPU should be quite a bit bigger in Tigerlake compared to 8 CU Vega.

As they tried to tell you Renoir is a one chip solution, there's no PCH or chipset involved. You also get double the cores. It doesn't have Thunderbolt or a IPU like I mentioned.

 

[IntelUser2000]

I remember in the past Intel used to show working silicon up to 18 months before it was available in retail/etail - have you seen working TGL silicon? Intel desperately needs to win the minds and hearts of consumers and right now all the rage is AMD and their Zen2/Zen3 CPU/APUs.

I'm not talking engineering samples. You can run ES even in a software emulator. I'm talking about complete devices like laptops or tablets.

The two quotes are somewhat contradictory.

I think this is called shifting goalposts.

 

[jpiniero]

Should say that the Tweakers roadmap did have Tigerlake U and Y at the end of Q1 2020 (shipping to OEMs, not products available). Of course it's also very out of date now.

 

[IntelUser2000]

Ian has his article about Tigerlake's die.

Damn, so the Xe iGPU is even more area efficient than I thought. Seems to be under 50mm2. Actually, I'm getting 46-48mm2. So that's something like a 15% increase. In comparison, Gen 11 is 41-43mm2(41mm2 according to wikichip).

Ian is getting 146mm2 for the whole die, which is actually what I got. Out of the ~24mm2 increase, 8mm is due to Willow Cove cores. The increase is pretty much as I said back in post #3831

Guesses on Tigerlake if they move to the split L2 configuration.

Looks like Intel arranged Tigerlake in a way that's easier to add cores.

Addendum: At 38mm2 vs 48mm2, the CPU portion is almost as large as the GPU portion. So much for the iGPU taking up majority of die space. This is because the iGPU scales better.