That magical better gaming IPC is mostly down to memory latency. Why AMD wins in applications is mostly caches (not only size but also better bandwidth).
In applications the IPC absolutely isn't equal. 3700x is within s few precent of 9900K (and 3800x surprasses it) in most multithreaded production loads, despite 10% lower clocks. Just look at pudget adobe benches, any encoding/rendering benches.
Zen3 will be much better in gaming because of it's unified cache (should be nearly as big a jump as zen2) if they also manage to improve memory latency a little ...
It's basically what
@IntelUser2000 said: You test IPC by running single-threaded tests. You can run a separate SMT-enabled test if you so desire. The performance advantage AMD has over Intel at the moment stems from dedicating more resources to SMT, however, Intel negates those advantages with clock frequency.
* SMT is only useful in highly threaded parallel loads, which gaming is not, and this is why Intel shines in gaming despite losing in highly threaded loads; ringbus included. SMT-less 9700k is a great example of this. A 9900k with SMT disabled, is even faster in gaming.
* A performance per core test (whether that core has SMT or not, must not be done at a catch-clock (so to speak). It must be done at default clocks simply because of the fact that operational fmax is already baked into the design of a chip. Mainly due to power constraints, chip designers must carve a balance between frequency and ipc. If you bump ipc by making it wider, it'll be hard to reach target frequencies, and at the same power envelope. This is why I sneer at all those tests done at the same clocks. There are also questions of optimal frequencies for a given chip, especially when one takes into account such things as cache and memory subsystems. In view of this, Zen 2 may well be still behind Skylake in
single threaded (default clocks) tests as a measure of a chip's true real world performance, where ipc is treated as ipc x frequency. After all, no chip is going to run at ipc x 1, but rather ipc x n, where n is the optimal frequency the chip manufacturer has designed them to run in order to achieve a certain performance at a certain power envelope.
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