Intel 10nm and GF 7nm at IEDM 2017

[Arachnotronic]

Price cuts would be good, but I want to see improvements in single core performance, which I hope these new processes deliver in a significant way.

A great way to improve single-core performance is through architecture. Apple A11 Bionic big core at 2.4GHz offers similar single-thread performance to 4GHz Zen or 3.4GHZ Kabylake, and it does so at a fraction of the power that either of those two state-of-the-art x86 cores do.

What you should really be hoping for is continued architectural innovation from the x86 companies because today's processes are mainly improving in density and power consumption rather than peak frequency.

 

[raghu78]

A great way to improve single-core performance is through architecture. Apple A11 Bionic big core at 2.4GHz offers similar single-thread performance to 4GHz Zen or 3.4GHZ Kabylake, and it does so at a fraction of the power that either of those two state-of-the-art x86 cores do.

What you should really be hoping for is continued architectural innovation from the x86 companies because today's processes are mainly improving in density and power consumption rather than peak frequency.

Apple has the luxury of designing a core which needs to only run at a certain specific frequency. The entire design is optimized for the speeds that are most efficient on the underlying foundry process being developed. Since Apple develops the CPU core, OS, developer SDKs and APIs they can also make decisions like dropping 32 bit ARMv8 ISA support. This is unimaginable in a x86 CPU which will have to support so much legacy software. Apple's CPU cores are not meant to scale a wide range of perf / frequency/power budget. They are very good at the speeds at which they are manufactured and those speeds are very carefully chosen/optimized for max efficiency.

 

[Arachnotronic]

Apple has the luxury of designing a core which needs to only run at a certain specific frequency. The entire design is optimized for the speeds that are most efficient on the underlying foundry process being developed. Since Apple develops the CPU core, OS, developer SDKs and APIs they can also make decisions like dropping 32 bit ARMv8 ISA support. This is unimaginable in a x86 CPU which will have to support so much legacy software. Apple's CPU cores are not meant to scale a wide range of perf / frequency/power budget. They are very good at the speeds at which they are manufactured and those speeds are very carefully chosen/optimized for max efficiency.

The x86 benefit and curse -- the legacy software locks the market into basically two vendors, but the validation complexity of cores with all of that extra cruft in the ISA probably holds back performance.

 

[goldstone77]

Price cuts would be good, but I want to see improvements in single core performance, which I hope these new processes deliver in a significant way.

As far as the process goes Intel and GLobalFoundries will be similar in density. If Scotten Jones is right 7nm Ryzen will have 90.5 mn tr per sq mm, and Intel 103 mn tr per sq mm. Ryzen 7n fin height ~42nm, and Intel 10nm 46nm. I can't wait I'm excited!

 

[Hans de Vries]

It looks like Intel relaxed some layers from an original 36 nm to 44 nm and went from a 7.5 track design to a 6 track design to keep the Logic cell size equal. Then developed Cotact-over-active-gate to squeeze their existing libraries into less tracks.

The odd thing is the track size 272:36 = 7.56 while the only 36nm (M1) lines run parallel with the gates...

The floor-plans would look like this I presume:

So the processes of Intel and Globalfoundries would look even more equal. With the exception of Intel's unusual 2:3 ratio of the M1 (green) and CPP (red) pitches of 36nm/54nm = 2/3.

 

[goldstone77]

It looks like Intel relaxed some layers from an original 36 nm to 44 nm and went from a 7.5 track design to a 6 track design to keep the Logic cell size equal. Then developed Cotact-over-active-gate to squeeze their existing libraries into less tracks.

The odd thing is the track size 272:36 = 7.56 while the only 36nm (M1) lines run parallel with the gates...

The floor-plans would look like this I presume:

So the processes of Intel and Globalfoundries would look even more equal. With the exception of Intel's unusual 2:3 ratio of the M1 (green) and CPP (red) pitches of 36nm/54nm = 2/3.

Man that is absolutely beautiful! I love it!

 

[raghu78]

It looks like Intel relaxed some layers from an original 36 nm to 44 nm and went from a 7.5 track design to a 6 track design to keep the Logic cell size equal. Then developed Cotact-over-active-gate to squeeze their existing libraries into less tracks.

The odd thing is the track size 272:36 = 7.56 while the only 36nm (M1) lines run parallel with the gates...

The floor-plans would look like this I presume:

So the processes of Intel and Globalfoundries would look even more equal. With the exception of Intel's unusual 2:3 ratio of the M1 (green) and CPP (red) pitches of 36nm/54nm = 2/3.

Nice work. So you are telling that Intel uses a 6.18T cell layout (44 x 6.18 = 272) with cell height 272nm. Very interesting.

 

[NTMBK]

The x86 benefit and curse -- the legacy software locks the market into basically two vendors, but the validation complexity of cores with all of that extra cruft in the ISA probably holds back performance.

Case in point, Zen had a bug with Virtual 8086 Mode Enhancements. A 25 year old feature, designed to improve emulation of a 40 year old processor.

 

[Dayman1225]

IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV

 

[goldstone77]

IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV

5 pages of information showing the progress from 14nm to 7nm. Looking at side by side difference in fins from 14nm to 7nm really shows a very big improvement!

 

[stuff_me_good]

Vow... this looks seriously interesting. Is it the first time in history that AMD and Intel are completely at the same playing field around 2019 regarding processors? If I remember correctly, Intel always had some extra lead due to better process, but AMD was able counter it many times by having better architecture(pre faildozer that is).

 

[goldstone77]

Vow... this looks seriously interesting. Is it the first time in history that AMD and Intel are completely at the same playing field around 2019 regarding processors? If I remember correctly, Intel always had some extra lead due to better process, but AMD was able counter it many times by having better architecture(pre faildozer that is).

It really looks that way. This kind of competition between the 4 foundries is really driving innovation! EXCITING! I'm saving up my pennies for 2019!

 

[raghu78]

Vow... this looks seriously interesting. Is it the first time in history that AMD and Intel are completely at the same playing field around 2019 regarding processors? If I remember correctly, Intel always had some extra lead due to better process, but AMD was able counter it many times by having better architecture(pre faildozer that is).

Yeah. AMD will have for the first time in more than a decade a competitive process to compete against Intel. I think IBM's experience with designing high performance nodes process combined with GF's HVM expertise has helped them come out with a very competitive node. It also looks like GF made few important decisions to reduce risk and increase flexibility of their process node as they are a foundry and not a IDM. SADP for metal layers, cobalt for contacts and cobalt liner + cap for M0-M3 metal layers (while not going too aggressive on cobalt for metal layers) choices seem to indicate that thought process.

It really looks that way. This kind of competition between the 4 foundries is really driving innovation! EXCITING! I'm saving up my pennies for 2019!

Actually I think Samsung made a strategic error by betting on EUV based 7LPP and are going to have the most risky route and are likely to arrive last with a true foundry 7nm node. Anyway I agree that there are 4 viable choices at the leading edge and thats a great development for semiconductor manufacturing.

 

[goldstone77]

Actually I think Samsung made a strategic error by betting on EUV based 7LPP and are going to have the most risky route and are likely to arrive last with a true foundry 7nm node. Anyway I agree that there are 4 viable choices at the leading edge and thats a great development for semiconductor manufacturing.

Samsung Says EUV on Schedule for 2018
Dylan McGrath
9/12/2017 00:01 AM EDT

The results of a survey of 75 semiconductor luminaries released Monday (Sept. 11) indicated that 75 percent now believe that EUV will be adopted in high-volume manufacturing before 2021. Just 1 percent said EUV will never be embraced, down from 6 percent last year and a whopping 35 percent in 2014.

Samsung said it has processed close to 200,000 wafers with EUV lithography technology since 2014 and has recently seen visible improvement with EUV technology, such as achieving 80 percent yield for 256 Mb SRAM.

Samsung Unveils Scaling, Packaging Roadmaps
Foundry unit rolls out ambitious plan down to 4nm, along with 18nm FD-SOI and advanced packaging developments.
MAY 24TH, 2017 - BY: ED SPERLING

But what is clear is that Samsung is attempting to pick up business at every node and half-node, including 8nm, 7nm, 6nm, 5nm, and 4nm, and it plans to introduce an 18nm version of its FD-SOI technology in 2019.

Low said that with EUV the company is turning out 1,200 wafers per day, and he expects that number to improve.

This was a risky strategic move by Samsung, but not something they just started. EUV is the almost assuredly the only way forward. They adopted EUV before anyone else, and have enough confidence to let their roadmap known. They are very close to the magic 1,500 wafers per day for full production reporting 1,200 per day May 24th, 2017, and have been working on EUV since 2014 and were achieving 80% yield for 256 MB SRAM. They also have the smallest measurements for 7nm cell out of the 4 foundries. If they pull this off who is going to stop them? They will gain back the lost foundry business from TSMC, and then some I'm sure! This is what aggressive plentiful competition looks like! We needed this in the desktop CPU market. There is no telling where we would be by now.

 

[goldstone77]

A 55% increase in fin height from 14nm(27nm) to 7nm(42nm).

 

[CatMerc]

Nice and rectangular too.

 

[ksec]

........If they pull this off who is going to stop them? They will gain back the lost foundry business from TSMC, and then some I'm sure! This is what aggressive plentiful competition looks like! We needed this in the desktop CPU market. There is no telling where we would be by now.

The problem with Samsung was never a technical one. EUV's problem has always been about yield, and that is a money problem that can be fixed with Samsung's dollar, ( Not just Samsung electronics ). They can throw money in to battle the next Chinese assault on NAND and DRAM, they can built and invest in battery tech to combat LG and Panasonic.

The problem is about trust. And that is not something a 10% better yield or better SRAM density be exchanged with.

One reason why TSMC is so popular is because they are pure play foundry.

 

[raghu78]

Nice and rectangular too.

That fin shape is the most rectangular one I have seen todate on any process - shipping currently or next gen ones showcased like Intel 10nm.

Sent from my SM-G935V using Tapatalk

 

[goldstone77]

It looks like Intel relaxed some layers from an original 36 nm to 44 nm and went from a 7.5 track design to a 6 track design to keep the Logic cell size equal. Then developed Cotact-over-active-gate to squeeze their existing libraries into less tracks.

The odd thing is the track size 272:36 = 7.56 while the only 36nm (M1) lines run parallel with the gates...

The floor-plans would look like this I presume:

So the processes of Intel and Globalfoundries would look even more equal. With the exception of Intel's unusual 2:3 ratio of the M1 (green) and CPP (red) pitches of 36nm/54nm = 2/3.

Question for you I was ask about the 14nm. 0.0499 and 0.0588 LV for the 14nm.
https://en.wikichip.org/wiki/14_nm_lithography_process
I found this:

Edit: I posted 10nm originally, here is 14nm with cell heights.

 

[Hans de Vries]

Question for you I was ask about the 14nm. 0.0499 and 0.0588 LV for the 14nm.
https://en.wikichip.org/wiki/14_nm_lithography_process
I found this:

Updated in the image, thanks!

 

[goldstone77]

Updated in the image, thanks!

I think you posted the wrong one.

 

[Hans de Vries]

I think you posted the wrong one.

It's the old image in your Browser cache. Reload the page while pressing on the shift key :^)

 

[goldstone77]

It's the old image in your Browser cache. Reload the page while pressing on the shift key :^)

thanks hahaha

 

[french toast]

That fin shape is the most rectangular one I have seen todate on any process - shipping currently or next gen ones showcased like Intel 10nm.

Sent from my SM-G935V using Tapatalk

Noob question...does the shape of the fin- ie; whether it's angled or not have much impact on the performance, or is it an admiration for the aesthetics?

Am I correct in saying the longer fin ratios improve frequency?

 

[goldstone77]

Noob question...does the shape of the fin- ie; whether it's angled or not have much impact on the performance, or is it an admiration for the aesthetics?

Am I correct in saying the longer fin ratios improve frequency?

Fin shape and "height" have an effect on performance. Shape determines how it will behave. The more rectangular the shape the better it will function. Fin height does effect frequency. Taller fins also create area efficiency, meaning you can pack more closer together.