Intel 10nm and GF 7nm at IEDM 2017

[raghu78]

Well, it looks like they did everything they could to best the competition. They will probably still be tops in electrostatics, but lose most of their density lead due competitors catching up (not that x86 CPUs are optimal for comparing density).

You need to have a process which hits the targets - performance, power, density, yield, time to market. I think 10 has failed badly on most counts especially the most important ones such as yields and time to market. charlie called Intel 10nm broken more than a year ago. We are seeing the Intel 10nm horrow show unfold now. The responsibility is now on 10+ to fix the issues at 10 and hit the necessary goals to bring ICL to market in H1 2019.

Business as usual for them, then, after a brief density lead.

Density lead ? TSMC 10nm is more dense than Intel 14nm. TSMC N7 6T is more dense than Intel 10nm 7.56T. For high performance TSMC N7 HPC uses 9T. But I am pretty sure Intel does not use std library cells for ultra high perf CPUs like CFL or its successor ICL.

 

[Ajay]

Density lead ? TSMC 10nm is more dense than Intel 14nm. TSMC N7 6T is more dense than Intel 10nm 7.56T. For high performance TSMC N7 HPC uses 9T. But I am pretty sure Intel does not use std library cells for ultra high perf CPUs like CFL or its successor ICL.

I'm sure Intel builds a library for it's x86 CPUs. They are more heavily synthesized than in the past. Nonetheless, the 'standard' cells are geared towards perf and perf/watt much more than density. For and ARM SoC, density (lowest cost) is the most important factor, except perhaps for Apple. Even Nvidia needs pretty high density to generate high margins.

 

[Yotsugi]

The responsibility is now on 10+ to fix the issues at 10 and hit the necessary goals to bring ICL to market in H1 2019.

Actually they need to bring ICL-SP to market as soon as possible because otherwise Rome will give us the horror show of the decade.

 

[raghu78]

Actually they need to bring ICL-SP to market as soon as possible because otherwise Rome will give us the horror show of the decade.

The guestion now boils down to can GF deliver 7LP HVM on time and with reasonably good yields. If they do Intel are in a world of deep trouble. 4 x 175-200 sq mm chiplets (with rumoured 64C,256 MB L3) on GF 7LP 6T (7SoC) will be a nightmare scenario for Intel's 400 sq mm first gen Icelake-SP (38C). I am hoping GF delivers the goods so we can see Intel's monopoly in servers be destroyed.

 

[Yotsugi]

The guestion now boils down to can GF deliver 7LP HVM on time and with reasonably good yields.

I think Patton&crew are confident on pretty much everything bar EUV insertion.
Oh, I can't wait for the nightmare that is Rome.

 

[Ajay]

The guestion now boils down to can GF deliver 7LP HVM on time and with reasonably good yields. If they do Intel are in a world of deep trouble. 4 x 175-200 sq mm chiplets (with rumoured 64C,256 MB L3) on GF 7LP 6T (7SoC) will be a nightmare scenario for Intel's 400 sq mm first gen Icelake-SP (38C). I am hoping GF delivers the goods so we can see Intel's monopoly in servers be destroyed.

Rome is 64 cores?! Is Ryzen 2 going to an 8 core CCX?? So far, destroying Intel's market dominance isn't proving easy (long qualification period on Epyc and 'no one gets fired for buying Intel' mentality).

 

[Yotsugi]

Rome is 64 cores?! Is Ryzen 2 going to an 8 core CCX?? So far, destroying Intel's market dominance isn't proving easy (long qualification period on Epyc and 'no one gets fired for buying Intel' mentality).

Purley is competitive with Naples.
AMD may go for separate server die with Rome.
They are already splitting client/server with PR.
So, why not to go for the throat?
Intel won't be able to respond in any reasonable timeframe.

 

[raghu78]

Rome is 64 cores?! Is Ryzen 2 going to an 8 core CCX?? So far, destroying Intel's market dominance isn't proving easy (long qualification period on Epyc and 'no one gets fired for buying Intel' mentality).

https://hothardware.com/news/amd-epyc-2-64-cores-128-threads-and-256mb-l3-cache

I don't know if its 2 * 8 core CCX per die or 4 x 4core CCX per die.My guess is AMD might not change CCX layout till Milan in 2020. I think AMD will improve the fabric speeds in Rome and from the rumoured specs they seem to be doubling L3 cache per CCX from 8MB to 16 MB.

Purley is competitive with Naples.
AMD may go for separate server die with Rome.
They are already splitting client/server with PR.
So, why not to go for the throat
Intel won't be able to respond in any reasonable timeframe.

Thats exactly what I expect to happen. AMD has the resources now with growing revenues and profits. Rome will use density and power efficiency optimized 7LP 6T (7SoC) while Ryzen will use performance optimized 7LP 9T (7HPC) .

 

[itsmydamnation]

Thats exactly what I expect to happen. AMD has the resources now with growing revenues and profits. Rome will use density and power efficiency optimized 7LP 6T (7SoC) while Ryzen will use performance optimized 7LP 9T (7HPC) .

I dont know why people expect this to happen it make little sense from AMD perspective.

i expect AMD is targeting:
new uarch + process every "even" year
optical/+ process in consumer every odd year.

A sales period of 1 year isn't enough time for a server part, a dedicated client die means 2 extra SOC's in a 2 year cycle. There is far better things they can spend their engineering dollars on.

 

[AMDisTheBEST]

This is so tiny... are they even large enough to block electrons, hence current from passing through?

 

[beginner99]

Perhaps nailing down cobalt use now is a good thing for later?

My thought as well. Could be Intel lost 1-2 years now but will gain them back later if the foundries must do that step.

Intel went from a few years lead from other foundries (not in names but in actual density and performance) to being on par with others. 10nm already lost them that. By the time we will see HVM 10nm products, TSMC will already be in HVM of their equally dense 7nm.

Whatever damage it might do or if it will be successful doesn't change the massive loss in time to market lead.

Since Intel isn't actually a foundry, the damage will not be that huge. One has to wonder if this cobalt thing is so problematic, at some point the foundries must use it too and loose the time then that intel lost now. Maybe.

 

[itsmydamnation]

My thought as well. Could be Intel lost 1-2 years now but will gain them back later if the foundries must do that step.



Since Intel isn't actually a foundry, the damage will not be that huge. One has to wonder if this cobalt thing is so problematic, at some point the foundries must use it too and loose the time then that intel lost now. Maybe.

But they are using it now, just not as much.which means they have an extra 2 years to get a handle on it and drive it further into the metal stack.at the same time the 3Rd party tools / solutions will get better too.

The bit that is the worry for Intel is that GF 7nm looks way better the 14llp relative to the Intel node (14/10).

 

[Arachnotronic]

My thought as well. Could be Intel lost 1-2 years now but will gain them back later if the foundries must do that step.



Since Intel isn't actually a foundry, the damage will not be that huge. One has to wonder if this cobalt thing is so problematic, at some point the foundries must use it too and loose the time then that intel lost now. Maybe.

Cobalt wires at some metal layers was being talked about for the foundry 5nm nodes, so you might see the foundries adopt in the 2020/2021 timeframe.

 

[Yotsugi]

Since Intel isn't actually a foundry,

Hmmmmmm.
What's Intel Custom Foundry then?

 

[Arachnotronic]

Hmmmmmm.
What's Intel Custom Foundry then?

Irrelevant.

 

[Yotsugi]

Irrelevant.

Well I dunno, Intel would say it the other way.

 

[maddie]

To those rationalizing Intel's risk taking. There's this little thing called the Pareto Principle.

Recent history by AMD's CPU division has given us a solid lesson in its effective application. Look and learn.

 

[raghu78]

But they are using it now, just not as much.which means they have an extra 2 years to get a handle on it and drive it further into the metal stack.at the same time the 3Rd party tools / solutions will get better too.

The bit that is the worry for Intel is that GF 7nm looks way better the 14llp relative to the Intel node (14/10).

Exactly. GF 7LP is a much more competitive process vs Intel 10nm than 14LPP vs Intel 14nm. In fact GF has the density advantage in low power GF 7SoC (6T) vs Intel 10 (7.56T). Performance should be very competitive too given that 7SoC 6T is 40% faster than 14LPP 9T at same power and complexity.

https://m.eet.com/content/images/eetimes/1 7 12 14 copared x 800_1505972923.jpg

I expect AMD to use 7SoC for almost all products - 7nm Rome server cpus, 7nm APUs and other semi-custom embedded products which may be built at GF 7LP. I expect only desktop Ryzen to use GF 7HPC to hit 5 Ghz speeds.

 

[Ajay]

I expect AMD to use 7SoC for almost all products - 7nm Rome server cpus, 7nm APUs and other semi-custom embedded products which may be built at GF 7LP. I expect only desktop Ryzen to use GF 7HPC to hit 5 Ghz speeds.

Why? The perf/watt is awful for 7HPC, it will get trashed for that in the media and on forums. It will also severely skew perceptions of Rome by the non tech savvy investor analysts.

 

[raghu78]

Why? The perf/watt is awful for 7HPC, it will get trashed for that in the media and on forums. It will also severely skew perceptions of Rome by the non tech savvy investor analysts.

7HPC for desktop Ryzen CPU is a good choice. Base clocks will be at the sweet spot of the 7HPC curve (close to start of the 7HPC curve in the graph below). Single core turbo will be at the top end of the voltage/freq curve. So for stock performance efficiency will be decent. But expect that to go out the window if you want to hit 5 Ghz across all cores.

For 7nm APUs I think AMD will go with 7SoC to maximize efficiency (perf/watt and perf/sq mm).

 

[LTC8K6]

To those rationalizing Intel's risk taking. There's this little thing called the Pareto Principle.

Recent history by AMD's CPU division has given us a solid lesson in its effective application. Look and learn.

The peapod part, the socialist land grab part, the wealth redistribution part, or the sales part?

https://en.wikipedia.org/wiki/Pareto_principle

 

[maddie]

The peapod part, the socialist land grab part, the wealth redistribution part, or the sales part?

https://en.wikipedia.org/wiki/Pareto_principle

Being the net, I hope this is a joke. On the off chance its not.

Spending 20% to get 80% of the benefits.

Intel seems to be having a reverse effect. Spending 80% to get 20%.

 

[goldstone77]

https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake#All_Ice_Lake_Chips

 

[ksec]

TSMC is already using quad patterning to pattern the fins on its 10nm technology (fin pitch of 36nm).



http://techinsights.com/technology-intelligence/overview/latest-reports/tsmc-10-nm-process/

That is news to me, but I am not aware of any other product using 10nm anyway, so this 10nm is more like an testing ground for 7nm. Which was when I thought would be TSMC using quad patterning.

Both TSMC and GF has a much larger market to help with R&D compared to the old days. So it is not surprising Intel lost / will lose the lead soon.

 

[Dayman1225]

http://www.zdnet.com/google-amp/article/iedm-2017-intel-inches-closer-to-euv-lithography/

TL : DR

Using when viable