Intel 10nm and GF 7nm at IEDM 2017

Discussion in 'CPUs and Overclocking' started by raghu78, Oct 19, 2017.

  1. Lodix

    Lodix Senior member

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    Intel sait that 10nm++ gives 15% better performance compared to 10nm. It should be a little over 14nm++.
     
  2. Abwx

    Abwx Diamond Member

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    Actualy we can, at least for GF since they published some curves, conservatively the 14nm curve end at about 3.3-3.4GHz, the 7nm SOC thus end at 4.0-4.1GHz and the 7nm HPC at 5.3-5.4GHz...

    Keep in mind that these are the efficient frequency ranges of thoses nodes.
     
  3. Abwx

    Abwx Diamond Member

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    http://www.digitimes.com/news/a20171024PD215.html
     
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  4. raghu78

    raghu78 Diamond Member

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    https://semiengineering.com/manufacturing-bits-dec-5/

    "Intel’s 10nm technology represents the company’s third-generation finFET technology. The technology shows the characteristics of a steep subthreshold slope device (~70 mV/dec).

    The process makes use of 193nm immersion lithography and self-aligned quadruple patterning (SAQP). As previously stated, the process includes self-aligned contact over active gate scheme. The technology features 12 metal layers with ultra-low-k dielectrics. In a first for the industry, the technology will also incorporate cobalt materials at three local interconnect layers.

    Intel and other chipmakers are following the same transistor path at 10nm and 7nm–they are extending the finFET and making the fins taller and thinner, which in turn boosts the drive current. At 7nm, Intel’s transistors feature rectangular fins with 7nm fin width and 46nm fin height, according to a paper from Intel. At 10nm, Intel’s fin pitch is 34nm and the fin height is 53nm.

    Using SAQP at the metal-0 and metal-1 layers, Intel achieved fin pitches down to 34nm and metal pitches of 36nm. “Scaling of density critical interconnect layers is up to 0.51x versus the traditional 0.7x,” according to Intel’s paper.

    The interconnect stack has 12 layers. “Cobalt is introduced at the lowest two interconnect layers providing a 5-10x improvement in electromigration and a 2x reduction in via resistance,” according to the paper. “A cobalt cladding layer is utilized at Metal 2 – Metal 5 to improve electromigration. Low-k CDO dielectrics are used on 11 layers.”

    Meanwhile, GlobalFoundries will present more details about its 7nm finFET process. Compared to 14nm, the 7nm process has a performance increase of >40% at fixed power, or power reduction of >55% at fixed frequencies, according to the company.

    The technology makes use of SAQP for fin formation and SADP for the wiring schemes. Initially, GlobalFoundries won’t use extreme ultraviolet (EUV) lithography at 7nm. But the process is designed to leverage EUV when the technology is ready.

    GlobalFoundries’ finFETs have a fin pitch of 30nm, a contacted gate pitch of 56nm, and a metal pitch of 40nm.

    Multiple copper level stacks are offered to enable a range of SoC applications, according to GlobalFoundries. One example of a general purpose SoC is a 13-level stack. “Cobalt is introduced for contact metallization to reduce the resistance of the 7nm middle-of-line (MOL),” according to GlobalFoundries.


    Intel 10nm vs GF 7nm (7SoC)
    Intel 10nm
    CPP = 54nm
    MMP = 36nm
    Fin Pitch = 34nm
    Fin Height = 46nm
    12 Metal layers
    Tracks = 7.56
    6transistor HD SRAM cell = 0.0312 um

    GF 7SoC
    CPP = 56nm
    MMP = 40nm
    Fin Pitch = 30nm
    Fin Height = Not revealed yet
    13 Metal layers
    Tracks = 6
    6transistor HD SRAM cell = 0.0269 um

    https://www.semiwiki.com/forum/cont...alfoundries-discloses-7nm-process-detail.html
     
    #29 raghu78, Dec 5, 2017
    Last edited: Dec 5, 2017
  5. dark zero

    dark zero Platinum Member

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    Woot! So Intel and Glofo are pretty much edging each other, but with Intel having advantage on the process?
     
  6. raghu78

    raghu78 Diamond Member

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    Actually GF has the edge on process . GF 7SoC 6T vs Intel 10nm 7.56T . 0.0269 um HD SRAM cell for GF vs 0.0312 um HD SRAM cell for Intel.
     
    #31 raghu78, Dec 5, 2017
    Last edited: Dec 5, 2017
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  7. stuff_me_good

    stuff_me_good Member

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    Oops... and there goes Intel's famous 3 year lead on process technology.
     
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  8. Bondrewd

    Bondrewd Senior member

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    This pill will probably be the hardest for them to swallow.
     
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  9. Arachnotronic

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    https://www.eetimes.com/document.asp?doc_id=1332696&page_number=2

    I wonder if the extensive use of cobalt is hurting yield rates/manufacturability.
     
  10. Bondrewd

    Bondrewd Senior member

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  11. Arachnotronic

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    36nm is precisely the limit of 2D EUV, so that pitch was probably chosen with an eye towards EUV insertion.
     
  12. Bondrewd

    Bondrewd Senior member

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    But Intel is not racing towards EUV.
    That's the weird part.
     
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  13. raghu78

    raghu78 Diamond Member

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    https://semiengineering.com/manufacturing-bits-dec-5/

    Meanwhile, GlobalFoundries will present more details about its 7nm finFET process. Compared to 14nm, the 7nm process has a performance increase of >40% at fixed power, or power reduction of >55% at fixed frequencies, according to the company.

    The technology makes use of SAQP for fin formation and SADP for the wiring schemes. Initially, GlobalFoundries won’t use extreme ultraviolet (EUV) lithography at 7nm. But the process is designed to leverage EUV when the technology is ready.

    GlobalFoundries’ finFETs have a fin pitch of 30nm, a contacted gate pitch of 56nm, and a metal pitch of 40nm.

    Multiple copper level stacks are offered to enable a range of SoC applications, according to GlobalFoundries. One example of a general purpose SoC is a 13-level stack. “Cobalt is introduced for contact metallization to reduce the resistance of the 7nm middle-of-line (MOL),” according to GlobalFoundries.

    Does GF use cobalt for contact metallization and if so on which metal layers ?
     
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  14. Dayman1225

    Dayman1225 Senior member

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  15. raghu78

    raghu78 Diamond Member

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    https://twitter.com/Siliconicsdick/status/938836791980728320

    Clarified with Dick James and Scotten Jones (semiwiki) .

    GF 7nm uses cobalt for contacts. Intel 10nm uses cobalt for contacts, M0, M1 layers and cobalt cap for M2-M5 layers.

    https://www.eetimes.com/document.asp?doc_id=1332696&page_number=2

    In an interview with EE Times following the presentation, Patton and Basanth Jagannathan, a distinguished member of Globalfoundries' technical staff who presented the 7-nm process technology, said that sticking with copper/low-k provides reliability benefits, reducing complexity and yield risk.

    "The copper system still has a lot of juice left in it," said Jagannathan.

    It looks like Intel was a bit too aggressive in going with cobalt for contacts,M0, M1 metal layers and cobalt cap for M2-M5. Intel is struggling with yield issues something which GF seem to hint at with aggressive use of cobalt for lowest metal layers.
     
  16. witeken

    witeken Diamond Member

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    Intel not talking about EUV does not mean they are not developing EUV. They will use it when it makes economic sense, that's all they've said about it.
     
  17. Dayman1225

    Dayman1225 Senior member

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    Sooooooooooooooooooooooo, 7nm
     
  18. Bondrewd

    Bondrewd Senior member

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    Intel not talking about something == it's dead.
     
  19. LTC8K6

    LTC8K6 Lifer

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    Perhaps nailing down cobalt use now is a good thing for later?
     
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  20. Dayman1225

    Dayman1225 Senior member

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    I'm sure it is, doing stuff for the first time is always harder than the second or third time. It seems to have some nice benefits. 2x reduction in resistance and 1000x improvement in electromigration performance over copper, according to Intel's paper IIRC.
     
  21. Bondrewd

    Bondrewd Senior member

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    Time to market is H I L A R I O S L Y important.
    There's no later.
     
  22. LTC8K6

    LTC8K6 Lifer

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    7nm is later...
     
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  23. maddie

    maddie Golden Member

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    Later? Sure. Often dropping the baton loses the race.
     
  24. maddie

    maddie Golden Member

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    Isn't it the first time for all? It's not like they share with others.
     
  25. Qwertilot

    Qwertilot Golden Member

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    Even if you don't know the details its a quite enormous help to know you're trying to do the right thing :)