Intel 10nm and GF 7nm at IEDM 2017

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Lodix

Senior member
Jun 24, 2016
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Duh, IBM infusion surely is nice.

Sounds pretty nice.
I wonder what kind of performance 10++ will deliver and if it's ever going to be competitive against 7LP with EUV.
Intel sait that 10nm++ gives 15% better performance compared to 10nm. It should be a little over 14nm++.
 

Abwx

Lifer
Apr 2, 2011
10,854
3,298
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As multiple people have tried to point out, you cannot translate those figures straight into FMAX for a CPU..

Actualy we can, at least for GF since they published some curves, conservatively the 14nm curve end at about 3.3-3.4GHz, the 7nm SOC thus end at 4.0-4.1GHz and the 7nm HPC at 5.3-5.4GHz...

Keep in mind that these are the efficient frequency ranges of thoses nodes.
 

Abwx

Lifer
Apr 2, 2011
10,854
3,298
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Globalfoundries has improved its extreme ultraviolet (EUV) mask yield rate to nearly 65% recently, continuing to make progress in its migration to EUV lithography, said company CTO Gary Patton

The nearly 65% mask yield rate is still far from the company's targeted 95%.

Globalfoundries will first use EUV lithography technology in its 7nm FinFET node, and has started to work with AMD in the process development, Patton indicated

The 12LP node will be ready for volume production in the first quarter of 2018, according to the foundry.




http://www.digitimes.com/news/a20171024PD215.html
 

raghu78

Diamond Member
Aug 23, 2012
4,093
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https://semiengineering.com/manufacturing-bits-dec-5/

"Intel’s 10nm technology represents the company’s third-generation finFET technology. The technology shows the characteristics of a steep subthreshold slope device (~70 mV/dec).

The process makes use of 193nm immersion lithography and self-aligned quadruple patterning (SAQP). As previously stated, the process includes self-aligned contact over active gate scheme. The technology features 12 metal layers with ultra-low-k dielectrics. In a first for the industry, the technology will also incorporate cobalt materials at three local interconnect layers.

Intel and other chipmakers are following the same transistor path at 10nm and 7nm–they are extending the finFET and making the fins taller and thinner, which in turn boosts the drive current. At 7nm, Intel’s transistors feature rectangular fins with 7nm fin width and 46nm fin height, according to a paper from Intel. At 10nm, Intel’s fin pitch is 34nm and the fin height is 53nm.

Using SAQP at the metal-0 and metal-1 layers, Intel achieved fin pitches down to 34nm and metal pitches of 36nm. “Scaling of density critical interconnect layers is up to 0.51x versus the traditional 0.7x,” according to Intel’s paper.

The interconnect stack has 12 layers. “Cobalt is introduced at the lowest two interconnect layers providing a 5-10x improvement in electromigration and a 2x reduction in via resistance,” according to the paper. “A cobalt cladding layer is utilized at Metal 2 – Metal 5 to improve electromigration. Low-k CDO dielectrics are used on 11 layers.”

Meanwhile, GlobalFoundries will present more details about its 7nm finFET process. Compared to 14nm, the 7nm process has a performance increase of >40% at fixed power, or power reduction of >55% at fixed frequencies, according to the company.

The technology makes use of SAQP for fin formation and SADP for the wiring schemes. Initially, GlobalFoundries won’t use extreme ultraviolet (EUV) lithography at 7nm. But the process is designed to leverage EUV when the technology is ready.

GlobalFoundries’ finFETs have a fin pitch of 30nm, a contacted gate pitch of 56nm, and a metal pitch of 40nm.

Multiple copper level stacks are offered to enable a range of SoC applications, according to GlobalFoundries. One example of a general purpose SoC is a 13-level stack. “Cobalt is introduced for contact metallization to reduce the resistance of the 7nm middle-of-line (MOL),” according to GlobalFoundries.


Intel 10nm vs GF 7nm (7SoC)
Intel 10nm
CPP = 54nm
MMP = 36nm
Fin Pitch = 34nm
Fin Height = 46nm
12 Metal layers
Tracks = 7.56
6transistor HD SRAM cell = 0.0312 um

GF 7SoC
CPP = 56nm
MMP = 40nm
Fin Pitch = 30nm
Fin Height = Not revealed yet
13 Metal layers
Tracks = 6
6transistor HD SRAM cell = 0.0269 um

https://www.semiwiki.com/forum/cont...alfoundries-discloses-7nm-process-detail.html
 
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dark zero

Platinum Member
Jun 2, 2015
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Woot! So Intel and Glofo are pretty much edging each other, but with Intel having advantage on the process?
 

raghu78

Diamond Member
Aug 23, 2012
4,093
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Woot! So Intel and Glofo are pretty much edging each other, but with Intel having advantage on the process?

Actually GF has the edge on process . GF 7SoC 6T vs Intel 10nm 7.56T . 0.0269 um HD SRAM cell for GF vs 0.0312 um HD SRAM cell for Intel.
 
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The use of cobalt by Intel for contact metalization at 10nm could emerge as a differentiator in the advanced semiconductor manufacturing battleground. Globalfoundries at 7nm continues to use the copper/low-k dielectrics which have been used by the semiconductor industry for the past several nodes.

In an interview with EE Times following the presentation, Patton and Basanth Jagannathan, a distinguished member of Globalfoundries' technical staff who presented the 7nm process technology, said sticking with copper/low-k provides reliability benefits, reducing complexity and yield risk.

"The copper system still has a lot of juice left in it," Jagannathan said.

https://www.eetimes.com/document.asp?doc_id=1332696&page_number=2

I wonder if the extensive use of cobalt is hurting yield rates/manufacturability.
 

raghu78

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Aug 23, 2012
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https://www.eetimes.com/document.asp?doc_id=1332696&page_number=2

I wonder if the extensive use of cobalt is hurting yield rates/manufacturability.

https://semiengineering.com/manufacturing-bits-dec-5/

Meanwhile, GlobalFoundries will present more details about its 7nm finFET process. Compared to 14nm, the 7nm process has a performance increase of >40% at fixed power, or power reduction of >55% at fixed frequencies, according to the company.

The technology makes use of SAQP for fin formation and SADP for the wiring schemes. Initially, GlobalFoundries won’t use extreme ultraviolet (EUV) lithography at 7nm. But the process is designed to leverage EUV when the technology is ready.

GlobalFoundries’ finFETs have a fin pitch of 30nm, a contacted gate pitch of 56nm, and a metal pitch of 40nm.

Multiple copper level stacks are offered to enable a range of SoC applications, according to GlobalFoundries. One example of a general purpose SoC is a 13-level stack. “Cobalt is introduced for contact metallization to reduce the resistance of the 7nm middle-of-line (MOL),” according to GlobalFoundries.

Does GF use cobalt for contact metallization and if so on which metal layers ?
 
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raghu78

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Aug 23, 2012
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https://twitter.com/Siliconicsdick/status/938836791980728320

Clarified with Dick James and Scotten Jones (semiwiki) .

GF 7nm uses cobalt for contacts. Intel 10nm uses cobalt for contacts, M0, M1 layers and cobalt cap for M2-M5 layers.

https://www.eetimes.com/document.asp?doc_id=1332696&page_number=2

In an interview with EE Times following the presentation, Patton and Basanth Jagannathan, a distinguished member of Globalfoundries' technical staff who presented the 7-nm process technology, said that sticking with copper/low-k provides reliability benefits, reducing complexity and yield risk.

"The copper system still has a lot of juice left in it," said Jagannathan.

It looks like Intel was a bit too aggressive in going with cobalt for contacts,M0, M1 metal layers and cobalt cap for M2-M5. Intel is struggling with yield issues something which GF seem to hint at with aggressive use of cobalt for lowest metal layers.
 

witeken

Diamond Member
Dec 25, 2013
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But Intel is not racing towards EUV.
That's the weird part.
Intel not talking about EUV does not mean they are not developing EUV. They will use it when it makes economic sense, that's all they've said about it.
 

Yotsugi

Golden Member
Oct 16, 2017
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Intel not talking about EUV does not mean they are not developing EUV. They will use it when it makes economic sense, that's all they've said about it.
Intel not talking about something == it's dead.
 

Dayman1225

Golden Member
Aug 14, 2017
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Perhaps nailing down cobalt use now is a good thing for later?

I'm sure it is, doing stuff for the first time is always harder than the second or third time. It seems to have some nice benefits. 2x reduction in resistance and 1000x improvement in electromigration performance over copper, according to Intel's paper IIRC.
 

maddie

Diamond Member
Jul 18, 2010
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I'm sure it is, doing stuff for the first time is always harder than the second or third time. It seems to have some nice benefits. 2x reduction in resistance and 1000x improvement in electromigration performance over copper, according to Intel's paper IIRC.
Isn't it the first time for all? It's not like they share with others.
 

Qwertilot

Golden Member
Nov 28, 2013
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Even if you don't know the details its a quite enormous help to know you're trying to do the right thing :)