In-Depth: Intel's 10nm was definitely NOT too ambitious

[dullard]

They cannot possibly ramp 10+ before 10.

Why? Why can they not find out that process A is not working, then release process B? Why must process A be released in mass production before B can be manufactured? I honestly do not understand the point that you and Lodix are trying to make.

 

[LTC8K6]

They cannot possibly ramp 10+ before 10. So are you implying they delaying 10nm even further until 10+ is ready? I do not think Intel can afford additional delays - they will bring 10nm into mass production as soon as possible, while 10+ will come later.

Why can't they abandon 10nm after some low volume / low yield production, and go with an improved 10+?

Intel's 10nm process may need to go to 10+ to work well. The process may simply be too hot/power hungry in the initial version.

Also, if 10nm doesn't compete well with 14nm++, what's the point of going to mass production with it? It's a waste.

Why not abandon it and go with 10+?

 

[maddie]

Why? Why can they not find out that process A is not working, then release process B? Why must process A be released in mass production before B can be manufactured? I honestly do not understand the point that you and Lodix are trying to make.

Are you saying that AFAIK process B, by your naming, being an improvement/iteration on process A, does not need A to work properly first?

Wouldn't all of the unsolved problems also transfer to the advanced process.

If 10nm as presently constituted is abandoned and we only get 10nm+, then they have changed direction and foregone most of the previous work as 10nm+ will have to be radically different.

Can you even use the term 10nm+ if 10nm never happened outside of research?

 

[Thala]

Why can't they abandon 10nm after some low volume / low yield production, and go with an improved 10+?

Of course they can, but not without delaying it further. 10+ being an improvement of 10 implies that there are additional technological challenges/features, which are not in 10nm. So you have all 10nm issues to solve and then some before you can ramp 10+.

 

[dullard]

Of course they can, but not without delaying it further. 10+ being an improvement of 10 implies that there are additional technological challenges/features, which are not in 10nm. So you have all 10nm issues to solve and then some before you can ramp 10+.

I think you misunderstand Intel's usage of '+'. There are no new challenges or features. It is a refined version of the exact same features. They just found that process B gives better results than process A that they have been using internally for months/years. There are no new issues solved, but a different optimization of the same issues.

 

[dullard]

Are you saying that AFAIK process B, by your naming, being an improvement/iteration on process A, does not need A to work properly first?

Wouldn't all of the unsolved problems also transfer to the advanced process.

If 10nm as presently constituted is abandoned and we only get 10nm+, then they have changed direction and foregone most of the previous work as 10nm+ will have to be radically different.

Can you even use the term 10nm+ if 10nm never happened outside of research?

Suppose you make a house and the original design had a door that is 2 feet tall. You are building the house, and in the process determine that there is a problem with the front door. So, you decide before moving in that 2 feet is too small and go with a door that is 7 feet tall. Is that 7 foot door not door #2? Does door #1 have to meet your needs before you can finish the house with door #2? Or must you move in with door #1, wait for mass usage of door #1 and then you can install door #2?

It just make no sense that you can't find out that door #1 is a failure and upgrade to door #2 before launch. And of course you can call it door #2. Even if door #1 was just research, you can call door #2 anything you want.

 

[HutchinsonJC]

The house wasn't operational with door #1. So you never had a base line sale to have a plus model.

 

[maddie]

Suppose you make a house and the original design had a door that is 2 feet tall. You are building the house, and in the process determine that there is a problem with the front door. So, you decide before moving in that 2 feet is too small and go with a door that is 7 feet tall. Is that 7 foot door not door #2? Does door #1 have to meet your needs before you can finish the house with door #2? Or must you move in with door #1, wait for mass usage of door #1 and then you can install door #2?

It just make no sense that you can't find out that door #1 is a failure and upgrade to door #2 before launch. And of course you can call it door #2. Even if door #1 was just research, you can call door #2 anything you want.

Staying in the whimsical tone of your analogy.

What if in building your house, you realize that the chosen site can't withstand the load, so you have to abandon the site and build another house elsewhere? Is it the same house?

The length of time being invested in 10nm, suggests very fundamental problems. Fiddling with details do not change those.

 

[Dayman1225]

Staying in the whimsical tone of your analogy.

What if in building your house, you realize that the chosen site can't withstand the load, so you have to abandon the site and build another house elsewhere? Is it the same house?

The length of time being invested in 10nm, suggests very fundamental problems. Fiddling with details do not change those.

Suppose you make a house and the original design had a door that is 2 feet tall. You are building the house, and in the process determine that there is a problem with the front door. So, you decide before moving in that 2 feet is too small and go with a door that is 7 feet tall. Is that 7 foot door not door #2? Does door #1 have to meet your needs before you can finish the house with door #2? Or must you move in with door #1, wait for mass usage of door #1 and then you can install door #2?

It just make no sense that you can't find out that door #1 is a failure and upgrade to door #2 before launch. And of course you can call it door #2. Even if door #1 was just research, you can call door #2 anything you want.

FWIW this is the most that Intel has given on the differences on 10 and 10+

 

[Thala]

I think you misunderstand Intel's usage of '+'. There are no new challenges or features. It is a refined version of the exact same features. They just found that process B gives better results than process A that they have been using internally for months/years. There are no new issues solved, but a different optimization of the same issues.

Are you somewhat confused today, because you gave the answer yourself already?

The difference between 14 nm and 14nm+ included things like fin height, fin pitch, and aspect ratio.

It is a well known fact that in order to increase current you have to increase fin height, in particular because other features are getting smaller, like fin width. However we are approaching fin aspect ratios of almost 10:1 - a real technological challenge. Therefore you do not try to achieve insane fin aspect ratios while your base technology with more modest aspect ratios is not working.

In addition you need to develop the according cell libraries - which again are iterations over the 10nm cell library.

I can only repeat myself, you cannot possibly skip 10nm and directly going to 10+ without delaying something.

 

[formulav8]

FWIW this is the most that Intel has given on the differences on 10 and 10+

Wasn't it said it would take 10nm++ to exceed 14nm+ transistor performance or am I not remembering correctly?

 

[Dayman1225]

Wasn't it said it would take 10nm++ to exceed 14nm+ transistor performance or am I not remembering correctly?

According to Intel, 10 and 10+ > 14+ but <14++ where 10++ is needed

 

[Thala]

Wasn't it said it would take 10nm++ to exceed 14nm+ transistor performance or am I not remembering correctly?

Indeed. The reason for this is, that decrease in current (Ion) is higher than decrease in capacitance due to shrink. They would need to increase the channel cross section as counter measure - which can be achieved by higher fins as example. (see also my comment about the challenge of achieving higher fin aspect ratios above)

 

[LTC8K6]

Intel has had working 10nm chips for ~18 months. That should be enough time to have decided to refine the process once before 2019 ramp-up.
We don't know for sure what the exact problem was with those first 10nm chips, but given the 8121u, it seems like maybe they ran hotter than expected?
That is, they worked okay, but not in comparison to the 14nm line in terms of heat and clocks.
There was also an IGP problem, but we don't know if the IGP simply didn't work, or if it also possibly ran too hot/slow?
There is also the fact that Intel is adding AVX-512 to these chips.

I'll be surprised to see Intel come out with very many first gen 10nm chips in mass production. Maybe they will.

 

[dullard]

I can only repeat myself, you cannot possibly skip 10nm and directly going to 10+ without delaying something.

Yes, there will be a delay. But that isn't what you (and others said). What I was denying is that people are saying you CAN'T skip 10 nm.

 

[dullard]

FWIW this is the most that Intel has given on the differences on 10 and 10+

Thank you for the post. Which ones of the 10 nm+ changes require mass production of 10 nm? Or do they just require 10 nm to be solved and then skipped?

Reusing IP, does that require mass production first? Doesn't sound like it. It just means the IP needs to be relevant and functional.

Additional CPP device. Does designing a CPP device require mass production of 10 nm?

New logic libraries, do they require mass production before you can possibly create libraries?

 

[ksec]

One possible reason, were that midway 10nm, Intel decide Custom Foundry will do 10nm as well. So they had lots of thing to change and taken care of, the reason why Intel has always had the node advantage was not only the millions of PC CPU ship every year, but also the tight integration of CPU and node, there are no other small and edge cases to be taken care of compare to TSMC.

And this dramatically slows down what 10nm they had in mind.

 

[wahdangun]

Intel has had working 10nm chips for ~18 months. That should be enough time to have decided to refine the process once before 2019 ramp-up.
We don't know for sure what the exact problem was with those first 10nm chips, but given the 8121u, it seems like maybe they ran hotter than expected?
That is, they worked okay, but not in comparison to the 14nm line in terms of heat and clocks.
There was also an IGP problem, but we don't know if the IGP simply didn't work, or if it also possibly ran too hot/slow?
There is also the fact that Intel is adding AVX-512 to these chips.

I'll be surprised to see Intel come out with very many first gen 10nm chips in mass production. Maybe they will.

No, the chip is alright, it's just intel can't ramping up production because they have become too ambitious.

 

[JoeRambo]

I remember Bohr presentation about "physics" of patterning and thinking that SAQP is madness. And here we are, with Intel doing three SAQP steps, two of those are very questionable when competition is doing 40nm metal interconnects in SADP. Whatever performance excuses there are (and we know from 14++ that performance was increased by relaxing density, not increasing it), they are clearly not working out for Intel.

8121u is IMHO giving away that real problem is the yields, both in functioning chips and poor bins due to "yield" factors. If it was only yield problem, they would have released chips with functional GPU. They'd need to bin maybe 10x less chips to get ones with functional GPU and not take a massive prestige hit for what is essentially management bonus CPU. Since they couldn't, we can rest assured 10nm won't be coming out any time soon in any form. 2020 is probably realistic timeframe for chips larger than 200mm2

 

[jpiniero]

8121u is IMHO giving away that real problem is the yields, both in functioning chips and poor bins due to "yield" factors. If it was only yield problem, they would have released chips with functional GPU. They'd need to bin maybe 10x less chips to get ones with functional GPU and not take a massive prestige hit for what is essentially management bonus CPU.

I imagine they are not running that many wafers. Maybe at some point you will see the 8114Y.

 

[JoeRambo]

I imagine they are not running that many wafers. Maybe at some point you will see the 8114Y.

Unless the number is ridiculously low, they could still bin X times less chips and get the ones with functioning GPU out of the gate. Much more likely the resulting chip characteristics ( speed, power usage, temps etc ) are horrible. In that case Intel has to do the reverse, bin even more chips to catch golden ones that meet 15w TDP and 3.2Ghz turbo.

 

[jpiniero]

Unless the number is ridiculously low, they could still bin X times less chips and get the ones with functioning GPU out of the gate.

It's not a quality issue, it's a defect problem. You get a defect in the GPU front end you have to trash the whole GPU.

Like I would say they are getting 15-20% of chips tops with no defects, and that's with how tiny it is.

 

[Thala]

Yes, there will be a delay. But that isn't what you (and others said). What I was denying is that people are saying you CAN'T skip 10 nm.

Not sure what you were reading..but i just reviewed all my comments in this thread as far. In summary i always said, that skipping 10 and going directly 10+ would mean delaying mass production even further and that for the same reason Intel would not do this. I never implied that it is technically impossible - just highly stupid - because this essentially means not going into 10nm mass production despite being ready.

 

[dullard]

Not sure what you were reading..but i just reviewed all my comments in this thread as far. In summary i always said, that skipping 10 and going directly 10+ would mean delaying mass production even further and that for the same reason Intel would not do this. I never implied that it is technically impossible - just highly stupid - because this essentially means not going into 10nm mass production despite being ready.

Compare the underlined sentence above with the underlined sentence below.

They cannot possibly ramp 10+ before 10.

You might have a valid and useful point. But, you are burying your point with statements that directly contradict each other. I am unable to get past the contradictions and find your point. If you would rephrase these posts, that would be of great help for people like me who have a hard time agreeing with you when you don't agree with yourself.

In my humble opinion, potential 10 nm profits are lower than 14 nm++ profits for Intel (yield, lack of actual user benefits, required extra machine time for production, processor reliability/lifespan, etc). Ultimately, whatever the true reason is, the effect is that the cost per transistor right now in 10 nm is probably more than 14 nm++. Thus, Intel has no reason to launch 10 nm in any mass quantities. However, just because 10 nm is bad now, doesn't mean that they cannot possibly launch 10 nm+. It is that last statement of yours that they cannot possibly ramp 10 nm+ that confuses me. You aren't giving a clear reason why. Yes, not launching 10 nm means it will delay things. But, very specifically and in excruciating detail, please tell me how it is not possible to launch 10 nm+?

 

[Thala]

Compare the underlined sentence above with the underlined sentence below.
You might have a valid and useful point.

Thanks for quoting me out of context! If you had used the full statement it would have read like below

They cannot possibly ramp 10+ before 10. So are you implying they delaying 10nm even further until 10+ is ready? I do not think Intel can afford additional delays - they will bring 10nm into mass production as soon as possible, while 10+ will come later.

Reading the full statement makes it clear to everyone that i am referring to delays and not to the theoretical impossibility.