In-Depth: Intel's 10nm was definitely NOT too ambitious

witeken

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Dec 25, 2013
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Intel's 10nm was definitely NOT too ambitious

Introduction
In this post I will analyze Intel's 10nm a bit more concretely from a density point of view. It is based on following tweet I posted yesterday (the discussion was started by Ashraf's tweet about 10nm using Ru liner), and the debate it has ignited. People have corrected what I said in the tweet, and I want to share that insight in a more informative way where I will lead you through my thinking -- and the conclusion of the article will be that no, Intel's 2.7x scaling at 10nm was not too ambitious unlike that BK said (and therefor I do not believe that that is the culprit of 10nm's 4 year delay).

I think I've made this post as accessible as I can for people who haven't done a lot of digging into the various nodes' density and metrics.

Analysis

1. Wrong calculation
So this was my tweet.
Analysis. A 6.2T library to me would indicate a 120MTr density, interestingly, which Intel hasn't reported. I mean, gate pitch is same as TSMC, metal gives Intel 0.9x, COAG is 0.9x and SDG is 0.8x. So a 6.2T library means Intel 10nm has a solid 50% higher density than TSMC 7nm.
On the face of it, my analysis seems entirely plausible. It's known TSMC has reduced cell height at 7nm from 7.5T at 10nm to 6T. Now, T stands for tracks, where a track refers to the interconnect (pitch). And fortunately for us, both TSMC and Intel have reported that metric: 40nm for TSMC using SADP and 36nm for Intel using SAQP. So if TechInsights has found 10nm to have 6.2T cell height (compared to the 7.5T that had been reported earlier by industry analysts and which is the same as 14nm), about the same as TSMC, then that means Intel has a smaller cell height, for one, giving Intel about a 10% base density advantage already.

That's cell height. Cell width (together it gives you area, of course) is determined by the gate pitch, which is the same for both Intel and TSMC at 54nm, so that doesn't make a difference.

That's one cell. However, where Intel's hyperscaling came from, were two additional density boosters: contact over active gate (COAG) (the contact placed on the cell instead of next to it) reduces area by 0.9x, and single dummy gate (SDG) (which Samsung uses too but TSMC does not) reduces area by approx. 0.8x (depending on the logic cell width).

So adding it up, if say an ARM logic IP block were implemented in Intel 10nm and TSMC 7nm, the logic's area (SRAM for 7nm is a bit smaller than Intel's 10nm) should be 0.9 (metal) * 0.9 (COAG) * 0.8 (SDG) = 0.65x the size of the version on TSMC's 7nm node, or in words 1.54x the density.

That was my reasoning. In the tweet, you can see that I wasn't really sure about it, as I said this suggests Intel should have* ~120MTr/mm2 whereas they have reported 100.8MTr/mm2 -- I doubted the 6.2T report. I will now explain what was wrong about my reasoning and what's up with the 6.2T that TechInsights reported.

*Intel kindly measured TSMC's 10nm to have 48.1MTr/mm2, and TSMC has reported that 7nm has 1.63x the density, so for Intel 10nm to have 50% higher density, it should have 120MTr/mm2.

Note: SADP and SAQP mean self-aligned double/quadruple patterning. Single patterning can only to minimum pitches of 80nm. SADP halves that and SAQP halves that again. But the downside is that you need multiple extra steps to pattern the features, increasing cost and also complexity (overlay issues, etc.), giving rise to yield learning challenges.

2. Correct calculation
The main error is that I didn't check what the actual cell size is, although after I did, I was still confused as to why actually TSMC's cell is smaller if Intel has a smaller metal pitch.

My main error was about the track height. So, it turns out that going off track height was the wrong thing to do. Just ignoring track height for a moment, the most unambiguous way to compare density of nodes would be to simply do what I did earlier: calculate cell size, and then take into account any additional boosters.

It turns out Intel 10nm has a cell height of 272nm, whereas TSMC has a cell height of 240nm.

So actually TSMC 7nm has a 13% cell density advantage. If I then apply COAG and SDG, Intel 10nm logic comes out at 0.816x the size of TMSC 7nm, for a smaller (but still respectable) ~23% density advantage compared to TSMC 7nm.

With that out of the way, really the only thing left to do is reconcile these reported and conflicting cell/track heights, and to answer how Intel could possibly have a larger cell size, actually.

First, track height. If ones divides 272 by the reported 36nm, we indeed get the often reported 7.56T height. For TSMC, 240nm/40nm = 6, which seems reasonable. However, it turns out the 36nm pitch (the only metal pitch Intel disclosed at its 10nm unveil in March 2017 at its manufacturing day) is not the right interconnect pitch.



The M1 pitch lies parallel to the gate pitch. So it is the M2 pitch that the is real pitch which determines the 10nm cell height for Intel's 10nm. So indeed, the real/sensible value of Intel's track height is indeed 6.2T. This is about the same as TSMC, and the bigger actual metal pitch (only a 0.85x scaling from 14nm, actually) "gives" (as I shall discuss next, this is the wrong reasoning as track height is an a posteriori calculation) Intel a noticeably bigger cell size (6.2*44 vs. 6*40).

So thanks to @raghu78 for pointing this out.

Now, we can't be fully satisfied with this. Where does the 6.2T come from, for one. If you think the 6.2T sounds like a peculiar value, you'd be right. It turns out the track height is not what *causally* determines cell height: it is just an arbitrary calculation. So in fact, the usage of track height in the FinFET era is nothing more than a remnant from the planar past (and actually is thus has no right or reason to be used anymore).

As David Schor explains in these tweets:
As I said, like Samsung, the cell height is a function of the quantized diffusion lines (your fin pitches). 14nm had 9.5 of them and that has been reduced to 8 in 10nm. Talking in terms of tracks does not really make sense for neither Intel nor Samsung for this very reason.
What, apparently, matters is the number of "quantized diffusion lines", which is determined by the fin pitch. At 14nm, the value was 9.5 and it has been reduced to 8 at 10nm (due to fin depopulation), which is the same number as TSMC's 7nm, so actually there's no difference there.

So the reason Intel has a bigger cell size, is because they have a noticeably larger fin pitch of 34nm versus 30nm for TSMC and Global Foundries, and all have a value of 8 for the quantized diffusion lines.

3. Intel 22-14-10-7nm scaling
If we ignore the quantized diffusion lines for a second, while pondering this issue I have found an interesting metric which uncannily well approximates cell height scaling: M2 pitch * fin pitch.

Intel's 14nm has a cell height of 399nm (9.5*42), 10nm is 272nm (8*34), for a scaling of 0.682x. Comparing this to the metric I just stated, we have (44 / 52) * (34 / 42) = 0.685. Close enough.

We can now go back and look at how Intel achieved the 14nm generation's 2.7x scaling: fin pitch shrunk from 60nm to 42nm, gate pitch from 90nm to 70nm and interconnect pitch from 80nm to 52nm. Remember cell area is composed of gate pitch * cell height. If we approximate the cell height scaling by M2*fin pitch scaling, we get 0.7*0.65 = 0.46x, which is again very close to the real value of 0.48x (840nm to 399nm).

So if we pause for a second, at 14nm, density more than doubled from cell height scaling alone. Then we apply the gate pitch scaling to get to the final 2.7x logic density scaling.

We can now compare this to 10nm. Cell height wasn't cut in halve: it was only shrunk by 0.68x, with gate pitch again 0.8x. The reason cell height didn't shrink as much is, by my metric, because M2 pitch was scaled at a very relaxed 0.85x scaling (52->44) and fin pitch, too, also at a very unaggressive 0.8x (42->34).

It's interesting to ponder this further, since it does raise a couple of questions. Why does Intel use SAQP for the interconnect, whereas TSMC only uses SAQP for the 30nm fin pitch (not in the interconnect), while having a bigger cell size? Why does Intel use a 36nm pitch at all, given that TSMC can do a smaller cell with 40nm pitch and SADP? My guess is that they went with 36nm to get the most out of the cobalt interconnect to hit their performance targets.

Anyway, indeed as Intel said, the hyper scaling didn't come from aggressive cell scaling, but because of the two scaling boosters mentioned earlier. Those are innovations that are separate from scaling, and that's why I believe BK's statement of 10nm's problems due to aggressive scaling are bogus: cell scaling is a very normal, ordinary 0.5x, and then it's simply a question of can you do COAG, can you do SDG? Given that Samsung already does SDG, and given that COAG is only a 0.9x scaling, I don't think these in itself are that difficult to cause a 4 year delay. My opinion. So I think the problems lie elsewhere and of course Intel does not want to disclose what's really going on, but came up with a reasonable but still somewhat valid explanation.

Let's look at what BK said in the April earnings call:
Sure, so the issues around 10-nanometer, I'm trying to lay that flat out without getting too deep into the technology. But this is the last technology that doesn't incorporate EUV. And what you also need to understand is that we took very aggressive goals at 10 nanometers. So if you talk about the scaling factor or think about it as the multiple at which you shrink a feature, we took a target of 2.7. So you took any feature and run over 2.7 is the dimensional shrink that you did to this device. For example, on 14-nanometer, we took a target of 2.4, so you're almost 10% more aggressive on 10 nanometers.

And if you look at what is the industry standard, what the foundries and other players are typically doing, they're typically in that 1.5 to 2.0 range. So there, we're maybe 20% more aggressive. So it's very aggressive goals to hit our cost targets and where we want the technology to be. And that combined with the end of life of the immersion scanner before we hit EUV has just created something that's a little bit more difficult.

So that's why I have the confidence that this is not something we're shipping. The transistors work. We know the performance is in line. So it's really just about getting the defects and the costs in line to where we want.

As far as what does that imply for future technologies, we made a lot of changes at 7 nanometers. 7-nanometer currently is the first technology forecasted to implement EUV, so that immediately makes the lithography system different. We're going back to a more standard, for us, compaction number of 2.4, so that makes it a little bit easier. We think we bit off a little too much in this case. And it may not seem like a lot, but 10% can make a lot of difference in this kind of a world.

And thirdly, we are using some very unique packaging technologies and such that allow us. At 7 nanometers and beyond, we're really moving to a world where you're not going to look at any piece of silicon as being a single node. You're going to use what we're going to call heterogeneous techniques that allow us to use silicon for multiple nodes. So you may use cores from 7 nanometers and IP from 14 nanometers and even as far back as 22 nanometers for the parts that don't need the high performance. And we're able to put those together and make them perform and behave like a single piece of silicon in the package. So really 7 nanometers is quite a bit different, and so I think as a result, we don't expect to see these kinds of impacts on 7 nanometers.
First, 14nm was not a 2.4x target. It was a 2.7x target just like 10nm (slide 6 of the manufacturing day 14nm presentation by Ruth Bain). Intel also calls 14nm hyperscaling. 14nm's scaling was entirely from fin, gate and metal pitch scaling. And 14nm was "only" 6 months too late (although it did take another 2 years to achieve yield parity with 22nm due to slow yield learning because of the SADP).

But my best argument for why BK's scaling argument is bogus, is because we have not seen TSMC having a 4 year delay of their 7nm process. Indeed, TSMC is high-volume manufacturing right now with the same gate pitch, a 4nm smaller fin pitch and a 4nm bigger smallest-interconnect-pitch. And note that 4nm delta from 34 to 30 is a bigger percentage change than 40nm to 36nm.

So... why then is BK hinting at that 4nm metal pitch (40->36) difference ("10% can make a lot of difference")? I think that's really a big hint he gave! In the end, it comes back to the cobalt. Intel very likely wanted to cobalt to hit their performance targets. For reference, TSMC has guided only 15% performance increase at 5nm and 20% power decrease, whereas Intel claims 0.55x power reduction and 35-70% performance increase at 10nm, so if you don't do a lot of materials innovation, at these small nodes, you're not going to get a lot of power and performance benefit anymore. Someone from the industry (I think imec) has also very recently said that from 16nm to 7nm performance/frequency is basically flat. For TSMC that's no problem because their major customers don't need the performance, they need the density, whereas Intel is really all about hitting those very high frequency targets of up to 5GHz.

But to get a lot of mileage out of cobalt, Intel had to go to 36nm, for which they needed SAQP (although that doesn't explain the SAQP at the 40nm pitch). So the two key reasons for Intel's delay as my guess are the more extensive use of SAQP (they're the only ones doing SAQP in the interconnect) and cobalt probably being very difficult.

Now, for 7nm, one can do interesting things. Intel is rumored to consider III-V materials. These give a lot of performance benefit, so a single-fin transistor becomes possible.

So let's do some wild guesses just for fun, shall we ;)? Fin pitch can scale from 34 to 22nm (0.65x) - remember this is entirely possible if you go single fin, and to make up for the less aggressive 34nm at 10nm vs. others' 30nm. Metal pitch can scale from 44nm to 26nm (0.6x) (I have noted fin pitch is about 0.8x the metal pitch, so I have preserved that difference). And gate pitch can scale the usual 0.8x to 44nm. This would have given 7nm a 0.65*0.6*0.8 = 0.312x scaling or 3.2x the density. Now, that would have been quite the hyper-scaling with EUV :D. Intel surely wouldn't have put that on their roadmap, would they?

Well, of course III-V isn't possible, and in the same call BK was kindly enough to disclose a more usual 2.4x scaling at 7nm.

4. TSMC 7nm
The last thing I want to do, is reconcile TSMC's scaling.

TSMC achieved 1.63x scaling compared to 10nm. Gate pitch scaled from 66nm to 54nm. Metal pitch from 42nm to 40nm. Anyone have a clue?

Conclusions
So, forget about track height. Cell height is determined by fin pitch and number of quantized diffusion lines (same for Intel and TSMC at this node). TSMC has a smaller fin at 30nm vs. 34nm, and therefor wins in cell height. Intel, however, is able to reduce area by 30% because of the COAG and SDG hyper-scaling boosters, giving Intel approx. a 23-28% density advantage (gate pitch is the same).

Metal pitch didn't come up in the previous calculation, so the reason Intel went with a 36nm minimum interconnect pitch (requiring SAQP) likely has more to do with performance/power targets in my opinion, which is why they went with cobalt. SAQP and cobalt are probably the prime reasons for why 10nm is broken/uneconomical for Intel. (All my own guesses.)

Intel 10nm has 101MTr/mm2, TSMC 7nm has approx. 1.63*48.1 = 78.4 MTr/mm2 (lower bound for TSMC, as I have seen higher estimates).

About the track height, ultimately this is actually just an outdated metric. The point of confusion for me was that Intel actually does not use the 36nm pitch for the cell height, given that that one runs parallel to the gate width (not perp.). Instead Intel uses a 44nm pitch, compared to TSMC's 40nm.

To come back to the title of this thread. While BK blames the aggressive 2.7x target for the 4-year 10nm delay, I think this is only partially true. TSMC has smaller fin and comparable gate and metal pitches in HVM right now, while Intel - despite being >2 years ahead on the 14nm (foundry 10nm) node - is now a year behind TSMC. Indeed, cell area scaling only gave a ~0.5x scaling in density, nothing out of the ordinary, with very unaggressive pitch scaling (0.85x metal pitch, 0.8x fin pitch). If Intel had pushed the fin and metal pitch a bit more like TSMC, they could have achieved a transistor density of up to 120MTr/mm2 for a scaling of about 3.25x, so actually they didn't push the button on feature scaling that hard, ultimately.

Some people might argue that Intel has done too much in the 10nm node (while COAG and SDG are not feature size scalings, they do require certain innovations), however in my opinion it is up to Intel to gauge the maturity of those technologies when deciding on insertion in a certain node, for instance deciding to wait until 7nm or later for insertion until they're ready. So if Intel thought COAG and/or SDG weren't ready, they simply wouldn't/shouldn't have been included in the node.

(Clearly, Intel's risk assessment when coming up with the 10nm node definition must have failed somewhere, else the technology would not have been delayed by 4 (!!) years. But as I said, I think 10nm would've arrived sooner if they went with a 40nm pitch with copper like TSMC. In any case, unless Intel can pull a magic trick with 7nm, they clearly have lost their multi-year process lead because of a multi-year delay.)

Further reading
https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/03/Ruth-Brain-2017-Manufacturing.pdf
https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/03/Kaizad-Mistry-2017-Manufacturing.pdf
http://fpga.org/wp-content/uploads/2017/03/10nm-Hyper-Scaling.png
https://images.anandtech.com/doci/8367/14nmFeatureSize.png
https://en.wikichip.org/wiki/7_nm_lithography_process
https://en.wikichip.org/wiki/10_nm_lithography_process
https://electroiq.com/chipworks_real_chips_blog/
https://www.semiwiki.com/forum/content/7191-iedm-2017-intel-versus-globalfoundries-leading-edge-page2.html
https://forums.anandtech.com/threads/intel-10nm-and-gf-7nm-at-iedm-2017.2523567/page-10#post-39459384
https://twitter.com/witeken/status/1007220571745210368
https://twitter.com/lasserith/status/1007266404033335296
 
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raghu78

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I definitely think Intel was too ambitious as they tried to go too aggressive on density and performance simultaneously. But I agree that performance needs drove the decision making on 10nm. The need for cobalt drove the need for 36nm MMP and SAQP for lowest metal layers which is the major reason for Intel's yield problems. So performance and not density drove the need for SAQP on M0/M1. I also think Intel tried to compensate for the slightly less aggressive scaling on cell height and M2P by adding COAG and SDG. As much as Samsung had SDB at 14nm they have moved to DDB at 7nm EUV. So all the foundries have gone with DDB at 7nm. There are reasons why they have all gone with DDB. Foundry 7nm is an extremely complex node and risk management is critical. The choice of 40nm by TSMC and GF for 7nm with copper as the interconnect material reiterates the fact that newer exotic materials like cobalt and/or ruthenium might be impressive on paper but a proper analysis of risk needs to be done before committing on them. Finally I think Intel will find it hard to gain the process lead from here. Intel's best bet is to try and atleast get back on parity with TSMC. So if they can execute on 7nm and get it to HVM by 2022 Intel would have done very well to recover from the 10nm debacle.
 

realibrad

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I think as foundry work gets more complex, it becomes more costly to do what Intel does. Having to maintain its foundry as well as do R&D into its chips becomes very costly. Other foundries work with more than one company and it gives them a lot more information. Intel's foundry was for Intel so the only goal was to make Intel chips better. That is not a good idea long term.
 

ksec

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You forgot to mention TSMC will get 7nm+ next year. Which is when or if Intel ramp up their 10nm.

There is another thing, TSMC 7nm also has a High Performance version, from GPU to next gen APU on console. So to say Intel needs to care about performance while TSMC don't is not entirely accurate.
 

LTC8K6

Lifer
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You forgot to mention TSMC will get 7nm+ next year. Which is when or if Intel ramp up their 10nm.

There is another thing, TSMC 7nm also has a High Performance version, from GPU to next gen APU on console. So to say Intel needs to care about performance while TSMC don't is not entirely accurate.
AFAIK, Intel 10nm is not going to be used for much. Intel's ramp up will probably be 10nm+.
Ice Lake is 10nm+
Also Intel 10nm and TSMC 7nm are basically the same class.
 

Lodix

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AFAIK, Intel 10nm is not going to be used for much. Intel's ramp up will probably be 10nm+.
Ice Lake is 10nm+
Also Intel 10nm and TSMC 7nm are basically the same class.
I think people is delusional thinking Intel can just ramp 10+ as the initial 10nm process. They are not independent of each other, first 10nm has to work ( in mass production) and with maturity, yield learning and some tweaks then 10+ happens. It is the same with Samsung's Plus versions.

So first product on Intel 10nm will just be 10nm without the "+". Unless Intel marketing wants to call it that way anyway for hype shake.
 
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jpiniero

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I think people is delusional thinking Intel can just ramp 10+ as the initial 10nm process.
It sure looks like they are doing just that. The FPGA might be the only product on the regular 10 that ends up actually being sellable, not sure if HVM is needed for that.

They are just using the regular 10 to understand what (if) can be done to fix the yield, it's not like Cannonlake will get HVM now.
 

Lodix

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It sure looks like they are doing just that. The FPGA might be the only product on the regular 10 that ends up actually being sellable, not sure if HVM is needed for that.

They are just using the regular 10 to understand what (if) can be done to fix the yield, it's not like Cannonlake will get HVM now.
It doesn't look like that, it is people's wishful thinking.
You don't understand that 10+ is the same 10nm with more mature yields and some minor tweaks ? 10+ can't exist without 10nm working first. They are using the same technology and tools.


Process=/Architecture. So no point bring cannonlake to the discussion.
 
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LTC8K6

Lifer
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I think people is delusional thinking Intel can just ramp 10+ as the initial 10nm process. They are not independent of each other, first 10nm has to work ( in mass production) and with maturity, yield learning and some tweaks then 10+ happens. It is the Samsung with Samsung's Plus versions.

So first product on Intel 10nm will just be 10nm without the "+". Unless Intel marketing wants to call it that way anyway for hype shake.
The first product on 10nm was apparently shipping long ago. So I'd guess that 10nm+ products are already well along towards release.
We apparently had a 10nm+ icelake leak with gen11 IGP in February of this year.
http://edge.alluremedia.com.au/m/g/2018/02/intelsnap.png

I read many times that Intel wasn't even going to use 10nm at all because it was so borked, but abandon it and go right to 7nm.
 

Lodix

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The first product on 10nm was apparently shipping long ago. So I'd guess that 10nm+ products are already well along towards release.
We apparently had a 10nm+ icelake leak with gen11 IGP in February of this year.
http://edge.alluremedia.com.au/m/g/2018/02/intelsnap.png

I read many times that Intel wasn't even going to use 10nm at all because it was so borked, but abandon it and go right to 7nm.
You don't know what the situation really is, it seems...

We got a "first 10nm product" just for marketing. It is a broken tiny SOC with half of the die not working because of terrible yields. So 10nm is not ready yet, not even close. Intel admitted that until some time in 2019 ( couldn't even commit for 1H ) they won't start real mass production of 10nm. ( and we never know if it is just another one of their lies ).

The design of IceLake has been finished long time ago, the problem is 10nm. They could manufacture IceLake in 14nm if they wanted to with some redesings.
 

LTC8K6

Lifer
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You don't know what the situation really is, it seems...

We got a "first 10nm product" just for marketing. It is a broken tiny SOC with half of the die not working because of terrible yields. So 10nm is not ready yet, not even close. Intel admitted that until some time in 2019 ( couldn't even commit for 1H ) they won't start real mass production of 10nm. ( and we never know if it is just another one of their lies ).

The design of IceLake has been finished long time ago, the problem is 10nm. They could manufacture IceLake in 14nm if they wanted to with some redesings.
I'm well aware of the 8121U. It began shipping in December of 2017, which is ~6 months ago now.
We also know that Intel demoed a working 10nm laptop in January of 2017, which is ~18 months ago.
I don't think we will see much, if any, mass production of chips on the original 10nm process.
 

ksec

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Mar 5, 2010
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There is another thing, while Intel is busy trying to ramp up 10nm, Intel are rumoured to be providing all the iPhone Modem this year. They will need another 100M modem / year capacity on 14nm. Where is that coming from?

Are they turning more of their 22nm to 14nm?
 

Lodix

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I'm well aware of the 8121U. It began shipping in December of 2017, which is ~6 months ago now.
We also know that Intel demoed a working 10nm laptop in January of 2017, which is ~18 months ago.
I don't think we will see much, if any, mass production of chips on the original 10nm process.
You still don't get it :S
 

jpiniero

Lifer
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It doesn't look like that, it is people's wishful thinking.
You don't understand that 10+ is the same 10nm with more mature yields and some minor tweaks ? 10+ can't exist without 10nm working first. They are using the same technology and tools.
The situation is such that it looks like any fix is going to need not just process and tooling changes but full respins of the die. Using Cannonlake as a guinea pig to try to figure out what can be done makes a ton of sense, but it's not going to be put into HVM.
 

dullard

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They are not independent of each other, first 10nm has to work ( in mass production) and with maturity, yield learning and some tweaks then 10+ happens.
10+ can't exist without 10nm working first.
Could you expand on this? The difference between 14 nm and 14nm+ included things like fin height, fin pitch, and aspect ratio. How many 14 nm parts are needed to be produced before a company has the ability to change something like fin height? What is stopping the ability to change fin height sooner (in your words, that means that this second fin height can't exist)?
 

Lodix

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Could you expand on this? The difference between 14 nm and 14nm+ included things like fin height, fin pitch, and aspect ratio. How many 14 nm parts are needed to be produced before a company has the ability to change something like fin height? What is stopping the ability to change fin height sooner (in your words, that means that this second fin height can't exist)?
There is no a fixed number or anything, it depends on the maturity of the node. And right now Intel's 10nm just doesn't work.
 

Lodix

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The situation is such that it looks like any fix is going to need not just process and tooling changes but full respins of the die. Using Cannonlake as a guinea pig to try to figure out what can be done makes a ton of sense, but it's not going to be put into HVM.
I didn't say they would release CannonLake for desktop. I am just saying that if next year they launch something manufactured in 10nm it will most likely just be 10nm without the "+". They can call the product what they want.
They are shipping broken tiny SOCs just for marketing. But 10nm is not in mass production.
 

jpiniero

Lifer
Oct 1, 2010
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I didn't say they would release CannonLake for desktop. I am just saying that if next year they launch something manufactured in 10nm it will most likely just be 10nm without the "+". They can call the product what they want.They are shipping broken tiny SOCs just for marketing. But 10nm is not in mass production.
Well as mentioned the only other regular 10nm product that would be realistic is the FPGA, which is kind of a low volume product. I'd say the most likely product that Intel takes into HVM is Icelake client, but even that really depends on if/when Intel fixes the node. And I have to think there's a deadline they have to hit before the 2019 client mix is basically entirely Comet Lake versus some percentage of both.
 

LTC8K6

Lifer
Mar 10, 2004
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They are shipping broken tiny SOCs just for marketing. But 10nm is not in mass production.
We know that, what's your point?

I just posted that 10nm is not in mass production, and that I thought it would never be in mass production.

I think 10nm will remain very low volume, and mass production will begin with 10+.

They aren't likely to mass produce a defective version. They are going to fix it first, I would think.
They can't keep giving away chips to get rid of them.
To me, it makes sense to fix it using a refined 10nm process.
It's been at least 18 months since they had at least one working 10nm chip.

I think they are ramping up 10+, but I guess we will find out in due time.
 
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Thala

Golden Member
Nov 12, 2014
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We know that, what's your point?

I just posted that 10nm is not in mass production, and that I thought it would never be in mass production.

I think 10nm will remain very low volume, and mass production will begin with 10+.

They aren't likely to mass produce a defective version. They are going to fix it first, I would think.
They can't keep giving away chips to get rid of them.
To me, it makes sense to fix it using a refined 10nm process.
It's been at least 18 months since they had at least one working 10nm chip.

I think they are ramping up 10+, but I guess we will find out in due time.
They cannot possibly ramp 10+ before 10. So are you implying they delaying 10nm even further until 10+ is ready? I do not think Intel can afford additional delays - they will bring 10nm into mass production as soon as possible, while 10+ will come later.
 
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