I'm confused about Intels 14nm process lead

[elemein]

Is there an Electrical Engineering program at your university? VLSI layout is typically an undergraduate 4th year class and those students should be able to answer your question. Maybe it's time to make some friends and engineers definitely don't have enough.

Nope, unfortunately no Electric Engineering here :\

 

[III-V]

Is there an Electrical Engineering program at your university? VLSI layout is typically an undergraduate 4th year class and those students should be able to answer your question. Maybe it's time to make some friends and engineers definitely don't have enough.

Jeez, I'm technically 1st year as far as actual major courses go, and I'm trying to take a VLSI class online right now from Coursera. There was a lot I didn't understand at first, with boolean algebra (and I'm still very slow at it), but it sounds like if I can get the hang of things, I'll be giving myself quite the head start.

I guess VLSI is the "end game," for those of us that want to go into it... kind of obvious to me now that knowing how to do VLSI layout in CAD is the last step in actually being in VLSI. Silly realization... but I've just taken so long to get anywhere in school, that I've felt so far away from actually having the know-how to be employable. But really, if I stick with this course, learn the background material necessary, and am able to start designing circuits in CAD or whatever... well, I'm basically at the finish line, and just need to go back and jump through the rest of the hoops I've skipped.

 

[witeken]

Jeez, I'm technically 1st year as far as actual major courses go, and I'm trying to take a VLSI class online right now from Coursera. There was a lot I didn't understand at first, with boolean algebra (and I'm still very slow at it), but it sounds like if I can get the hang of things, I'll be giving myself quite the head start.

Jeez, I feel like I literally know nothing about anything when I read things from all those smart people here!

 

[III-V]

Jeez, I feel like I literally know nothing about anything when I read things from all those smart people here!

It doesn't take much to get the basics down -- you just need to focus. Unfortunately, that's what I'm terrible at.

 

[Fjodor2001]

And really, none of those reasons apply to process nodes. The people who actually need to know the details and make decisions are quite knowledgeable and intelligent. They don't look at actual node names but instead process parameters. And they always have.

I find it strange that the XX μm/nm process node metric was invented in the first place, if it really doesn't serve any purpose at all.

 

[witeken]

It doesn't take much to get the basics down -- you just need to focus. Unfortunately, that's what I'm terrible at.

Focus on what? KhanAcdemy? DrPhysicsA? Wikipedia? Coursera? And which topic? Semiconductors are fine, but there are thousands of things that can also be studied, and it isn't like there is some digital Aristotle for guidance.

For example, take the 'scientific revolution'. Sounds interesting, right? 'Coincidentally', I found a nice book about the topic: How Modern Science Came into the World : Four Civilizations, One 17th-Century Breakthrough (download in linked site). But... Woops, 750 pages. I guess I'm just very inefficient, like spending to much time on this site.

 

[witeken]

I find it strange that the XX μm/nm process node metric was invented in the first place, if it really doesn't serve any purpose at all.

It did.

 

[tweakboy]

One day we will have 1nm ,, then what ? lol run into 24 cvore systems with 48 hreads.

 

[TuxDave]

Jeez, I'm technically 1st year as far as actual major courses go, and I'm trying to take a VLSI class online right now from Coursera. There was a lot I didn't understand at first, with boolean algebra (and I'm still very slow at it), but it sounds like if I can get the hang of things, I'll be giving myself quite the head start.

I guess VLSI is the "end game," for those of us that want to go into it... kind of obvious to me now that knowing how to do VLSI layout in CAD is the last step in actually being in VLSI. Silly realization... but I've just taken so long to get anywhere in school, that I've felt so far away from actually having the know-how to be employable. But really, if I stick with this course, learn the background material necessary, and am able to start designing circuits in CAD or whatever... well, I'm basically at the finish line, and just need to go back and jump through the rest of the hoops I've skipped.

Well, I wouldn't say it's the last steps but it's one of the things you CAN learn that would make the design process less of a black box. There's also VLSI design automation (not "how to use a tool" but "how to design your own tool and optimize a design"). Or there's design verification (rarely taught) or you can just stay away from layout and focus more on the various architectures (CPU/GPU etc....) Or you can go real deep and start focusing on device physics/process development.

So it's not the final step, but it's a potential step depending on what you like to do (and are good at).

 

[imported_ats]

I find it strange that the XX μm/nm process node metric was invented in the first place, if it really doesn't serve any purpose at all.

The original node numbering comes from the ITRS roadmaps that were used throughout the years. These used to be pretty good and accurate overall, but they ran into significant issues once the light sources stopped shrinking. In the olden days, the lithographic light sources were in general the same size or smaller than the actual features being implemented which basically kept everyone on the roadmaps. Once the lightsources stopped shrinking (largely due to the EUV teething issues), the roadmaps started significantly diverging from the actual process.

 

[Fjodor2001]

The original node numbering comes from the ITRS roadmaps that were used throughout the years. These used to be pretty good and accurate overall, but they ran into significant issues once the light sources stopped shrinking. In the olden days, the lithographic light sources were in general the same size or smaller than the actual features being implemented which basically kept everyone on the roadmaps. Once the lightsources stopped shrinking (largely due to the EUV teething issues), the roadmaps started significantly diverging from the actual process.

Previously you wrote here:

And really, none of those reasons apply to process nodes. The people who actually need to know the details and make decisions are quite knowledgeable and intelligent. They don't look at actual node names but instead process parameters. And they always have.

Seems contradictory. In the top quote you say that the metric in fact was useful and accurate for previously process nodes. But then in the second quote you say that it has never been useful anyway, even for older process nodes when it was accurate.

To me it looks like there in fact was a need for this metric in the first place, and it was also useful for older nodes when it was accurate. But nowadays the technology to produce the dies has changed, so the old definition of the metric does no longer provide accurate results. But since there at least once was use for such a metric, it should be useful to define a new metric with a common definition that is up to date with later process tech.

 

[imported_ats]

Seems contradictory. In the top quote you say that the metric in fact was useful and accurate for previously process nodes. But then in the second quote you say that it has never been useful anyway, even for older process nodes when it was accurate.

not at all contradictory. Even when the ITRS roadmap was accurate for feature sizes, it didn't in any way mean that 2 350nm processes were the same. There were numerous parameters that were different between various processes from actual Fmax to metalization and metal related parameters.

To me it looks like there in fact was a need for this metric in the first place, and it was also useful for older nodes when it was accurate. But nowadays the technology to produce the dies has changed, so the old definition of the metric does no longer provide accurate results. But since there at least once was use for such a metric, it should be useful to define a new metric with a common definition that is up to date with later process tech.

The ITRS roadmaps were useful, but not so much for the actual processes themselves but for the equipment manufactures and the fabs to be somewhat on the same page with where they wanted things to go from an equipment perspective. Even given the exact same equipment, two different companies almost always came up with significantly different process recipes, which isn't very shocking when there are thousands of parameters in play with any given process.

I would suggest you stop trying to read things into what is said that simply aren't there.

 

[mikk]

http://www.computerbase.de/2015-02/intel-von-10-und-7-nm-bis-zu-2.5d-und-3d-chips/


Mark Bohr told last week in a webcast that their 10nm chip development progresses 50% faster than their 14nm development.

 

[oobydoobydoo]

http://www.computerbase.de/2015-02/intel-von-10-und-7-nm-bis-zu-2.5d-und-3d-chips/


Mark Bohr told last week in a webcast that their 10nm chip development progresses 50% faster than their 14nm development.

I think they are being very generous on the intel SRAM sizes there, I believe samsung quoted High density and also high performance, and that SRAM is citing samsungs High performance (low density) figures. Intel doesn't say whether it's High Density or High Performance, but intel isn't exactly known to be conservative in its predictions, so we can assume this is the best density they can get.



Also... it has been pointed out by Hans De Vries that even TSMC 20nm Planar is giving A8X much better density than Core M, despite the cited gate pitches.

 

[Arachnotronic]

I think they are being very generous on the intel SRAM sizes there, I believe samsung quoted High density and also high performance, and that SRAM is citing samsungs High performance (low density) figures. Intel doesn't say whether it's High Density or High Performance, but intel isn't exactly known to be conservative in its predictions, so we can assume this is the best density they can get.



Also... it has been pointed out by Hans De Vries that even TSMC 20nm Planar is giving A8X much better density than Core M, despite the cited gate pitches.

No.

 

[mikk]

http://www.anandtech.com/show/8991/...ng-the-benefits-of-14nm-and-going-beyond-10nm

 

[krumme]

The interconnect methology differences means intel get lower density than tsmc - yes - as evident from bw core m vs a8. Gate pitch and s-ram differences here is of minor importance and very small.

But Intels 1d interconnect methology also means higher yield. As evident from eg the huge server cores, where there is minor differences in size meaning no need for harvesting.
The end result is the same but Intel approach seems better for larger cores and their market - the same goes for tsmc.

Heck it turns out nobody is stupid or incompetent but the oposite !

 

[Arachnotronic]

The interconnect methology differences means intel get lower density than tsmc - yes - as evident from bw core m vs a8. Gate pitch and s-ram differences here is of minor importance and very small.

You don't *actually* think the Core M v.s. A8 density comparison is at all valid, do you?

 

[ShintaiDK]

I think they are being very generous on the intel SRAM sizes there, I believe samsung quoted High density and also high performance, and that SRAM is citing samsungs High performance (low density) figures.

Nope.

 

[krumme]

You don't *actually* think the Core M v.s. A8 density comparison is at all valid, do you?

Its not the only example. Historically the difference have always been there go eg look bobcat vs prior atom gen.
Ofcource its different arch and eg cpu vs gpu area but the pattern is the same.
I guess you think a fast transistor is bigger?

 

[Arachnotronic]

Its not the only example. Historically the difference have always been there go eg look bobcat vs prior atom gen.
Ofcource its different arch and eg cpu vs gpu area but the pattern is the same.
I guess you think a fast transistor is bigger?

Look at the kind of density improvement AMD got with Carrizo on the same 28nm process. 30%+ improvement just by using high density libraries.

Do you not think that something like the A8/A8X is using similarly density-tuned libraries while a higher performance/frequency chip like the Core M isn't?

 

[witeken]

http://www.anandtech.com/show/8991/...ng-the-benefits-of-14nm-and-going-beyond-10nm

It was explained that while 10nm will have more masking steps than 14nm, and the delays that bogged down 14nm coming late to market will not be present at 10nm – or at least reduced. We were told that Intel has learned that the increase in development complexity of 14nm required more internal testing stages and masking implementations was a major reason for the delay, as well as requiring sufficient yields to go ahead with the launch. As a result, Intel is improving the efficiency testing at each stage and expediting the transfer of wafers with their testing protocols in order to avoid delays. We were quoted that 10nm should be 50% faster to market than 14nm was as a result of these adjustments.

So Intel has indeed learned and is indeed trying harder.

Does that "50% faster" TTM mean that instead of 2.5 years, 10nm will launch 1.25 years or 15 months after 14nm?

 

[krumme]

http://www.anandtech.com/show/8991/...ng-the-benefits-of-14nm-and-going-beyond-10nm

It looks to me Intel is unfortunately starting to do the same pr crap that the other foundries do. I might as well stop reading Intel stuff as i stopped reading the gf crap 4 years ago, tsmc 2 years ago and samsung was never worth going into details with. Who actually use that stuff - lol.

They claim cost per transistor goes down following the historical trend. And that 10nm is more easy and faster ton get than 14nm.
That will be truly great and worth celebrating with some new gear. But I think i will wait and see what happens.

 

[Arachnotronic]

So Intel has indeed learned and is indeed trying faster.

Does that "50% faster" TTM mean that instead of 2.5 years, 10nm will launch 1.25 years or 15 months after 14nm?

15 months after 14nm would imply product in the market in late 2015/early 2016. I don't think that's realistic.

 

[witeken]

15 months after 14nm would imply product in the market in late 2015/early 2016. I don't think that's realistic.

It depends on which date you pick (you could take February for higher volumes), but maybe they meant 1.5x faster, then it would be 18 months from 14nm. In any case, it's a lot better.