I'm confused about Intels 14nm process lead

[Idontcare]

Well except people trying to compare density between two processes based on two designs that are operating at upwards of 3x+ clock speed differences for the majority of the area...

We've been over this area before. The comparison is at best invalid and at worst disingenuous. Transistor numbers are not a reliable comparison point without much more data on how they were derived. Nor is comparing density between two products with widely varying frequency optimization points.

So true.

Even further, it does nothing to deconvolute the impact of unknown but surely disparate investments made into the development of the products as well.

A team of 1500 engineers budgeted 4 years and $500M to develop a chip is going to result in a vastly more optimized IC versus the company that challenges a team of 500 engineers to develop a chip in 3 years with a budget of $200M.

The history of IBM's CELL 90nm->65nm->45nm shrink (including why the 45nm didn't, intentionally so, shrink as much as one might have expected based on the 45nm vs. 65nm process specs alone) is perhaps the best annotated and readily available example of recent times.

In the 45 nm CELL processor presentation, IBM was rightfully proud to boast that it was able to dramatically lower power consumption of the processor with minimal design resources – estimated at (low) ten’s of man-years of design effort spent in the successful port of a highly complex modern processor from one process technology to another process technology. The low amount of (re)design effort was no doubt the result of efficient application of effort by the team that contributed the ten’s of man-years of effort. But it is also fundamentally enabled by a highly automated design flow that started with the re-use of the basic floorplan and highly automated shrinks of the basic functional blocks. The cost of the design methodology and low power focus means that the die size scaling was far from linear.

 

[Dave2150]

I think Intel will begin high volume production on 10nm in Q2 2016.

They haven't even started high volume of 14nm, your mentally challenged if you think 10nm will be in mass production in Q2 2016.





Insults and personal attacks are not allowed in the tech forums.



esquared
Anandtech Forum Director

 

[ShintaiDK]

They haven't even started high volume of 14nm, your mentally challenged if you think 10nm will be in mass production in Q2 2016.

14nm is in high volume production and have been for some time.

 

[Dave2150]

14nm is in high volume production and have been for some time.

All that's on the market are the 2 core Broadwell-U chips. Hardly mass availability either - still few and far between from what I've seen.

If they were mass producing these 14nm parts now - where are the quad cores? Where are the desktop chips?

Would intel simply stockpile them awaiting a future launch date, hoping to clear the 22nm Haswell stock first?

 

[ShintaiDK]

All that's on the market are the 2 core Broadwell-U chips. Hardly mass availability either - still few and far between from what I've seen.

If they were mass producing these 14nm parts now - where are the quad cores? Where are the desktop chips?

Would intel simply stockpile them awaiting a future launch date, hoping to clear the 22nm Haswell stock first?

14nm for Desktops will first come with Skylake. Desktop is the small market. Its all about mobile.

And there is quite more models out than that.

 

[Fjodor2001]

I guess you could say that Intel has high volume production in certain 14 nm segments, more specifically some specific mobile U/Y-models.

But to consider Intel having general high volume production on 14 nm, I'd say they have to provide chips across all or most of their segments, and in large quantities. I.e. primarily including all or most mobile and desktop models (and/or possibly server) too. And they are not there yet.

 

[kimmel]

All that's on the market are the 2 core Broadwell-U chips. Hardly mass availability either - still few and far between from what I've seen.

If they were mass producing these 14nm parts now - where are the quad cores? Where are the desktop chips?

Would intel simply stockpile them awaiting a future launch date, hoping to clear the 22nm Haswell stock first?

How many millions of chips do they need to be selling to OEMs for you to consider it "mass production"? "mass production" has qualifier has very little to do with your particular SKU desires.

But to consider Intel having general high volume production on 14 nm, I'd say they have to provide chips across all or most of their segments, and in large quantities. I.e. primarily including all or most mobile and desktop models (and/or possibly server) too. And they are not there yet.

Move them goalposts.

 

[Dave2150]

I guess you could say that Intel has high volume production in certain 14 nm segments, more specifically some specific mobile U/Y-models.

But to consider Intel having general high volume production on 14 nm, I'd say they have to provide chips across all or most of their segments, and in large quantities. I.e. primarily including all or most mobile and desktop models (and/or possibly server) too. And they are not there yet.

Yes, fully agree. 14nm still seems to be in it's infancy - we're yet to see any quad cores for example.

 

[kimmel]

Yes, fully agree. 14nm still seems to be in it's infancy - we're yet to see any quad cores for example.

If TSMC can only produce 16nm products for Apple but not Qcom then they can't qualify for "mass production"? I don't understand your reasoning at all.

 

[ShintaiDK]

Yes, fully agree. 14nm still seems to be in it's infancy - we're yet to see any quad cores for example.

Quadcore mobile is a niche product.

How many chips do Intel need to ship to forfill your requirement? Or is it all about shipping quadcores or desktop?

 

[krumme]

So true.

Unsubstantiated.
The usual strawman about design - does not change the fact the numbers for years fairly consistently have shown the same pattern. And its not like the differences in density was small.

 

[imported_ats]

Unsubstantiated.
The usual strawman about design - does not change the fact the numbers for years fairly consistently have shown the same pattern. And its not like the differences in density was small.

Design isn't a strawman, in fact its a central core issue. I suppose you think the IBM/GF 22nm process is super undense as well... It only has 2x the transistors in 6x the area...

 

[krumme]

Design isn't a strawman, in fact its a central core issue. I suppose you think the IBM/GF 22nm process is super undense as well... It only has 2x the transistors in 6x the area...

I dont know anytning about ibm/GF 22nm process, and who cares for GF anyway. If thats the benchmark ...

What about explaining more in depth - instead of the usual headlines - what it is in the apple A8 that makes it so dense since you dont beliewe its process tech?

Its not like the cpu cores are small vs. intel. And its not like the performance is slow. Who exactly is producing performance cores? What is atom and core ipc vs A8?

 

[krumme]

If anyone want to see how most in this forum thinks of Intel and proces tech go look this recent thread:
http://forums.anandtech.com/showthread.php?t=2404898

Under the title:
[ASML] Intel to introduce EUV in 2016

Its telling how uncritical things is. Go read it. Its history lesson one.

When we talk density. Its about time someone brings some more solid fact to the table, otherwice the actual numbers for density stand.

 

[kimmel]

Different designs yield differently. Yes, but that has no bearing on calling something high volume or not. Especially not for two additional cores that had to yield reasonably well for the dual core part to start with.

 

[III-V]

Yes, fully agree. 14nm still seems to be in it's infancy - we're yet to see any quad cores for example.

They're supposedly having issues with parametric yields -- chips capable of high frequency aren't coming out of the oven.

 

[Idontcare]

Unsubstantiated.
The usual strawman about design - does not change the fact the numbers for years fairly consistently have shown the same pattern. And its not like the differences in density was small.

Unsubstantiated?

Ever been part of a design team?

 

[III-V]

If anyone want to see how most in this forum thinks of Intel and proces tech go look this recent thread:
http://forums.anandtech.com/showthread.php?t=2404898

Under the title:
[ASML] Intel to introduce EUV in 2016

Its telling how uncritical things is. Go read it. Its history lesson one.

When we talk density. Its about time someone brings some more solid fact to the table, otherwice the actual numbers for density stand.

It was logical to guess that Intel would be the first to adopt EUV, as they're the first adopter for virtually everything.

People who guessed it'd be Intel, in most cases, were just better informed about the industry. That doesn't mean they're biased -- really, it's the opposite.

Also, you can be well-informed and still be wrong on occasion -- you're just less likely to.

 

[Idontcare]

So Intel has indeed learned and is indeed trying harder.

Does that "50% faster" TTM mean that instead of 2.5 years, 10nm will launch 1.25 years or 15 months after 14nm?

EETimes has an article in which they directly quote Bohr:

We may have underestimated the learning rate with a technology that adds many more masks as 14nm did with multi-patterning. That slowed us down more than expected, but we are up to high yields now with more than one product in production and more coming this year.

At 10nm [we’re] running 50% faster in steps per day through the fab, increasing the rate of wafer movement. I think that will keep 10nm on track…[We’re] getting very good area scaling and cost per transistor reduction in 10nm. In our development fab we’ve sped up the move of wafers to offset the increased number of mask steps.

This is a completely different meaning than that which was presented in the Anandtech article. I'm going to assume the Anandtech article author misunderstood the meaning of Bohr's comments in writing the original Anandtech article.

Based on Bohr's actual quote, Bohr was referring to the cycle-time of a 10nm wafer versus a 14nm wafer. Not referring to any specific timeline.

Merely saying the 10nm wafers experience 50% more steps per day than a 14nm wafer. Which means the 10nm wafers go through the fab faster than 14nm wafers unless 10nm wafers require 50% more processing steps than 14nm wafers.

But nothing Bohr spoke of says anything about the 10nm production timeline.

There was another little tidbit though:

Bohr declined to comment on what new materials or circuit structures Intel will use beyond its tall, thin fins at 14nm. However, he noted Intel researchers “have published more than a couple papers on III-V devices as one example of a new material being considered by our research group.”

I take that as a " "

 

[witeken]

EETimes has an article in which they directly quote Bohr:

This is a completely different meaning than that which was presented in the Anandtech article. I'm going to assume the Anandtech article author misunderstood the meaning of Bohr's comments in writing the original Anandtech article.

Based on Bohr's actual quote, Bohr was referring to the cycle-time of a 10nm wafer versus a 14nm wafer. Not referring to any specific timeline.

Merely saying the 10nm wafers experience 50% more steps per day than a 14nm wafer. Which means the 10nm wafers go through the fab faster than 14nm wafers unless 10nm wafers require 50% more processing steps than 14nm wafers.

But nothing Bohr spoke of says anything about the 10nm production timeline.

That makes sense, given all the different interpretations I'm reading on Fudzilla, ET, AT.

Do you know how it's possible to have such a dramatic increase in wafer throughput and how that will improve yield learning?

I think "we’ve sped up the move of wafers to offset the increased number of mask steps" is important since that probably enables them to basically go back to 22nm levels of yield improvements, I guess.

There was another little tidbit though:

I take that as a " "

Considering that he uses "considering", which is just plain false since he told us in 2012 that 10nm had been pinned down, I guess we might be on to something.

I'm also kind of surprised that Intel is having low hopes on EUV, which makes them spend lots of time developing a good yielding and low-cost 7nm node, but I guess waiting for EUV would delay the development process because how else would they create 7nm node transistors before EUV arrives in '16?

 

[krumme]

Unsubstantiated?

Ever been part of a design team?

Instead of posing question we all know the answer to go read your post in the thread i linked. If one is stuck in preunderstanding reality can be difficult to see no matter the competence.

I still miss the argument why bw and a8 differs so much for density.

 

[witeken]

I still miss the argument why bw and a8 differs so much for density.

It should be clear as a matter of fact that it has nothing to do with the lithography: anyone can do the math and see that 14nm has a 60% higher density than 16nm and has 10% or 30% denser SRAM.

Differences in density per mm² may include design decisions to make BDW suitable for up to 5GHz while Cyclone goes to a meager 1.5GHz; deliberate use of a less dense (higher performance) production process; a higher portion of the silicon die may not have any transistors; a difference in how the transistors are counted (Intel uses schematic count); BDW could have a substantially higher larger portion of its area dedicated to logic, which has a lower density (e.g. NAND is already approaching 100B transistors).

 

[krumme]

It was logical to guess that Intel would be the first to adopt EUV, as they're the first adopter for virtually everything.

People who guessed it'd be Intel, in most cases, were just better informed about the industry. That doesn't mean they're biased -- really, it's the opposite.

Also, you can be well-informed and still be wrong on occasion -- you're just less likely to.

Are you to young to remember eg soi and copper?

For 2 month prior to the thread i linked i was sugesting Intel was perhaps not first for euv. There was plenty signs going that direction and many said the same. Excepts the usual 10 on anandtech cpu forum.
The result was i had a personal stalker following me until reality just was just to much.
What exactly is it of knowlegde i dont know about Intel that shintai, mrmt and others know? - and why is it that the knowledge they have always makes them wrong? What kind of special knowledge is that?

Still what exactly is it in density that gives bw far worse density than a8 when a8 is a big high perf core?

 

[krumme]

It should be clear as a matter of fact that it has nothing to do with the lithography: anyone can do the math and see that 14nm has a 60% higher density than 16nm and has 10% or 30% denser SRAM.

Differences in density per mm² may include design decisions to make BDW suitable for up to 5GHz while Cyclone goes to a meager 1.5GHz; deliberate use of a less dense (higher performance) production process; a higher portion of the silicon die may not have any transistors; a difference in how the transistors are counted (Intel uses schematic count); BDW could have a substantially higher larger portion of its area dedicated to logic, which has a lower density (e.g. NAND is already approaching 100B transistors).

We agree its not lithography

Why not contribute it to the difference in methology for connecting the metal layers?

I doubt Intel with its ressources and high volume waste a lot of unused space where there is no transistors.

And what "designs" is it that makes 4ghz use that more space than 1.5ghz? - because this is only the cpu part. And what critical paths is so damn important for Intel but not for apple for eg power optimization that laying those out uses that much space?

I am not saying its impossible but just highly unlikely. The arguments is stretched while the confronting argument is just far more likely and straight forward.

 

[dahorns]

We agree its not lithography

Why not contribute it to the difference in methology for connecting the metal layers?

I doubt Intel with its ressources and high volume waste a lot of unused space where there is no transistors.

And what "designs" is it that makes 4ghz use that more space than 1.5ghz? - because this is only the cpu part. And what critical paths is so damn important for Intel but not for apple for eg power optimization that laying those out uses that much space?

I am not saying its impossible but just highly unlikely. The arguments is stretched while the confronting argument is just far more likely and straight forward.

You've had two people involved in chip design tell you that there are differences. Isn't that enough evidence that there may be something to it?