I'm confused about Intels 14nm process lead

[witeken]

We agree its not lithography

Why not contribute it to the difference in methology for connecting the metal layers?

I doubt Intel with its ressources and high volume waste a lot of unused space where there is no transistors.

And what "designs" is it that makes 4ghz use that more space than 1.5ghz? - because this is only the cpu part. And what critical paths is so damn important for Intel but not for apple for eg power optimization that laying those out uses that much space?

I am not saying its impossible but just highly unlikely. The arguments is stretched while the confronting argument is just far more likely and straight forward.

http://forums.anandtech.com/showpost.php?p=37157739&postcount=36

 

[krumme]

You've had two people involved in chip design tell you that there are differences. Isn't that enough evidence that there may be something to it?

I am not disputing there is differences. Ofcource there is! eg. how much is automatic routing, interconnetc tech, l3 area vs cpu logic whatever.

 

[krumme]

http://forums.anandtech.com/showpost.php?p=37157739&postcount=36

Good thread
Now it would be nice to get a step deeper.
Eg why is 1d 2d layer not important for density but matters a lot for yield?

As i said go look at the old atom vs bobcat. Same huge differences in density.

 

[TuxDave]

And what "designs" is it that makes 4ghz use that more space than 1.5ghz? - because this is only the cpu part. And what critical paths is so damn important for Intel but not for apple for eg power optimization that laying those out uses that much space?

Higher frequency -> Less time to do logic -> Need for faster transistors -> Bigger transistors

As for which critical paths? All of them!

 

[witeken]

Higher frequency -> Less time to do logic -> Need for faster transistors -> Bigger transistors

As for which critical paths? All of them!

How do bigger transistors affect efficiency at lower frequencies?

 

[krumme]

Higher frequency -> Less time to do logic -> Need for faster transistors -> Bigger transistors

As for which critical paths? All of them!

But that brings us back to the argument that bw u cpu plus l3 running at high freq is only 20% of the area.
Unless that asumption is wrong?:
http://forums.anandtech.com/showthread.php?p=37157792

 

[TuxDave]

How do bigger transistors affect efficiency at lower frequencies?

If the bigger transistors were bigger because you needed it for high frequency designs, then it'll be suboptimal at low frequency.

But that brings us back to the argument that bw u cpu plus l3 running at high freq is only 20% of the area.
Unless that asumption is wrong?:
http://forums.anandtech.com/showthread.php?p=37157792

I believe that statement was using the "CPU is high frequency" and "CPU takes 20% of the die area". Not sure why that contradicts the statement that high frequency designs = bigger transistors.

(and I noticed this other post)

I am not disputing there is differences. Ofcource there is! eg. how much is automatic routing, interconnetc tech, l3 area vs cpu logic whatever.

What I would do first is settle the "how we count" problem before going down to those differences. That one introduces the largest margin of error.

 

[krumme]

I believe that statement was using the "CPU is high frequency" and "CPU takes 20% of the die area". Not sure why that contradicts the statement that high frequency designs = bigger transistors.
.

Well it doesnt. It just underlines that high freq differences between a8 and bw can only explain a minor part of the density differences. Thats how i read Hans De Vries argument.

What I would do first is settle the "how we count" problem before going down to those differences. That one introduces the largest margin of error.

Good point

I dont really care much for who is eg highest performant or densest, but what is interesting to me in that regard is eg a little insight when and how that "how to count" is changed internally and why?

 

[Exophase]

Higher frequency -> Less time to do logic -> Need for faster transistors -> Bigger transistors

As for which critical paths? All of them!

And I've said it before many times, but if you design a CPU that can clock to 4GHz but is never deployed beyond 1.5GHz you've got a very suboptimal CPU. This is true at all levels of the uarch, even if you need to change the transistor types and layout and what have you to reach 1.5GHz. The higher frequency design will simply need more clock cycles for many of the same operations than the lower frequency design. This will need more pipelining which will require better branch prediction, and the increased result latencies of some operations will need more cache, reordering, prefetching, etc to maintain similar IPC.

I'm going to wait and see how high Carrizo ends up clocking, but if it caps at something like 3.5GHz turbo it'll be a real waste of a design, given that I expect for the most part it'll still be true to its original speed demon design intended to hit ~5GHz in normal consumer parts (even if that fell short too). The increased L1 dcache is a good concession away from this, but I doubt they've improved the branch mispredict penalty or substantially changed the L2 cache latency. But I'm really basing this on the lack of IPC change.

 

[TuxDave]

I dont really care much for who is eg highest performant or densest, but what is interesting to me in that regard is eg a little insight when and how that "how to count" is changed internally and why?

I'm sure equalizing the way we count matters to the people who are in charge of investigating whether or not there's any waste in the design process. That same person probably has no authority to make that knowledge public. So then it's some executive/legal/whatever guy from high above that probably needs to weigh the "is revealing more detail about our design worth the PR?".

The last time I've seen that happen is when the x86 myth was all over the place and they probably felt that it was a most urgent matter.

 

[imported_ats]

I dont know anytning about ibm/GF 22nm process, and who cares for GF anyway. If thats the benchmark ...

What about explaining more in depth - instead of the usual headlines - what it is in the apple A8 that makes it so dense since you dont beliewe its process tech?

Its not like the cpu cores are small vs. intel. And its not like the performance is slow. Who exactly is producing performance cores? What is atom and core ipc vs A8?

Oh, I don't know, how about Fmax for the entire design is ~1.4Ghz and that makes up roughly 10-15% of the total die. The vast majority of the die is running at <~450mhz. If you haven't been able to figure out how frequency and density of inversely linked, Its not my job to give you an education on VLSI design.

 

[imported_ats]

Well it doesnt. It just underlines that high freq differences between a8 and bw can only explain a minor part of the density differences. Thats how i read Hans De Vries argument.

You do realize that like 99% of the BDW die is designed to run at ~Fmax+ for the fastest part of the A8, right? And that only about 10-15% of the A8 die actually runs at its Fmax with roughly 80-85% of the die running at <= ~450mhz.

You have practically no understanding of the actual designs, no understanding of any design process, no understanding of anything related for semiconductor performance and density. I nor others have either the time or inclination to teach these things to you. Y

 

[Enigmoid]

For the record core M uses the same chip as BW-U GT2.

Which runs up to 3.2 ghz on the cpu + cache and 950 mhz on the igp.

 

[Abwx]

You have practically no understanding of the actual designs, no understanding of any design process, no understanding of anything related for semiconductor performance and density. I nor others have either the time or inclination to teach these things to you. Y

That s the whole point of a forum, to ask informations from thoses who are knowledgeable...

 

[imported_ats]

That s the whole point of a forum, to ask informations from thoses who are knowledgeable...

The information has already been given, it has been ignored, its not the job of anyone here to teach other people 4+ years of university level knowledge.

 

[Abwx]

The information has already been given, it has been ignored, its not the job of anyone here to teach other people 4+ years of university level knowledge.

There s no need of such level to understand how a transistor work in very simple fashion, but for sure that explaining what makes it fast or slow or efficient require abilities in vulgarization from the knowledgeable and a little effort at grasping some very basic analog design principles on the noob side, indeed it looks like the difficulty is that people are not aware that "digital" circuitries are actualy analog circuitries...

I pointed that there s a good article about semiconductors recently published at AT, people can read it and ask for explanations in this forum.

 

[III-V]

Another example of density being inversely related to frequency is one Idontcare mentioned in response to a question I asked him. I'd asked about the rumor that Intel was having parametric yield issues -- their desktop and high performance laptop parts not hitting high enough clocks -- and he suggested that it was likely an issue with dopant implantation. The fact that 14nm has fins that are both taller, and packed closer together, makes it more difficult to evenly dope a fin without affecting its nearest neighbors. He stated that this would affect the high clock speed part of the spectrum more, since you're always bound by the lowest common denominator -- lower clocking parts aren't affected nearly as much, unless things are really broken.

I'd also asked what could be done to achieve better yields, as I was concerned if Skylake would run into the same issues, and he responded that the troublesome circuits can be spaced out more, allowing the dopants to be implanted without interference.

But I'm really basing this on the lack of IPC change.

Yeah, a measly 5%, which I find a bit surprising. You'd think there being big room for improvement would make said improvement easier... and that certainly ended up being the case with Piledriver.

 

[JDG1980]

Yeah, a measly 5%, which I find a bit surprising. You'd think there being big room for improvement would make said improvement easier... and that certainly ended up being the case with Piledriver.

AMD has limited resources for R&D. The Bulldozer architecture is a dead end; no point in throwing good money after bad. Zen and the cat cores take priority; their best CPU designers will be working on those.

 

[III-V]

AMD has limited resources for R&D. The Bulldozer architecture is a dead end; no point in throwing good money after bad. Zen and the cat cores take priority; their best CPU designers will be working on those.

Well, most of the work for Excavator would have been completed some time ago. Although a lot of it did probably take place post-layoffs.

 

[witeken]

You do realize that like 99% of the BDW die is designed to run at ~Fmax+ for the fastest part of the A8, right? And that only about 10-15% of the A8 die actually runs at its Fmax with roughly 80-85% of the die running at <= ~450mhz.

What would happen with Broadwell if it was adjusted to have the same (or up to 60% higher) density as Apple's A8? Surely you could place a lot more transistors on the die for a much better IGP?

 

[witeken]

Another example of density being inversely related to frequency is one Idontcare mentioned in response to a question I asked him. I'd asked about the rumor that Intel was having parametric yield issues -- their desktop and high performance laptop parts not hitting high enough clocks -- and he suggested that it was likely an issue with dopant implantation. The fact that 14nm has fins that are both taller, and packed closer together, makes it more difficult to evenly dope a fin without affecting its nearest neighbors. He stated that this would affect the high clock speed part of the spectrum more, since you're always bound by the lowest common denominator -- lower clocking parts aren't affected nearly as much, unless things are really broken.

Interesting hypothesis, but not sure if true.

It doesn't a allow me to quote, but see transistor performance and variation.

http://www.intel.com/content/dam/ww...foundry/intel-14nm-iedm-2014-presentation.pdf

 

[carop]

Have the transistor count and die size of 14nm Cherry Trail been announced?

 

[NTMBK]

I still miss the argument why bw and a8 differs so much for density.

Just look at Carrizo vs Kaveri. Same 28nm SHP process, but Carrizo is far more dense. Why? Because of the design.

 

[carop]

why is 1d 2d layer not important for density but matters a lot for yield?

The claim that 1D metals are density neutral or have better density than 2D metals is just a load of bollocks.

1D metals require restricted design rules which decrease effective density, and more metal layers are needed.

 

[krumme]

What would happen with Broadwell if it was adjusted to have the same (or up to 60% higher) density as Apple's A8? Surely you could place a lot more transistors on the die for a much better IGP?

what about 22nm atoms density?