Globalfoundries 7LP 7nm Leading Performance FINFET process and FX-7 ASIC platform

[raghu78]

https://www.globalfoundries.com/new...ver-leading-performance-7nm-finfet-technology

Santa Clara, Calif., June 13, 2017 – GLOBALFOUNDRIES today announced the availability of its 7nm Leading-Performance (7LP) FinFET semiconductor technology, delivering a 40 percent generational performance boost to meet the needs of applications such as premium mobile processors, cloud servers and networking infrastructure. Design kits are available now, and the first customer products based on 7LP are expected to launch in the first half of 2018, with volume production ramping in the second half of 2018.

https://www.globalfoundries.com/sites/default/files/product-briefs/7lp-product-brief.pdf

Technology Overview
• Twin-well CMOS bulk FinFET
• 5 Core device Vt’s
• Two gate dielectrics: thin (SG) and medium I/O (EG)
• Full suite of passive devices
• Optional MIM capacitor, eFuse
• VDD: 0.75V nominal or 0.85V overdrive
• Standard temperature range: -40°C to 125°C
• Optical lithography based process with EUV compatibility
• Up to 17 layers of metallization

Application-optimized Platform Extensions

High Performance - 5GHz operation Server, Data Center, ASICs

https://www.semiwiki.com/forum/content/6837-globalfoundries-7nm-euv-update.html

Globalfoundries 7LP vs 14LPP

> 40% performance improvement
> 60% lower power
> 2x transistor density
30% cost reduction (45% for target segments)
2H 2018 volume production

https://www.forbes.com/sites/patric...-with-7nm-and-5nm-announcements/#11130f244730

https://www.design-reuse.com/news/42169/globalfoundries-7nm-asic-platform.html

GLOBALFOUNDRIES Launches 7nm ASIC Platform for Data Center, Machine Learning, and 5G Networks
FX-7 offering leverages the company’s 7nm FinFET process to deliver best in class IP and Solutions

Santa Clara, Calif., June 13, 2017 – GLOBALFOUNDRIES today announced the availability of FX-7 TM, an application-specific integrated circuit (ASIC) offering built on the company’s 7nm FinFET process technology. FX-7 is an integrated design platform that combines leading-edge manufacturing process technology with a differentiated suite of intellectual property and 2.5D/3D packaging to deliver the industry’s most complete solution for data center, machine learning, automotive, wired communications, and 5G wireless applications.


There is a very good possibility of 7nm Zen 2 and Navi by late 2018 or Q1 2019. The GL 7LP process looks very competitive with Intel 10nm and TSMC 7nm for performance, power and area. GF with IBM's expertise in developing high performance nodes is shaping up to be a strong alternative to TSMC for bleeding edge high performance process nodes among foundries. 7LP is optimized for High performance and 5 Ghz operation. Looks very good for Zen 2

 

[scannall]

Looks like all those IBM engineers are doing some great things at GF.

 

[Phynaz]

http://www.eetimes.com/document.asp?doc_id=1331887

More details here.

 

[raghu78]

GF is being very secretive about their metal pitch and contacted gate pitch. If they hit a 64% shrink from 14nm as they said last year then GF 7LP will be the world's most dense process node in 2019.

http://semiengineering.com/to-7nm-and-beyond/

"7nm has a pretty aggressive scaling factor. It’s a 64% reduction in area to compensate for the fact that you have additional masks."

I think a 30-45% cost reduction which GF claim for 7nm vs 14nm which includes the much higher wafer cost of 7nm needs a 1.5 node shrink ( 1 node = 50% 2 node = 75%) .

Edit : My revised calculations for GF 7LP area shrink is 55% based on the availability of a 6 track library at 7LP vs a 7.5 track library at 14LPP which was the densest library option for that process.

 

[itsmydamnation]

For its 7nm ASIC process, Globalfoundries claims it has unique 60 and 112 Gbit/s serdes from its IBM heritage.

http://www.eetimes.com/document.asp?doc_id=1331887&page_number=2
I wonder what they mean by this? its a strange way to phrase it, is that data rate per pin?

 

[rainy]

That's a great news for AMD and of course second generation of Zen - for about 18 or bit more months AMD should be even more competitive to Intel than it's now.

 

[raghu78]

Here are a few thoughts and guesses on GF's 7nm contacted gate pitch and metal pitch after looking at the 7LP product brief. There is support for 6 track and 9 track library at 7LP. If the 64% shrink is correlated with the availability of a 6 track library at 7LP vs a 7.5 track library at 14LPP which was the densest available option then 20% area shrink comes from the lower track library.

Cell Area (Contacted Gate pitch * Metal pitch) * Track height

14 LPP = 78 * 64 * 7.5
7LP = ( ) * 6

7LP is a 64% shrink

X * 6 = 0.36 * 4992 * 7.5
X (Cell Area) = 2240 Approx

Assuming a contacted pitch of 56nm and metal pitch of 40 nm works out to cell area of 56 * 40 = 2240

The actual shrink in terms of Contacted Gate pitch * Metal Pitch is around 55% .

7LP vs 14LPP = 56 * 40 / 78 * 64 = 0.45 approx

This also agrees well with Gary Patton's statement

https://www.hpcwire.com/2017/06/13/globalfoundries-7nm-chips-coming-2018-euv-2019/

The platform integrates 17 million gates per square millimeter, over a 50 percent scaling off of 14nm. GlobalFoundries Chief Technology Officer Gary Patton noted, “Because of the need for multi patterning on these nodes, the complexity is increasing more than it has done historically. We scale a little bit more than 50 percent so when we add the higher complexity we still end up at the right point for our customers, which is at least a 30 percent die cost improvement and for some products maybe as much as 45 percent cost improvement.”

TSMC N7 is expected to have a 40nm metal pitch and a contacted gate pitch of 54nm .Intel 10nm has a metal pitch of 36nm and a contacted gate pitch of 54nm. So this puts GF 7LP at roughly the same density as TSMC N7 and slightly behind Intel. The performance looks to be even better than TSMC N7 with a high performance version optimized for 5 Ghz operation (which I assume will use the 9 track library) .GF 7LP looks to probably provide the highest performance for a foundry process. It will be interesting to see GPUs manufactured at TSMC N7 HPC (Nvidia) vs GPUs manufactured at 7LP (AMD). GF has a 7nm+ with EUV which will provide even better performance and a further area shrink a year later. Some of the interesting contests in terms of process and actual products using the process

GF 7LP Zen 2 vs Intel 10+ Icelake
GF 7LP+ Zen 3 vs Intel 10++ Tigerlake
GF 7LP Navi vs TSMC N7 HPC Nvidia
GF 7LP+ Next gen vs TSMC N7+ HPC Nvidia

For TSMC N7 estimates and Intel 10nm actual specs you can read
https://www.semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html

 

[beginner99]

There is a very good possibility of 7nm Zen 2 and Navi by late 2018 or Q1 2019.

I believe it when the reviews are in. For now it looks like your typical foundry PR.

 

[krumme]

I believe it when the reviews are in. For now it looks like your typical foundry PR.

Add GF keeps the record of unrealistic foundry PR. By far. They have to earn the trust now and it takes time.

 

[Abwx]

http://www.eetimes.com/document.asp?doc_id=1331887&page_number=2
I wonder what they mean by this? its a strange way to phrase it, is that data rate per pin?

https://en.wikipedia.org/wiki/SerDes

 

[NTMBK]

Only 2x transistor density over 14nm? How on earth can they justify calling this 7nm?

 

[ThatBuzzkiller]

Only 2x transistor density over 14nm? How on earth can they justify calling this 7nm?

Depends on source I guess. Semiaccurate says 2x density improvement but from the interview Semiengineering did with Gary Patton and Thomas Caulfield it's roughly ~2.17x more dense (1/0.64 = 2.17) ...

And it also sounds like GF could improve the density with their next iteration of 7nm technology using EUV this time if that's not enough ...

 

[krumme]

Yep probably. And then they will call it 5nm

 

[Atari2600]

Only 2x transistor density over 14nm? How on earth can they justify calling this 7nm?

They don't understand the properties of 1D and 2D "shapes"...

 

[itsmydamnation]

https://en.wikipedia.org/wiki/SerDes

i know what SerDes are.... what i mean in given a Gbit/s rate is odd because its a throughput not a clock rate, so if the interface was 16bits wide then the quoted numbers aren't impressive..... if it is 1 bit wide then it is very impressive.

 

[raghu78]

Only 2x transistor density over 14nm? How on earth can they justify calling this 7nm?

Slightly > 2x transistor density . 64% with the inclusion of a 6 track library. In my calculations it works out to 55% for Contacted Gate Pitch * Minimum metal pitch.

GF 7LP - 56 nm CMP and 40nm MMP = 2240 sq nm (CMP * MMP)
TSMC N7 - 54nm CMP and 40nm MMP = 2160 sq nm
Intel 10nm - 54 nm CMP and 36 nm MMP. = 1944 sq nm

GF 7LP is roughly the same density as TSMC N7. Both of them are slightly behind Intel 10nm. The performance of 7LP is very impressive . > 40% perf increase at iso power vs 14 LPP. Bodes well for AMD 7nm CPUs and GPUs.

 

[raghu78]

Add GF keeps the record of unrealistic foundry PR. By far. They have to earn the trust now and it takes time.

GF 7LP is a process ready for customer designs and tapeouts with PDKs available. No customer including AMD will commit to tapeouts if the process is not ready. Lisa Su confirmed 7nm tapeouts later this year. I am pretty sure they are at GF 7LP given GF is the preferred foundry and AMD have wafer targets to meet under WSA. IBM's process development expertise combined with GF high volume manufacturing expertise is a very good combination and the initial results are very promising. There is a very good chance of 7nm Zen 2 by late Q1 2019 or early Q2 2019. 7nm Navi could come even earlier given GPU designs take less time from tapeout to volume production.

 

[Abwx]

i know what SerDes are.... what i mean in given a Gbit/s rate is odd because its a throughput not a clock rate, so if the interface was 16bits wide then the quoted numbers aren't impressive..... if it is 1 bit wide then it is very impressive.

It should be a two conductors differential transmission line, this could be two pins + ground eventually.

This amount to 112GHz since such lines use quasi sinusoidal signals, FTR a CPU that work at 4GHz require a clock signal that include harmonics up to those frequencies to get clean rising and falling hedge to reduce cross conduction losses.

 

[CatMerc]

5GHz operation High Performance vs >3GHz operation High Performance.

Looks like GloFo are trying to be the highest performance 7nm node out of the gate, while Samsung and TSMC remain in the low power SoC realm. This is no doubt influenced by AMD's needs for Zen 2 and Navi.

 

[raghu78]

5GHz operation High Performance vs >3GHz operation High Performance.

Looks like GloFo are trying to be the highest performance 7nm node out of the gate, while Samsung and TSMC remain in the low power SoC realm. This is no doubt influenced by AMD's needs for Zen 2 and Navi.

The main driver for GF processes at 7nm and future nodes is IBM and AMD high performance CPU designs. IBM has a heritage of going for the highest possible transistor performance. GF 7LP is IBM 7nm . IBM drives the Research alliance with GF and Samsung by doing fundamental research at the transistor level and materials. GF and Samsung adopt that research and bring the tech to high volume manufacturing. IBM's 5nm GAA FET is going to power the next major process nodes from Samsung (4LPP) and GF (node not yet named).

Zen 2 could easily have turbo clocks of 5 Ghz with max clocks going further as the process has been designed for very high frequency CPU designs.

 

[SarahKerrigan]

The main driver for GF processes at 7nm and future nodes is IBM and AMD high performance CPU designs. IBM has a heritage of going for the highest possible transistor performance. GF 7LP is IBM 7nm . IBM drives the Research alliance with GF and Samsung by doing fundamental research at the transistor level and materials. GF and Samsung adopt that research and bring the tech to high volume manufacturing. IBM's 5nm GAA FET is going to power the next major process nodes from Samsung (4LPP) and GF (node not yet named).

Zen 2 could easily have turbo clocks of 5 Ghz with max clocks going further as the process has been designed for very high frequency CPU designs.

This.

IBM has shipped server processors at 5.5GHz. That isn't going to happen on a low-power process.

 

[maddie]

The main driver for GF processes at 7nm and future nodes is IBM and AMD high performance CPU designs. IBM has a heritage of going for the highest possible transistor performance. GF 7LP is IBM 7nm . IBM drives the Research alliance with GF and Samsung by doing fundamental research at the transistor level and materials. GF and Samsung adopt that research and bring the tech to high volume manufacturing. IBM's 5nm GAA FET is going to power the next major process nodes from Samsung (4LPP) and GF (node not yet named).

Zen 2 could easily have turbo clocks of 5 Ghz with max clocks going further as the process has been designed for very high frequency CPU designs.

That 7LP name will cause a lot of confusion. Many will keep saying Low Power instead of Lead performance. Why not call it HP outright?

 

[Ajay]

This.

IBM has shipped server processors at 5.5GHz. That isn't going to happen on a low-power process.

Yes, but at a higher power consumption level that wouldn't be competitive in the x86 server market. So, I'm curious what AMD will do with Zen2. Zen has excellent perf/watt - AMD needs to maintain that while increasing overall performance to match or exceed That of Intel's CPUs (10nm+?). Interesting times

 

[Atari2600]

Yes, but at a higher power consumption level that wouldn't be competitive in the x86 server market.

That'd depend on how the voltage gradient is with frequency. If its quite favourable, then at , say, 3.5 GHz, you could still have a very efficient many-core CPU.


Don't forget, in the market where power consumption is critical, many cores at lower frequencies tend to be much more acceptable.

For enthusiasts - power consumption isn't such a big deal.

 

[raghu78]

Yes, but at a higher power consumption level that wouldn't be competitive in the x86 server market. So, I'm curious what AMD will do with Zen2. Zen has excellent perf/watt - AMD needs to maintain that while increasing overall performance to match or exceed That of Intel's CPUs (10nm+?). Interesting times

AMD has a lot of low hanging fruit to pick with regards to improvements from Zen . I think AMD will definitely aim for >=10% higher IPC and 50% higher core counts with Zen 2 along with a physical design optimized for 5 Ghz operation. I think we will see Zen on 14nm+ hit 4.5 Ghz turbo and Zen 2 on GF 7LP to hit 5 Ghz turbo comfortably with even further OC headroom. Zen 2 for servers will be clocked at much lower clock speeds around 3-3.5 Ghz for a 48C/96T CPU.