Discussion Future ARM Cortex + Neoverse µArchs Discussion

[NostaSeronx]

RISC-V won't replace ARM until something revolutionary happens like Smartphones in the computing space.

This is actually over complicating things. RISC-V will start to replace ARM once it goes from for "Advanced/Experts" to for "Novice/Newbs" in basics.

#1 - Buy a RISC-V computer with an operating system, everything works out of the box.
#2 - As well as the ability to download generic-images for RISC-V to replace/reinstall OS:
"debian-12.5.0-amd64-DVD-1.iso" // "debian-12.5.0-arm64-DVD-1.iso" // fyi: riscv64 generic-image is due by mid-2025 for Debian.

For example the first OS to support RISC-V is not generic-image'd:
openkylin-cdimage/1.0.1/openKylin-1.0.1-x86_64.iso <-- generic image (Targets all AMD64 processors (Intel/AMD/Zhaoxin))
openkylin-cdimage/1.0.1/openKylin-1.0.1-visionfive2-riscv64.img.xz <-- JH7110-target
openkylin-cd/1.0.1/openKylin-1.0.1-licheepi4a-riscv64.ext4.xz <-- TH1520-target

For example, ARM in desktop has yet to leap to generic-image other than Windows on ARM(Qualcomm[Newb]/Rockchip[Expert]/Ampere[Expert]):
openkylin-cd/1.0.1/openKylin-1.0.1-raspi-arm64.img.xz Rasp Pi Target
openkylin-cd/1.0.1/openKylin-1.0.1-coolpi-arm64.img.xz RK3588 Target

OpenKylin is likely to get an generic-image with the next-wave of CN cores:
T-head C920 = RVA22 + Vector
Nuclei UX1000 = RVA22 + Vector {Xiaomi-related}
SpacemiT X100 = RVA22 + Vector {Xiaomi-related}
Sophgo RXU (3.x) = RVA22 + Vector
Institute of Computing Technology, CAS Kunminghu (3rd Gen core) = RVA22 + Vector {Tencent-related}
StarFive, Dubhe-100[ or whatever] = RVA22 + Vector
SiFive CN, P670 = RVA22 + Vector [+ Vector Crypto]

Each successive generation of RISC-V will fundamentally operate closer to x86-64 (RVA(xy) ~ x86-64v(x)). Especially, since every new high-end RISC-V core is faster than KX-6000:

x86-64 Lujiazui @ 3 GHz​	RISC-V CN Top-end @ 3 GHz​
SpecInt 2006 - 29.2​	SpecInt 2006 - 41​
SpecFP 2006 - 38​	SpecFP 2006 - 44​

The other scenario is Hyperscalers moving from ARM to RISC-V:

Kunpeng 920 Chipset

Kunpeng 920 is the industry's leading-edge Arm-based server CPU in the industry. The processor adopts 7Nm manufacturing process and is authorized based on ARM architecture. Under the typical dominant frequency, the specific benchmark score exceeds 930, exceeding the industry benchmark by 25%.

www.hisilicon.com

Yitian 710

Your Chips and Semi News

fuse.wikichip.org

Which is likely to happen next year for both Hisilicon and T-head. Starfive/Baidu has a 256-core part in the works.

x86-64 (60%) and ARM (40%) -> CN, Hyperscalers // RISC-V replacing ARM is more significant in CN.
x86-64 (90%) and ARM (10%) -> Global, Hyperscalers

As well is how many devkits can be launched from this: https://developer.huawei.com/consum...e18a77267ccb/606cf023ba064610a501211b63cfeeae
As well as how fast Tencent can port their Gaming Library over to RISC-V.
- 552.4 million/$37.63 billion spent => CN Gamers vs 212 million/$23.92 billion spent => US Gamers

#1. How fast desktops take after RISC-V's ISA stabilizes.
#2. How fast Hyperscalers move to RISC-V ISA after ISA maturity.
#3. Everything else.

 

[Nothingness]

Legacy support ain't so important nowadays - it's pretty much enough that there is emulation layer to support existing software.

That worked well for Itanium.

 

[FlameTail]

ARM Cortex X5

+50% performance increase

 

[naukkis]

That worked well for Itanium.

x86 is hard to translate to any other ISA but Apple and Windows are doing it fine today for aarch64. Arm to risc-V and other way around isn't big deal at all, should except near native performance.

 

[Nothingness]

x86 is hard to translate to any other ISA but Apple and Windows are doing it fine today for aarch64. Arm to risc-V and other way around isn't big deal at all, should except near native performance.

I've been implementing simulation models for the last 30 years, including dynamic code generation; the instructions themselves are not the problem (well except flag emulation is quite costly especially on an architecture that doesn't have flags in its core spec such as R-V). The memory model on the other hand is. Apple had to alter the AArch64 memory model to support x86. So is the RISC-V memory model close enough to AArch64? Does RISC-V support the 3 semaphore semantics of AArch64? And last but not least why do you assume R-V would have to translate AArch64 and not x86?

EDIT: BTW we've been polluting several threads with RISC-V discussions; we should move to specific R-V threads 😀

 

[Nothingness]

ARM Cortex X5

+50% performance increase

Source?

 

[eek2121]

Itanium comparison might be extreme, but in the long run, ARM has a huge established software base. RISC-V won't replace ARM until something revolutionary happens like Smartphones in the computing space.

That isn’t necessarily true. Google is porting Android to RISC-V and you can certainly expect them to do an in house RISC-V SoC at some point unless contractual agreements forbid it.

Apple has been quiet about RISC-V. This also mostly goes for AMD. Intel has been all over the place. Amazon, Meta, and other large tech firms have either experimented with it, or are working on designs.

R&D takes years, and RISC-V hasn’t been out that long.

It will get here, eventually.

 

[FlameTail]

Source?

My imagination!

That isn’t necessarily true. Google is porting Android to RISC-V and you can certainly expect them to do an in house RISC-V SoC at some point unless contractual agreements forbid it.

Apple has been quiet about RISC-V. This also mostly goes for AMD. Intel has been all over the place. Amazon, Meta, and other large tech firms have either experimented with it, or are working on designs.

R&D takes years, and RISC-V hasn’t been out that long.

It will get here, eventually.

Qualcomm recently released a RISC-V watch SoC for Google'a WearOS.

 

[NostaSeronx]

I've been implementing simulation models for the last 30 years, including dynamic code generation; the instructions themselves are not the problem (well except flag emulation is quite costly especially on an architecture that doesn't have flags in its core spec such as R-V). The memory model on the other hand is. Apple had to alter the AArch64 memory model to support x86. So is the RISC-V memory model close enough to AArch64? Does RISC-V support the 3 semaphore semantics of AArch64? And last but not least why do you assume R-V would have to translate AArch64 and not x86?

EDIT: BTW we've been polluting several threads with RISC-V discussions; we should move to specific R-V threads 😀

RISC-V's progress is relatable to Cortex+Neoverse. Once they hit the market they will start affecting ARM's roadmaps.

RISC-V from ARM and Power :: RVWMO (~2019-ratification)
RISC-V from x86 and SPARC :: RVTSO (~2022-ratification)
RISC-V Dynamic RVTSO is still in the works but is being fast-tracked: https://github.com/riscv/riscv-ssdtso
"The Ssdtso extension adds a 'dynamic-RVTSO' mode of operation. It is supported only on implementations that default to RVWMO semantics."
MicrosoftXTA = Software TSO
AppleRosetta2 = Hardware TSO
MicrosoftXTRV = Hardware TSO (likely)

Ascalon/Veyron -> Cortex X/Neoverse V series
Rest of RISC-V RVA cores -> Cortex A/Neoverse N series

The thing to watch out for is the Intel Arc effect. Where it pulled from both Nvidia's share and AMD's share. ARM's Cortex-X minipc/laptop market is very small. Even, if lets say Nvidia/Mediatek join that group. They will be more affected by RISC-V also going into that market.

Cortex-X5C/Cortex-A725CorA730C will have to compete with RISC-V's swarm of minipc/laptop/desktop targets.

 

[SarahKerrigan]

Itanium also failed because Intel thought it was a great idea to rely on compiler improvements to extract performance from a brain dead ISA.

Itanium didn't fail.

 

[Nothingness]

Itanium didn't fail.

It sunk?

Sorry I can't say if you're being serious or not 😑

 

[SarahKerrigan]

It sunk?

Sorry I can't say if you're being serious or not 😑

Itanium was a successful replacement for PA in HP's product line. It produced many years of good (and highly profitable) sales for HP, including migrating the bulk of its PA base. It outsold SPARC and wasn't far behind Power for much of its lifetime. It hit solid performance for some time (Montecito, Power6, and Core2 Xeon were all at fairly similar performance levels in '07-ish.) It has many thousands of users on it today. It had active CPU development for over a decade - longer than Alpha did.

One could argue it "failed" in the limited sense that merchant-processor sales were never huge, but from the perspective of HP and the Integrity product line, IPF did fine.

 

[igor_kavinski]

One could say that the ISA failed and died. Once the last Itanium CPU putters out, it will probably be relegated to live inside emulation.

 

[soresu]

RISC-V's progress is relatable to Cortex+Neoverse. Once they hit the market they will start affecting ARM's roadmaps.

RISC-V from ARM and Power :: RVWMO (~2019-ratification)
RISC-V from x86 and SPARC :: RVTSO (~2022-ratification)
RISC-V Dynamic RVTSO is still in the works but is being fast-tracked: https://github.com/riscv/riscv-ssdtso
"The Ssdtso extension adds a 'dynamic-RVTSO' mode of operation. It is supported only on implementations that default to RVWMO semantics."
MicrosoftXTA = Software TSO
AppleRosetta2 = Hardware TSO
MicrosoftXTRV = Hardware TSO (likely)

Ascalon/Veyron -> Cortex X/Neoverse V series
Rest of RISC-V RVA cores -> Cortex A/Neoverse N series

The thing to watch out for is the Intel Arc effect. Where it pulled from both Nvidia's share and AMD's share. ARM's Cortex-X minipc/laptop market is very small. Even, if lets say Nvidia/Mediatek join that group. They will be more affected by RISC-V also going into that market.

Cortex-X5C/Cortex-A725CorA730C will have to compete with RISC-V's swarm of minipc/laptop/desktop targets.

You are still starting from a position absent of software.

You need more than just OS and compiler support - you need actual apps otherwise no one will actually use it.

3 years after the M1 Mac there are still applications lacking ARM ports, and that is after years of ARMv8-A hardware provenance to produce competent coders for the platform.

AI/ML could speed up a RISC-V software transition, but it still isn't going to happen anytime soon when they are only just in the middle of a major transition to ARM at the moment.

 

[eek2121]

You are still starting from a position absent of software.

You need more than just OS and compiler support - you need actual apps otherwise no one will actually use it.

3 years after the M1 Mac there are still applications lacking ARM ports, and that is after years of ARMv8-A hardware provenance to produce competent coders for the platform.

AI/ML could speed up a RISC-V software transition, but it still isn't going to happen anytime soon when they are only just in the middle of a major transition to ARM at the moment.

Software is a mixed bag. It really depends on what you use. For my productivity use case, all my software works on mac, ARM, or RISC-V except 2 applications, which are closed source. They do work on Wine, however, just not on RISC-V/ARM. For gamers? forget it. Come back in 10-15 years.

RISC-V currently is seeing a ton of pickup in the AI space.

 

[igor_kavinski]

It's all gonna change in a matter of weeks or months when AI gains the ability to translate code from one architecture to any other. All it needs is training on source code for applications with different architecture binaries.

 

[SarahKerrigan]

One could say that the ISA failed and died. Once the last Itanium CPU putters out, it will probably be relegated to live inside emulation.

By that standard, SPARC and Alpha are also failures. Nobody's doing new design on either.

 

[camel-cdr]

This is actually over complicating things. RISC-V will start to replace ARM once it goes from for "Advanced/Experts" to for "Novice/Newbs" in basics.

#1 - Buy a RISC-V computer with an operating system, everything works out of the box.
#2 - As well as the ability to download generic-images for RISC-V to replace/reinstall OS:
"debian-12.5.0-amd64-DVD-1.iso" // "debian-12.5.0-arm64-DVD-1.iso" // fyi: riscv64 generic-image is due by mid-2025 for Debian.

For example the first OS to support RISC-V is not generic-image'd:
openkylin-cdimage/1.0.1/openKylin-1.0.1-x86_64.iso <-- generic image (Targets all AMD64 processors (Intel/AMD/Zhaoxin))
openkylin-cdimage/1.0.1/openKylin-1.0.1-visionfive2-riscv64.img.xz <-- JH7110-target
openkylin-cd/1.0.1/openKylin-1.0.1-licheepi4a-riscv64.ext4.xz <-- TH1520-target

For example, ARM in desktop has yet to leap to generic-image other than Windows on ARM(Qualcomm[Newb]/Rockchip[Expert]/Ampere[Expert]):
openkylin-cd/1.0.1/openKylin-1.0.1-raspi-arm64.img.xz Rasp Pi Target
openkylin-cd/1.0.1/openKylin-1.0.1-coolpi-arm64.img.xz RK3588 Target

OpenKylin is likely to get an generic-image with the next-wave of CN cores:
T-head C920 = RVA22 + Vector
Nuclei UX1000 = RVA22 + Vector {Xiaomi-related}
SpacemiT X100 = RVA22 + Vector {Xiaomi-related}
Sophgo RXU (3.x) = RVA22 + Vector
Institute of Computing Technology, CAS Kunminghu (3rd Gen core) = RVA22 + Vector {Tencent-related}
StarFive, Dubhe-100[ or whatever] = RVA22 + Vector
SiFive CN, P670 = RVA22 + Vector [+ Vector Crypto]

Each successive generation of RISC-V will fundamentally operate closer to x86-64 (RVA(xy) ~ x86-64v(x)). Especially, since every new high-end RISC-V core is faster than KX-6000:

x86-64 Lujiazui @ 3 GHz​	RISC-V CN Top-end @ 3 GHz​
SpecInt 2006 - 29.2​	SpecInt 2006 - 41​
SpecFP 2006 - 38​	SpecFP 2006 - 44​

The other scenario is Hyperscalers moving from ARM to RISC-V:

Kunpeng 920 Chipset

Kunpeng 920 is the industry's leading-edge Arm-based server CPU in the industry. The processor adopts 7Nm manufacturing process and is authorized based on ARM architecture. Under the typical dominant frequency, the specific benchmark score exceeds 930, exceeding the industry benchmark by 25%.

www.hisilicon.com

Yitian 710

Your Chips and Semi News

fuse.wikichip.org

Which is likely to happen next year for both Hisilicon and T-head. Starfive/Baidu has a 256-core part in the works.

x86-64 (60%) and ARM (40%) -> CN, Hyperscalers // RISC-V replacing ARM is more significant in CN.
x86-64 (90%) and ARM (10%) -> Global, Hyperscalers

As well is how many devkits can be launched from this: https://developer.huawei.com/consum...e18a77267ccb/606cf023ba064610a501211b63cfeeae
As well as how fast Tencent can port their Gaming Library over to RISC-V.
- 552.4 million/$37.63 billion spent => CN Gamers vs 212 million/$23.92 billion spent => US Gamers

#1. How fast desktops take after RISC-V's ISA stabilizes.
#2. How fast Hyperscalers move to RISC-V ISA after ISA maturity.
#3. Everything else.

T-head C920 = RVA22 + Vector

This is a misconception, C910 pretty much equals C920, e.g. the SG2042 is listed as having C920 cores, but RVV 0.7.1. There will be a C920 version with RVV 1.0 support with the SG2044, but honestly the performance isn't that interesting compared to the other stuff that is supposed to release in 2024.

Nuclei UX1000 = RVA22 + Vector {Xiaomi-related}

I haven't seen that one before, looks neat.

SpacemiT X100 = RVA22 + Vector {Xiaomi-related}

Will be quite interesting for developers, I hope there will be an SBC this year. It has 7.5 SPECint2k6/GHz, so lower than the P670 (>12 SPECint2k6/GHz), but it has a VLEN=256, hypervisor extension, and has some interesting fusion targets: "[...] load ALU operation coalescing, load ALU store operation coalescing"
The P670 fusion targets currently listed in llvm don't seem all that expansive, although it might just be that they didn't add all of them to llvm yet.
There is a slim chance, that the Banana Pi BPI-F3 will have it as their core, see this.

Sophgo RXU (3.x) = RVA22 + Vector

Also looks cool, but well probably need to wait some time until we see it in hardware. As far as I know there is only this slide-deck about it.

Institute of Computing Technology, CAS Kunminghu (3rd Gen core) = RVA22 + Vector {Tencent-related}

I'm not aware of any plans to fab this outside of validation purposes, the RTL isn't even ready yet. But the cool thing is that it's open source they target 45 SPECint2k6 @ 3GHz, so 15/GHz. This will be, if it isn't already, the most powerfull open source CPU.

StarFive, Dubhe-100[ or whatever] = RVA22 + Vector

Dubhe-90 is the one with RVV support (VLEN=256) with 9.4 SPECInt2006/GHz. I'd expect a dev board this year, we've seen them upload to the riscv-test-reports, and a few kernel commits referenced the JH-8110.

SiFive CN, P670

I'm really getting my hopes up for the SG2380, as said above the target is >12 SpecINT2k6/GHz, and we are likely to see hardware at the end of the year.

 

[NostaSeronx]

You are still starting from a position absent of software.

You need more than just OS and compiler support - you need actual apps otherwise no one will actually use it.

3 years after the M1 Mac there are still applications lacking ARM ports, and that is after years of ARMv8-A hardware provenance to produce competent coders for the platform.

AI/ML could speed up a RISC-V software transition, but it still isn't going to happen anytime soon when they are only just in the middle of a major transition to ARM at the moment.

Mac OS is a closed ecosystem so Rosetta2 is good enough till developers pay someone to port. Asahi Linux is open ecosystem but is only a sub-slice of the Mac OS quantity of developers.

For gamers? forget it. Come back in 10-15 years.

The only reason we haven't gotten Godot games on RISC-V. Is that VF2 = BXE-4-32 and TH1520 = BXM-4-64 have the distros only supporting OpenGL ES.

Which is also the same issue for Qualcomm(a7xx/SQ3 and Snapdragon X[competitor to Cortex-X])/Mediatek+Nvidia(NVK): https://www.phoronix.com/news/Mesa-24.1-Zink-D3D12-Default

2024-05-01

24.1.0-rc4

or 24.1.0 final

It is a race for adoption: $600+ for ARM(Cortex series) or >$150(minimum price so far w/o discount) for RISC-V(Bunch of series potentially releasing).

Unity runtime on Arm-based Windows devices | Unity Blog

Unity runtime support is now available for Windows on Arm devices.

blog.unity.com

 

[Doug S]

It's all gonna change in a matter of weeks or months when AI gains the ability to translate code from one architecture to any other. All it needs is training on source code for applications with different architecture binaries.

Porting C code from ARM to RISC-V or whatever is not what makes such a transition costly. It is the testing (I don't care how good you think "AI" is, it still has to be tested just like you have to test human ported code) and supported.

There's also a massive amount of infrastructure around ARM, especially in the embedded world, that takes time to build up. It happened over more than a decade for ARM, it can't happen overnight for a different ISA no matter how much overly inflated expectation for what "AI" is able to do that one throws at it.

 

[soresu]

It is a race for adoption: $600+ for ARM(Cortex series) or >$150(minimum price so far w/o discount) for RISC-V(Bunch of series potentially releasing).

Is it though?

Devkits =/= mass adoption.

RISC-V has no mass adoption consumer facing platform as yet.

Snapdragon X Elite is poised to seriously increase WoA adoption just as more serious apps are porting to it, and as Mediatek, nVidia and likely Samsung pile on too that momentum will only increase probably culminating in the first native AAA games for the platform within the next couple of years.

I don't see RISC-V interests just pulling that out of their hat anytime soon.

I'm not saying I'm not interested - but I just don't think that the market is there yet.

 

[soresu]

All this being said can we stop derailing ARM threads now with RISC-V talk?

 

[NostaSeronx]

Dubhe-90 is the one with RVV support (VLEN=256) with 9.4 SPECInt2006/GHz. I'd expect a dev board this year, we've seen them upload to the riscv-test-reports, and a few kernel commits referenced the JH-8110.

It is going to be called Dubhe-125:

Dubhe-125: RV64GCBVH => X1 Target
Dubhe-90: RV64GCBH => A76 Target
Dubhe-80: RV64GCBVH => >A75 Target

Is it though?

Devkits =/= mass adoption.

RISC-V has no mass adoption consumer facing platform as yet.

Snapdragon X Elite is poised to seriously increase WoA adoption just as more serious apps are porting to it, and as Mediatek, nVidia and likely Samsung pile on too that momentum will only increase probably culminating in the first native AAA games for the platform within the next couple of years.

I don't see RISC-V interests just pulling that out of their hat anytime soon.

I'm not saying I'm not interested - but I just don't think that the market is there yet.

Devkits can lead to mass adoption based on how fast they bring developers. The cheaper it is the faster the adoption of developers.

Snapdragon X Elite is unlikely to be a significant increase on adoption of Windows on ARM. The future platform that uses newer Cortex-X cores will be the one that will be the mainstream product: 10 X4 cores + 4 A720 cores


CN Mobile AAA games are possible on the TH1520 for "Performance Tier" while the SG2380 having the bigger iGPU gets bumped up to "HD Tier".

Unity forms new venture to manage China operations | Unity Blog

Unity China will unlock new opportunities for partnering with local companies and help increase R&D investment to better serve the needs of the Chinese creator community.

blog.unity.com

It is very likely that CN Exclusive RISC-V ports will exist. ==> "... will be designing exclusive games specifically for the HarmonyOS operating system.[A] -- The agreement will not only cover exclusive games but also include existing titles.[C]"

团结引擎 - 手册: OpenHarmony requirements and compatibility

docs.unity.cn

团结引擎 - 手册: Android requirements and compatibility

docs.unity.cn

Both of these already are being worked on with the TH1520 (Quad-core), it will only be faster with the SG2380 (16-core). How fast these are done will determine the speed for Windows. This shift will be big because it is the largest ARM market shifting away to RISC-V. With the big stick for western RISC-V ports being this company:


Games are generally the first thing to get ported if there is demand: CryTek announced immediately in 2003 -> 2005 (FC64) and Atari didn't announce (SO:RM64) 2004. However, adjust that to AAA/AAAA CN Games which have already agreed to make ports.

If the partnership is held:
SG2380 w/ P670(Gen: 2024) -> Cortex-A78 :: 5W phone target in original document as well as 30W mini-desktop target with a 16x PCIe G4 slot.
SGnext w/ P870(Gen: 2025 ;; 24G2, 25G1, 25G2[CNGA]) -> Cortex-X class core (X2~X3 on Int and A710~A720 on FPU)
SGnext2 w/ Napa(Gen: 2026 ;; 25G2, 26G1, 26G2[CNGA]) -> Cortex-X class core (unknown architecture config)

It is unlikely Neoverse V4 will be competitive against the RISC-V datacenter cores that release shortly after it. RISC-V's launch will most likely lead Cortex/Neoverse to have larger IPC jumps. Since, x86-64 couldn't enter the smartphone market and x86-64 dense cores aren't cost-competitive with ARM cores.

Neoverse V5/N5 and Cortex X6/X7 must have a large IPC jump as RISC-V designs can extract higher ILP below 2000-entry ROBs. The second wave of CN cores is going to be on-par with Neoverse N3, all HiPerf CN RV64 designs will be beyond this:


The cost is important in the rate of adoption:

64-core N3 Dev Kit​	Higher Cost​
64-core N1 Dev Kit​	~$3300​
64-core C920 (RVA22+V-2023gen)​	Lower Cost​
64-core C910 (RVA22-2023gen)​	~$2500​

"the unit(T-head) is launching an initiative to encourage around 150,000 developers to learn about and get international credentials on the open-source chip design(RISC-V) architecture."
"The first Android device based on Xuantie(T-head) RISC-V will also be commercialized on a large scale in 2024."
The news article didn't disclose if there will be a C930/XT930 for it. Since the C910/C920 are A72/A73 target and designed for 2020. The 1H'24 budget smartphones for Cortex-A is the Cortex A76 @ 2.7 GHz. If it leaps to A78-perf like the P670, nothing to worry about. While, if it leaps to Cortex X-perf since it has been almost five years since prior cores showcase in Jul 25, 2019. Then, future Cortex/Neoverse cores will need to compete with RISC-V.

C910/C920 V-behavior:
VLEN=128, LMUL=1 and LMUL=2 executes in single op.

C930 V-behavior if it is X-class/V-class and way more advanced:
VLEN=128; LMUL=1, LMUL=2, LMUL=4 executes a single op. 512-bit w/ 8 regs
VLEN=256; LMUL=1 and LMUL=2 executes a single op. 512-bit w/ 16 regs
VLEN=512; LMUL=1 executes a single op. 512-bit w/ 32 regs

SVE2 will need to adopt this, if other RISC-V architectures adopt this behavior.

SOPHGO's Target: "In 2025, RISC-V will welcome an estimated 1 million+ RISC-V application developers, while RISC-V will enter the world's supercomputing TOP500 in 2025"
One of SOPHGO's partners for the above plan is Microsoft APRD associated.

CN RISC-V has the less than best cores but are targeting 2024 for PCs/Mobile devices. <== this determines the NA RISC-V adoption rate.
NA RISC-V has the best cores but are targeting 2025 for PCs and 1H2026 for Mobile devices. <== With no CN effect.
"on Arm apparently looking to change its royalty model from one based on chip value to one based on device value." <== Change of model is this year.

Cortex/Neoverse going up in price is going to need to come up with a big performance increase. Or, everyone Xiaomi, Oppo, Vivo, etc will simply switch to RISC-V. As the target is to get RISC-V in some volume in Android 15/OpenHarmony later in the year.

CN Then​	CN Now​
First to latest ARM​	First to latest RISC-V​
Bleeding edge ARM patches to linux/android​	Bleeding edge RISC-V patches to linux/android​

Also, probably need to keep RISC-V discussions. Just in case ARM decides to MIPS itself and releases RISC-V Cortex/Neoverse IP. As well as Cortex/Neoverse once again switching version numbers: ARMvA(/10)-A for SME2 mandatory designs.

 

[FlameTail]

Will the lack of SMT in client ARM cores that will be used in PCs be a problem?

A lot of software in the PC is optimised for x86, and that also means it is optimised for multithreading as well.

Especially gaming.

People say most games are optimised for 6 or 8 cores. What that really means is it is optimised for 6 cores/12 threads or 8 cores/16 threads. (Correct me if I am mistaken).

 

[NostaSeronx]

Will the lack of SMT in client ARM cores that will be used in PCs be a problem?

A lot of software in the PC is optimised for x86, and that also means it is optimised for multithreading as well.

Especially gaming.

People say most games are optimised for 6 or 8 cores. What that really means is it is optimised for 6 cores/12 threads or 8 cores/16 threads. (Correct me if I am mistaken).

The lack of SMT in client won't be significant enough for gaming. Vulkan/DX12 gaming leans more to SMT=Off having the highest FPS.

ARM can lean towards more energy efficiency with aiming for dead/gated units. Rather than completely filled units and thrashed regs/renames/caches/etc.

The real issue will be discrete GPUs. Since, both ARM's and Qualcomm's solutions are laptop leaning. So, it is going to hit that iGPU wall where x86-64 desktop can just slap latest phat dGPU in.

The only case for a successful ARM takeover for PC gaming is not adopting SMT but rather getting into the desktop market. Where CN gets it, Qualcomm/ARM will most likely never get it.


As well as SMT being replaced by BT [Bulk threading]. Ideal solution is >4 Cortex-X prime cores and >8 Cortex-A energy efficient dense option cores.

Where most of the back-end for games are being switched to bulk cores(Cortex A) while the front-end is handled by prime cores(Cortex X).