This isn't a AMD BD thread . Stop baiting. Start a BD topic keep it out of this topic. Were not talking BD. I heard enough with the PhI and how great it would be.
AMD doesn't have AVX VEX prefix Which I assume to be the jit compiler . That is why AMD doesn't have it. Intel doesn't have to share jit compilers with AMD.
Vexprefix has everthing to do with sse2 instructions. Which to me is a hugh deal. 20% IPC improvement not 5% Bob has one so we know. The App running in this video runs all 4 cores with 8 threads . If intel can get all 4 cores to do as your saying with turbo mode I be very surprised because were not seeing that at all.
Thanks for the incentive to read more detailed info about Ct,AVX,the Vex prefix and SSE2, i think i'm beginning to understand where you're getting at. Now as for the SB sample your friend Bob has and the 20% ipc across the board claims you make, if thats from a ES and on very premature bios/microcode support, its very impressive, to say the least.
