EETimes: ST plans for Dresden FDSOI production

Discussion in 'CPUs and Overclocking' started by Idontcare, Jan 21, 2013.

  1. Idontcare

    Idontcare Elite Member

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    Dude! :eek: Don't ever do that again! Don't walk into a thread and so cavalierly drop an otherwise innocously looking link only to walk away as if that was all there was to it.

    I almost missed your link because it didn't look like there was much to it, but that link has lots of great nuggets of info buried inside.

    Please please please next time you find great links like this include a few select quotes from it as well, use flashing lights, arrows, whatever it takes to get some attention to it ;)

    I mean look at what they have here:

    big.Little just got one-upped right there :eek:

    And what about this gem:

    Boom, testimonial evidence that supports ST's claim that porting designs from 28nm bulk to FD-SOI really are as simple as claimed.

    And what about the results of the port from bulk to FD-SOI?

    That is basically the performance and power benefits of a node shrink on its own.

    Great link SocketF :thumbsup:
     
  2. grimpr

    grimpr Golden Member

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    Damn thats great info indeed! This looks like it will work wonders for AMDs chips.
     
  3. mrmt

    mrmt Diamond Member

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    Something fishy here. First STM wants to pull out of the joint venture, and then I found this:

    Ericsson wiped out the asset on its balance sheet. That's 0 recoverable value, zip, nil, nada, and nobody stepped in to take the leftovers. Too drastic for a company that had such a good IP.
     
  4. Hitman928

    Hitman928 Golden Member

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    http://www.reuters.com/article/2012/12/10/us-stmicroelectronics-st-ericsson-idUSBRE8B90N520121210

    The join venture has nothing to do with FD-SOI from ST from everything I've seen. Basically, ST-Ericsson has been unprofitable since its foundation and has really taken a beating as its biggest customer (Nokia) has gone down the tubes. But this is completely separate from the parent company's work on FD-SOI. It seems that ST-Ericsson is pretty much doomed but ST hasn't decided what to do with it yet and this new chip is a flagship design utilizing their parent companies best new process, probably their last push to do something big and turn a profit to stop the axe from falling. If nothing else, ST probably saw it as a chance to prove their process before letting ST-Ericsson out to pasture.
     
  5. mrmt

    mrmt Diamond Member

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    The JV has everything to do with 28nm FDSOI. Why would you pull out of a JV if you just developed a truly competitive, disruptive product?

    Just trying to be skeptical and FD-SOI might turn out what STM is saying, but I find rather strange for them to pull out now when they hit the jackpot with FDSOI.

    The problem is that the sword already fell on them. STM already said they would pull out and Ericsson wrote down the entire asset, which means they are expecting 0 returns from STE. It may be a honey-trap to attract buyers.
     
  6. Hitman928

    Hitman928 Golden Member

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    The disruptive product is FD-SOI, this is developed by the parent company STM, not ST-Ericsson. STE is a join venture between STM and Ericsson and is a a wireless processor / platform developer. STE has lost money ever since coming into existence in 2009 due mainly to their main customer slipping in market share and bad margins. STM saw the writing on the wall and got out, but this does not effect their other businesses.

    Like I said, most likely this is Ericsson's last attempt at making a profit before shutting it down for good (notice, the doors are still open, technically) and/or STM made a push (as no doubt there are still former STM people there) to get STE to make a "proof of concept" product for their new process.

    The last paragraph is just conjecture on my part, but either way, you can't link FD-SOI to ST-Ericsson as they have nothing to do with it besides porting a product to the process.

    Edit: Just as a note, I have my doubts about FD-SOI going forward as well, just because of SOI's difficulties in general over the years, but that doesn't change anything I wrote above.
     
  7. mrmt

    mrmt Diamond Member

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    What I'm trying to point out, and I think the concern is valid, is that the benefits of the SOI technology are being touted by an undead JV and its parent company, we have no independent means to verify SOI claims, not only about performance but on ease of manufacturing and costs too.

    And if FD-SOI claims are true then STE has a winning horse on its hands and why would you sell your race ticket now that your horse will be ahead of the pack in the next curve? Sure, I can still think of a few scenarios where both STM and Ericsson would want to pull out regardless of how good STE chips were, but I also can think in a scenario where spectacular claims are made in order to attract buyers. When both parts in the JV declared their intention of pulling out and one of them wrote off the entire stake, it's advisable to take those claims with sizable quantities of salt.
     
  8. Ajay

    Ajay Platinum Member

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    I don't expect an enthusiast big core product, I think AMD is committed to two big core products; APUs (Kavari) and Opterons (which will need >> 4 modules) and will not be suited to desktop usage.

    I think there is enough R&D evidence that the performance and power improvements are real. I think what needs to be proven is the ease of porting bulk-SI to FD-SOI and whether or not it is cost effective in a high volume production environment.

    STM has some sort of contract with GF. If I had to guess, it's to prove the later item on GF equipment, but I haven't seen any details of the deal and don't expect to unless it's a success.
     
    #83 Ajay, Jan 28, 2013
    Last edited: Jan 28, 2013
  9. Idontcare

    Idontcare Elite Member

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    My process technology background and experience with SOI compels me to be suspicious of ST's claims...but it costs me nothing to take them at their word until proven otherwise.

    That said, perhaps what is more telling here is what is not being said (and who is electing to not say anything).

    Global Foundries is central to all of this, and no foundry shies away from the opportunity to sing their own praises when it comes to process technology capability and timeline. In fact, if anything they over-sell their capability and over-hype their timeline to such an extent that the reader usually builds in an expected "reality factor" to the foundry's press releases.

    As ST would tell it, their 28nm FDSOI is the MOAN (mother of all nodes).

    And yet we don't see GloFo beating down the door with press releases vaunting their newly implemented "TSMC killer" technology.
     
  10. Ajay

    Ajay Platinum Member

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    Then it would appear, that ST-Micro's claim that if GF started the conversion in February, then GF would be able to start producing wafers sometime in 4Q13 is something that GF isn't comfortable with yet. Otherwise, I agree - GloFo would be screaming the benefits of FD-SOI from the rooftops. The proof of the pudding is in the eating!
     
  11. SocketF

    SocketF Senior member

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    Yes and furthermore there is a general trend that all the mobile devices' manufacturers are making their own SOC. Most prominent example: Apple.

    Thus pure SoC-makers like STE are not profitable. Even Texas Instruments canned their OMAP SoCs.

    So all in all it may and like a sad story. Best technology but maybe soon no chip. However, I hope that the STE SoC will be used at least in one mobile phone. There should be some L8540 designs around that should be easily upgradeable. (Haven't checked though).


    @Idontcare:
    I will try next time ^^
    It just didn't give much credit because it is nothing new to me, I follow FD-SOI since December and was anticipating the demo of the L8580. STM already stated during the SOI consortium meeting in the mid of December all the now proven facts about STE's SoC@FD-SOI.

    In case the PDFs were not linked previously, lots of up-to-date FD-SOI presentations below:
    http://www.soiconsortium.org/fully-depleted-soi/presentations/december-2012/

    I hope that was clear enough ;-)

    To the FD-SOI skeptics:
    I also doubt any information of a company about its own products but now we have proof with the L8580. Only thing that could still be fishy are yields. But a sincere FD-SOI customer should be able to get that information. Furthermore the promised (general) information is that FD-SOI yields are better due to less usage of dopants. Everything looks really tooooo good to be true. Just imagine what that could do to an APU. You could bias the CPU-part for high-clocks and the GPU-part for low-leakage. That's exactly the "holy-grail" of APU-manufacturing that AMD was looking for since the Llano disaster. And then that process will be even a bit cheaper ... ridiculous.

    I am searching for a catch since several weeks .. but it is really hard to find.
     
  12. SiliconWars

    SiliconWars Platinum Member

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    AMD need to stop chasing the holy grail and just actually do the (relatively) easy things right.

    Intel's process lead is overstated. As you mentioned earlier, yield and cost is the great equaliser. AMD has a history of making incredible improvements on the same process, far ahead of anything intel has ever done, because intel is basically in a hurry to abandon the current process and move to the next smaller one.

    FD-SOI should be an interesting talking point for AMD's top echelon's (at 20nm) but they simply don't have the money left to go chasing the holy grail any more.
     
  13. Idontcare

    Idontcare Elite Member

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    I like :)

    On the topic of the back bias, I thought that had to be applied to the entire IC, it is not possible to just apply it to select regions dynamically. Is this true?
     
  14. SocketF

    SocketF Senior member

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    They don't need to chase, FD-SOI *is* the holy grail and it is available @GF soon. It really sounds too good to be true.

    There won't be any 20nm FD-SOI node STM just canned it in last December (check the PDFs from my last link, there you can see the new roadmaps). I guess it has something to do with GF's decision to launch their 14XM process ( which uses the back-end of 20nm) just 1y after their 20nm bulk process. FD-SOI normally is also planned to be available some time after the bulk process, too, thus I assume that they decided to wait a few months more to be able to use the 14nm "XM"-node.

    I am no expert in this field but I don't see any difference to the current situation of having different voltage planes for the GPU/CPU/Uncore parts. These voltages are the transistor's gate voltages. If it is possible to have several voltage planes for the gate voltage, why should it be impossible to have several planes for the bias-voltage, too?

    However I did not find proof, only something for a special type of transistors from SuVolta:
    http://www.suvolta.com/index.php/download_file/view/40/77/

    Sounds like what we want, but I am not 100% sure if that is also valid for the back bias in FD-SOI transistors.
     
  15. ShintaiDK

    ShintaiDK Lifer

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    It was pretty obvious it would happen, even tho we already had alot of people cheering for big.LITTLE already. Also shows ARMs position as a core designer.

    I wonder if Qualcomm will follow suit, leaving Samsung and ARM alone on the big.LITTLE :biggrin:
     
  16. simboss

    simboss Member

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    I do not really see why you could not combine the 2 technologies to work together.
    It would give you an even better dynamic range of performance or power efficiency. Obviously it would increase the system complexity to handle the different possible combinations, but once you have a big.LITTLE working, it should not be that hard.
     
  17. NTMBK

    NTMBK Diamond Member

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    Wow, 28 FD-SOI sounds seriously tasty. I very much hope that GloFo will get it as quickly as they say- Jaguar ported onto that could be very nice.
     
  18. ShintaiDK

    ShintaiDK Lifer

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    Well...first product seems to be out in 2014 if it enters the fab in Q4 2013. Plus I bet this is LP only. I am quite sure Jaguar will use a HP process.

    But lets see in a year what comes out.
     
    #93 ShintaiDK, Jan 29, 2013
    Last edited: Jan 29, 2013
  19. Idontcare

    Idontcare Elite Member

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    We used body-biasing at TI as well, the difference between back-bias and what you are thinking of in terms of power-planes is that the back-bias applied to the substrate cannot be electrically isolated and partitioned...it applies to the entire substrate (die) all at once.

    The power planes on the active side of the die can be partitioned and electrically isolated as a matter of straightforward patterning and isolation techniques when forming the transistors themselves. No such processing occurs on the backside of the die.

    Back biasing is basically turning the entire substrate into a controlled capacitor (like a MIMCAP). To have regions of the substrate biased at one voltage, and other regions biased at another voltage, would require electrical isolation between those regions. That is no feasible with today's process technology.

    It would be possible if the substrates were MCM'ed. One die for the cores and one die for the iGPU, then each die could be independentally biased with a different back-bias voltage because the two die would be electrically isolated from each other.

    That is what I understand of the technology. But maybe ST has figured out a way around this as well?

    It isn't that they can't be combined, it is that combining them would be superfluous at that point.

    big.Little elevates production cost because it makes the die larger than it otherwise would be. If your process tech allows the power to scale over a wider range then your reward for that more robust process tech window is the ability to have smaller and less complicated die. Validation improves, yields improve, die per wafer improves, production costs go down.

    You could take a step back from that and still do big.LITTLE, but ideally you'd like to not have to.
     
  20. SocketF

    SocketF Senior member

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    Yes it is based on the 28nm LP-libraries from the IBM/GF consortium, but with FD-SOI that LP process nearly scales as high as the HP version - just with much less leakage.

    Don't forget that the demoed STE SoC can clock up to 2.5/2.8 Ghz. That is just a Cortex-A9, i.e. it just has a 8 stage pipeline. Jaguar with 14 stages should be easily able to run at much higher clocks.

    More on the LP-HP-FD-SOI differences here:

    http://blog.stericsson.com/blog/201...st-ericssons-next-generation-novathor-part-1/

    http://blog.stericsson.com/blog/201...ricssons-next-generation-novathor-–-part-2-2/

    Edit:
    @Idontcare:
    Ah ok, then if it is really the whole substrate then it wont work :( No clue if they have found a way around it, I doubt it, and 2 dies would be "stupid", too, we had that previously e.g. intel did it, and the interconnect between those dies will be a bottleneck. The only other thing they promoted was the integration of FD-SOI and bulk transistors on the same die. In that case you just remove that "precious" thin SOI layer and work on it like on a normal bulk die. But then I guess the back-bias wont improve either.

    OK then finally at least one feature that is really toooo good to be true ^^
     
    #95 SocketF, Jan 29, 2013
    Last edited: Jan 29, 2013
  21. simboss

    simboss Member

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    Combining the 2 technologies would still give you a larger range of performance/power efficiency, wouldn't it?
    An A7 running at 0.65V would still consume much less than an A15, right? The question here is obviously how much less? And is the difference worth the effort.
    and the A15 should be able to clock higher, so you are gaining on the high performance as well.


    Given the fact that the bL chips are already here and that the port to FD-SOI is (supposed to be?) straightforward, the added complexity does not seem like a non-starter.

    Yes it would cost more, as it would cost more to move to a more advanced node, or to design a new core.
     
  22. piesquared

    piesquared Golden Member

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    #97 piesquared, Jan 29, 2013
    Last edited: Jan 29, 2013
  23. SocketF

    SocketF Senior member

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    Probably not. You forgot that STE uses the A9. Smaller than the A15, also less IPC, but you can compensate by a higher clock for the A9@FD-SOI part.
    Compared to the A7 it is a much better performer due to In-Order <> OoOrder-Execution.
    Surely an A15@FD-SOI would again have a higher performance but I don't think that it is worth it to have 2 additional A7 on the die. It justs complicates the whole design. Two A9s are the golden middle. Easy design, low die size, high clocks and low clocks, cheap price, perfect.

    A big+Little chip might be slightly better, but I don't want to pay the extra price for the bigger die.

    However, I can see the market for it in expensive "bling bling phones" ^^
    Some people might pay lots of $ for it.

    Interesting but you are in the wrong thread. There is no direct connection to FD-SOI. If there is no other HSA-Thread feel free to open one, it is an important topic.
     
  24. piesquared

    piesquared Golden Member

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    It's related to ST. No harm no foul.
     
  25. Ajay

    Ajay Platinum Member

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