EETimes: ST plans for Dresden FDSOI production

[Idontcare]

Saw this at EETimes:

ST plans for Dresden FDSOI production

ST claims that at 28-nm, its FDSOI process can provide 30 percent more performance than bulk 28-nm CMOS at the same power consumption, or, alternatively, can provide as much as a 50 percent saving in dynamic power consumption at the same performance. This is because FDSOI allows the use of voltages down to 0.6-V whereas bulk CMOS only goes down to about 0.9-V, said Joel Hartmann, executive vice president of front-end manufacturing and process R&D, for the digital sector at ST.

Source

I really enjoyed the embedded video at the end of the article, direct link here, as it did a great job highlighting some basic xtor functions that are of interest to people.

Even if you don't care about FD-SOI, watching the video can be educational.

If the numbers are true and not just hype, and the ease-of-porting existing 28nm bulk designs to 28nm FD-SOI is true, then AMD could really see a boost in their 28nm products by migrating to FD-SOI at GloFo

 

[Homeles]

I thought AMD wanted nothing to do with SOI on 28nm?

 

[SiliconWars]

Enjoyed that one, cheers. This is ST Micros, the memory guys I take it?

 

[inf64]

I thought AMD wanted nothing to do with SOI on 28nm?

That's because GloFo didn't want anything to do with it either. Maybe things change in the future.

 

[grimpr]

Fingers crossed that we will see Steamroller on AM3+ and this node.

 

[Greenlepricon]

Very cool find! I'm hoping that we'll see how effective this really is soon enough, especially if chips are already being developed with this method.

 

[zebrax2]

Nice video! I really hope this could help AMD reduce the amount of power their processor consume

 

[cbn]

I really enjoyed the embedded video at the end of the article, direct link here, as it did a great job highlighting some basic xtor functions that are of interest to people.

Even if you don't care about FD-SOI, watching the video can be educational.

Great video. Thank you for posting that.

P.S. The part at 5:26 I thought was particularly interesting. After describing the top gate and the buried gate the video goes on to say at 5:58..."a processing core built up with such transistors can operate as if it were , in fact, two cores. One optimized for high performance and the other for low power."

 

[Greenlepricon]

Great video. Thank you for posting that.

P.S. The part at 5:26 I thought was particularly interesting. After describing the top gate and the buried gate the video goes on to say at 5:58..."a processing core built up with such transistors can operate as if it were , in fact, two cores. One optimized for high performance and the other for low power."

I thought that was interesting as well. It might not help the cpu if it is under load, but the idle to low usage power might be amazing. I'm still not expecting any miracles on the max TDP, but at least it can compensate for that the majority of the time (for most people).

 

[dma0991]

Very interesting video indeed. I'd wish Intel is good at making videos like these as good as they make chips. The ones I've seen from Intel are quite dull without commentary.

 

[Idontcare]

I thought AMD wanted nothing to do with SOI on 28nm?

I don't recall AMD ever saying anything official regarding their position on SOI, for or against, below 32nm.

They just basically said 28nm would be bulk-Si but never really addressed the question of whether or not this was a good thing, or a bad thing...nor any idea whether it was their idea or GloFo's idea.

The supposition here is that ST Micro is not embellishing the capabilities or ease of porting designs to take advantage of FD-SOI at 28nm. Provided ST Micro is being truthful then I see no reason why AMD wouldn't want to take advantage of this technology as soon as GloFo can get it online and ramped in capacity.

Enjoyed that one, cheers. This is ST Micros, the memory guys I take it?

ST Micro is kinda like the European version of TI (Texas Instruments). Like TI, ST Micro pretty much has a finger in every pot when it comes to various semiconductor segments.

Fingers crossed that we will see Steamroller on AM3+ and this node.

The reported timeline for getting 28nm FD-SOI into production makes the scheduling rather tight:

Hartmann said Fab 1 in Dresden, Germany, would be a logical place for Globalfoundries' to host FDSOI as it is already the where the foundry manufactures 32/28-nm bulk CMOS. "If we start this month or in February Globalfoundries could be in production in the fourth quarter of 2013," said Hartmann.

Can AMD really intercept their existing 28nm bulk-Si design schedules in time to port them over to the FD-SOI process and bring them to market within the year? Questionable.

 

[Homeles]

Perhaps AMD could have a leg up before the announcement.

 

[SiliconWars]

I don't think AMD will be having anything to do with this tbh.

 

[Homeles]

I don't think AMD will be having anything to do with this tbh.

I think they'd be insane not to, assuming the technology delivers as promised and it was made very clear that the manufacturing kinks had been worked out.

 

[mrmt]

I don't recall AMD ever saying anything official regarding their position on SOI, for or against, below 32nm.

They just basically said 28nm would be bulk-Si but never really addressed the question of whether or not this was a good thing, or a bad thing...nor any idea whether it was their idea or GloFo's idea.

If you have the guts to listen to Rory Read for more than 3 minutes, you can listen to his speech at CreSui tech conference. There he states that it it is his goal to make AMD use only 2 manufacturing processes, from the 9 they are using currently. And he mention cost as a cardinal factor behind this drive. This factor alone would hind the SOI prospects for AMD.

 

[guskline]

IDC: Thank you. I spent the time watching the embedded video and I found for someone like me with very limited background in transitors and cpus it was a great explanation of the process developed by ST.

Why wouldn't AMD jump at the chance to use this process or is it too expensive?

 

[Idontcare]

If you have the guts to listen to Rory Read for more than 3 minutes, you can listen to his speech at CreSui tech conference. There he states that it it is his goal to make AMD use only 2 manufacturing processes, from the 9 they are using currently. And he mention cost as a cardinal factor behind this drive. This factor alone would hind the SOI prospects for AMD.

Going with the premise that ST Micro is not over-selling the capabilities of their FD-SOI process tech, AMD would benefit by migrating their 28nm designs to FD-SOI:

Hartmann acknowledged that the raw wafer cost for a silicon-on-insulator wafer is about two to three times that of a standard silicon wafer. But the FDSOI manufacturing process is simpler, he said, which saves cost and improves yield. "FD-SOI process cost is 10 to 12 percent cheaper than bulk. This will allow us to fully compensate extra cost of SOI substrate when in high-volume manufacturing," said Hartmann.

ST Micro gains nothing by misleading the public on the advantages of their FD-SOI process. If the cost savings are imagined and not real then every potential customer of the process would know immediately and the entire affair would be a non-starter.

So I am inclined to believe the purported claims and take them at face value.

But the specs alone don't ensure AMD will use the node for simple fact that the timing is rather off. Usually a design team needs a good 2-3 years beforehand to design and optimize an IC for the specific electrical parametrics of a given node.

If ST Micro is only just now making its 28nm FD-SOI node available to IC designers then it starts that 2-3 yrs clock ticking now...unless the 28nm bulk-Si -> 28 FD-SOI porting process really is as straightforward easy as they claim it to be.

 

[mrmt]

Going with the premise that ST Micro is not over-selling the capabilities of their FD-SOI process tech, AMD would benefit by migrating their 28nm designs to FD-SOI:

ST Micro gains nothing by misleading the public on the advantages of their FD-SOI process. If the cost savings are imagined and not real then every potential customer of the process would know immediately and the entire affair would be a non-starter.

I tend to take that kind of announcements with a huge pile of salt, not only because they don't really say anything about their baseline scenario, every bleeding edge high volume foundry out there that examined SOI didn't adopt the technology.

Also Soitec wasn't really upbeat about SOI prospects in their last financial statements, quite the opposite, they used an unusual blunt language to describe SOI prospects.

In any case, I think this process is a non-starter. By Q413 TSMC will already preparing their 20nm process, so will Samsung. 28nm SOI will be relegated to second/third tier products..

 

[Khato]

So, who else finds it interesting that the performance claims of the ST FDSOI process pretty much exactly match what Intel said about their 22nm process not quite two years ago? Granted Intel said 37% more performance at same power consumption instead of 30%, but the 50% reduction in power at same performance is the same. Implies that in that regard at least there's not much difference between the finfet and FDSOI approached to achieve fully depleted transistors. Though glancing back over Intel's announcement I do wonder where the supposed 10% cost adder for FDSOI has gone - maybe the FDSOI wafer cost has fallen that much in the last ~2 years?

Other thing that I didn't really see mentioned anywhere - they start off talking about the problem of leakage power, but only mention that the FDSOI process reduces body leakage (so IGIDL and IREV) which especially at the current geometries are dwarfed by ISUB. So I'm guessing that their FDSOI will only make a very minor dent in leakage current?

 

[AtenRa]

I dont see AMD using 28nm FD-SOI, they already have 32nm PD-SOI.

And no way that SteamRoller will be 28nm.

 

[Idontcare]

I dont see AMD using 28nm FD-SOI, they already have 32nm PD-SOI.

And no way that SteamRoller will be 28nm.

20nm bulk-Si then?

 

[Homeles]

So, who else finds it interesting that the performance claims of the ST FDSOI process pretty much exactly match what Intel said about their 22nm process not quite two years ago? Granted Intel said 37% more performance at same power consumption instead of 30%, but the 50% reduction in power at same performance is the same. Implies that in that regard at least there's not much difference between the finfet and FDSOI approached to achieve fully depleted transistors. Though glancing back over Intel's announcement I do wonder where the supposed 10% cost adder for FDSOI has gone - maybe the FDSOI wafer cost has fallen that much in the last ~2 years?

Other thing that I didn't really see mentioned anywhere - they start off talking about the problem of leakage power, but only mention that the FDSOI process reduces body leakage (so IGIDL and IREV) which especially at the current geometries are dwarfed by ISUB. So I'm guessing that their FDSOI will only make a very minor dent in leakage current?

I thought that FDSOI and FinFETs weren't mutually exclusive?

 

[mrmt]

So, who else finds it interesting that the performance claims of the ST FDSOI process pretty much exactly match what Intel said about their 22nm process not quite two years ago? Granted Intel said 37% more performance at same power consumption instead of 30%, but the 50% reduction in power at same performance is the same.

Did intel claim a 30% reduction in voltage?

 

[inf64]

I dont see AMD using 28nm FD-SOI, they already have 32nm PD-SOI.

And no way that SteamRoller will be 28nm.

CES 2013 roadmap AMD revealed exactly stated: 28nm Kaveri based on SR core to arrive in Q4 2013.

 

[AtenRa]

CES 2013 roadmap AMD revealed exactly stated: 28nm Kaveri based on SR core to arrive in Q4 2013.

Yes i know they said Kaveri will be 28nm, i was talking about Server/Desktop (FX) SteamRoller.