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[DigiTimes] TSMC 10 nm trial production in 2015, mass production in 2016

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Every time the node shrinks, the delay between risk production and actual products gets expanded. Thats what TSMC historically have shown. So a better bet would be sometime in 2019.
 
In any case, this strongly suggests that TSMC is indeed going to be 4 years behind Intel. The delta between Intel and the second semiconductor company with Germanium products might be up to 6 years.
 
Yep. Technology wise TSMC is around 3½ years behind today.

This is also why btw that the time for risk production to actual products keep increasing:
14nm-Ramp-IBS.jpg


The prospects for TSMCs 20nm and below is also relatively megre. 28nm is expected to stay strong through 2020.
Wafer-volumes-Handel-Jones-2-4.jpg


And it also explains what we see, with big customers already annoucing that they have no interest in 20nm or below due to economic reasons.
 
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"The good news is TSMC believes it can offer the full advantages of a new process node with a 10nm FinFET process, including a doubling in the density of logic gates relative to the 16nm node. Designers could start early work in the 10nm process before the end of 2015, Sun said."

http://seekingalpha.com/article/196...semiconductor-have-very-different-definitions

Design work is not the same as risk production, is it?

The article says that TSMC will have 10 nm qualified by the end of 2015, meaning it is ready for the customers to design chips for it. It does not say that risk production is targeted for end of 2015. They have only said that risk production will commence sometime in 2015. TSMC can potentially produce 10 nm chips in risk production for testing before they are 100% certain of the design guidelines that their customers will have to abide by (i.e. indicating it is qualified).

Anyway, I guess it's a matter of definition of terms.
 
Risk production. Mass production earliest in 2016 (thread title).

Those are not the only types of production to chose from. Could be e.g. risk production in 2015Q1, early prototype production for customers in 2015Q4, and mass production in 2016.
 
While reading parts of TSMC's annual report, I didn't see any other kinds of production. It's the most likely assumption.
 
Those are not the only types of production to chose from. Could be e.g. risk production in 2015Q1, early prototype production for customers in 2015Q4, and mass production in 2016.

TSMCs roadmap says it all:
TSMC_ProcessRoadmap_689.jpg


And TSMC says, box left edge=Risk production, box right edge=No meaning(And with good reason since its floating.).
 
The prospects for TSMCs 20nm and below is also relatively megre. 28nm is expected to stay strong through 2020.
Wafer-volumes-Handel-Jones-2-4.jpg


And it also explains what we see, with big customers already annoucing that they have no interest in 20nm or below due to economic reasons.
A projected full fab utilisation for 5+ years equals a lot of low risk cash. And ~360k wafer starts per month on 28nm alone is close to what Intel produces in total. Just as a reminder, those numbers carry a lot more value than your analysis.

Further cost and size compares between TSMC and Intel for 2015 and 2016.

11952436783_0c5afdcd2d.jpg

11952446883_f8bea1abb6.jpg
Critical analysis of these slides: http://electroiq.com/blog/2014/01/intel-vs-tsmc-an-update/
It's a good read imho.
 
A projected full fab utilisation for 5+ years equals a lot of low risk cash. And ~360k wafer starts per month on 28nm alone is close to what Intel produces in total. Just as a reminder, those numbers carry a lot more value than your analysis.

Critical analysis of these slides: http://electroiq.com/blog/2014/01/intel-vs-tsmc-an-update/
It's a good read imho.
I have no doubt that the Jefferies estimate is overly optimistic, however the author makes a lot of errors in his analysis.

Firstly, he is assuming that 14nm and 22nm are more than marketing labels; they're not. Second, his math is incorrect. If the trend is 0.5x per generation, the math is very simple: 0.5 * 0.092 = 0.046. Intel, however, is claiming more than a 0.5x reduction, somewhere around 2.2x the size, or ~0.45x. This would correspond to a cell size of 0.042um2.

Additionally, the TRAMS project he cites has a different SRAM configuration that the one Intel used on its 22nm process, and it is therefore not comparable.

Overall... kind of clumsy work from a CEO.
 
While reading parts of TSMC's annual report, I didn't see any other kinds of production. It's the most likely assumption.

Yes, I agree, it's the best guess. But we don't know for sure. All we know for sure is that they've said trial production sometime in 2015.
 
Firstly, he is assuming that 14nm and 22nm are more than marketing labels; they're not. Second, his math is incorrect. If the trend is 0.5x per generation, the math is very simple: 0.5 * 0.092 = 0.046. Intel, however, is claiming more than a 0.5x reduction, somewhere around 2.2x the size, or ~0.45x. This would correspond to a cell size of 0.042um2.
That size difference between sram configurations would still be unusual, especially since...

Additionally, the TRAMS project he cites has a different SRAM configuration that the one Intel used on its 22nm process, and it is therefore not comparable.
...the same project also analyzed 6T-111 Srams, the (theoretically) smaller HDC Srams, and mentions:
- This solution removes one pull-down fin on each side.
- Area Update (June 2012): Due to dominating IM2 – via spacing rule, this has no effect on area.
 
They're Imec's cell layout and RDRs. And they manage ~0.024um2 on 10nm, so it's not like there's a fundamental issue. It would just come down to how much they're willing to pattern, although that would increase cost. They may also have less restrictive design rules for their own process, which may be why they ran into yield issues.
 
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Meanwhile, TSMC plans to set up a special R&D unit, which will be powered by 300-400 technicians, to develop 10nm processes, aiming to push the process into trial production in 2015 and mass production in 2016.
Are they riding exercise bikes connected to generators?

The authors got the gist of it correct but they got the node wrong.

The second-shift for R&D development was pulled together for accelerating 7nm, not for 10nm.

10nm is being handed off from development team to process xfr team at this time in preparation of production.
 
A projected full fab utilisation for 5+ years equals a lot of low risk cash. And ~360k wafer starts per month on 28nm alone is close to what Intel produces in total. Just as a reminder, those numbers carry a lot more value than your analysis.

Critical analysis of these slides: http://electroiq.com/blog/2014/01/intel-vs-tsmc-an-update/
It's a good read imho.


And why would Apple or Qualcomm ever use Intel? The ARM crowd is desperately trying to get away from the old days of the Intel monopoly and throwing more money at Intel at the expense of TSMC, Samsung, and GF is counter productive to the overall health of their own future.
 
And why would Apple or Qualcomm ever use Intel? The ARM crowd is desperately trying to get away from the old days of the Intel monopoly and throwing more money at Intel at the expense of TSMC, Samsung, and GF is counter productive to the overall health of their own future.

Using Intel as a foundry - assuming they would actually offer such a thing to Apple, let alone Qualcomm, which is a huge leap - isn't directly giving into their CPU monopoly. Apple and Qualcomm would want to use them because they have a better (faster, lower power, more dense) process than TSMC, GF, or Samsung. That much is indisputable. It's also only one parameter, so it'd have to balance favorably in terms of costs and customer relationship (and I don't think TSMC is blowing smoke when they say their far more comprehensive foundry experience vs Intel or Samsung actually makes a difference)

Even then, Apple, Qualcomm, and others may still have trepidation even if Intel is the best option. Perhaps out of fear of giving a competitor an SoC competitor information about their SoCs, or in fear that they're only extending the opportunity temporarily in order to damage TSMC, later leaving them with trailing edge processes (or nothing) while extending the advantage they have in manufacturing their own products.
 
The authors got the gist of it correct but they got the node wrong.

The second-shift for R&D development was pulled together for accelerating 7nm, not for 10nm.

10nm is being handed off from development team to process xfr team at this time in preparation of production.

So 20nm will show up in high volume in products during 2H 2014 (Apple), then 16 FinFET 2H 2015, then 16 FinFET+...also 2H 2015, then 10nm FinFET in 2H 2016?

That's a really, really rapid development cadence. What's the caveat here, IDC?
 
What's the caveat here, IDC?
It isn't really shrinks unless TSMC, GlobalFoundries, UMC, etc are adopting EUV + 450mm.

20-nm = 20-nm
16-nm / 14-nm = 20-nm FinFETs
10-nm = 14-nm FinFETs
7-nm = 10-nm FinFETs

It's really just tricks with the libraries being denser with the higher current drive of FinFETs.
 
And why would Apple or Qualcomm ever use Intel? The ARM crowd is desperately trying to get away from the old days of the Intel monopoly and throwing more money at Intel at the expense of TSMC, Samsung, and GF is counter productive to the overall health of their own future.

Source? That sounds ridiculous to me. OEMs just take the best SoC they can get for their money. If Intel asks too much, they'll go with Qualcomm. If they stay with ARM, soon they'll have to use tech that Intel's been shipping for many years, so they'll have no choice if they want to have a competitive SoC.

So to answer your question (I don't know why you mention Qualcomm), Apple will use Intel simply because they (will) have the best SoCs. Why would you use a 20nm SoC if there is 14nm, 10nm and 7nm?
 
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Source? That sounds ridiculous to me. OEMs just take the best SoC they can get for their money. If Intel asks too much, they'll go with Qualcomm. If they stay with ARM, soon they'll have to use tech that Intel's been shipping for many years, so they'll have no choice if they want to have a competitive SoC.

So to answer your question (I don't know why you mention Qualcomm), Apple will use Intel simply because they (will) have the best SoCs. Why would you use a 20nm SoC if there is 14nm, 10nm and 7nm?

It's more complicated than that. If Apple wanted to choose the best process, they wouldn't be using ARM and Samsung for the SoC solution. But they are and have been since they first approached Intel before the iPhone. Plus, they have this developed relationship, further tying the companies together.

Yields could influence a transition, and that pressure doesn't seem to be increasing. (Pricing could increase pressure, but I'm doubtful on that)

You say why have 20nm when you can have 14nm, 10nm, and 7nm. But, that's not a fair time-frame to compare. It's why 20nm planar vs. Intel 14nm-Broadwell; or 16FF/+ vs. 14nm-Skylake / 10nm-Cannonlake or 10FF TSMC vs. 10nm-Icelake...

it isn't fair to reference 20nm TSMC to 10nm/7nm because the time-frame is too long.
 
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I still consider TSMC's 16nm node as 20nm (you gain performance and TTM, but lose out on cost). TSMC's 20nm process without and with FinFETs will face Intel's 14nm, 10nm and 7nm as competition.
 
Further cost and size compares between TSMC and Intel for 2015 and 2016.

https://markets.jpmorgan.com/research/email/-kjegkq4/GPS-1336259-0

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"We estimate that TSMC’s cost structure at 28nm 20nm is 30% lower than Intel. While Intel may narrow this somewhat at 14nm, we expect the cost gap to widen again at 10nm. "

TSMC 16FF+ matches Intel 14nm in performance and is marginally behind in transistor density. TSMC stated in Q1 2014 earnings call that the majority of 16 FINFET volume production in 2015 would be at TSMC 16FF+.
 
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