[DigiTimes] TSMC 10 nm trial production in 2015, mass production in 2016

[Exophase]

Cancel it? I have at no time said that. The 20nm with FF aka what they call 16nm is what majority of their customers want. (Read low power.)

Sorry, I somehow totally misread your sentence here. I'll have to look for what you said in the other thread, but since you clearly don't think that it was probably a misunderstanding there as well.

Look at my post above. TSMC is doing some 'magic tricks' to make their ever growing gap with Intel look better. Node names are not more than marketing names. Instead of naming their node like traditionally, where it indicates a new step of Moore's Law, TSMC decided it was okay to take a new node for just releasing a new transistor technology without any increases in density, which is exactly what they will do at 16nm. So now we will get the better transistor sooner than before (half a year), but we'll have to wait 2 years after FinFETs for a new node with improved density. In the meantime, TSMC will release a 'FinFET Plus' with 15% scaling.

So 2 years after 2016 is 2018. TSMC, however, says they will qualify 10nm EOY 2015 (+ new nodes are generally a few months later than 24 months), so that makes it reasonable to think that it will be H1'19 before we'll see TSMC's competitor of Intel's 14nm in products.

What does any of this have to do with what you quoted? All I said is that 10nm products coming out of Intel in mid-2016 would mean a node to node launch schedule that's a lot shorter than the past few node transitions have been. So I think your estimation is too optimistic and I gave my estimation that's ahead of it by ~6 months. Nothing TSMC says or does is relevant to this.

Except then that TSMC's comments have been proven to be not factual (it looks more like a 1.65x improvement).

You can't really prove anything TSMC said about their upcoming 10nm node to be non-factual until you have a 10nm product to look at. Intel, in their slides, assumed that the shrink from TSMC 16nm to 10nm will be a typical node to node density improvement. TSMC says it'll be greater than that (they show a steeper slope line in their graph). I'm going with TSMC's claims until something tangible contradicts it.

 

[witeken]

What does any of this have to do with what you quoted? All I said is that 10nm products coming out of Intel in mid-2016 would mean a node to node launch schedule that's a lot shorter than the past few node transitions have been. So I think your estimation is too optimistic and I gave my estimation that's ahead of it by ~6 months. Nothing TSMC says or does is relevant to this.

Intel puts 10nm production in 2015 (and 7nm in 2017), or 2 years after when 14nm was originally intended to start production. I'm assume that Intel won't delay 10nm because of 14nm, but I think it won't be more than 24 months.

You can't really prove anything TSMC said about their upcoming 10nm node to be non-factual until you have a 10nm product to look at. Intel, in their slides, assumed that the shrink from TSMC 16nm to 10nm will be a typical node to node density improvement. TSMC says it'll be greater than that (they show a steeper slope line in their graph). I'm going with TSMC's claims until something tangible contradicts it.

Did you read my link? I think it proved enough, certainly when TSMC's reply confirms it.

 

[Homeles]

You can't really prove anything TSMC said about their upcoming 10nm node to be non-factual until you have a 10nm product to look at. Intel, in their slides, assumed that the shrink from TSMC 16nm to 10nm will be a typical node to node density improvement. TSMC says it'll be greater than that (they show a steeper slope line in their graph). I'm going with TSMC's claims until something tangible contradicts it.

They'll need a lot more than >2x density going from 16nm to 10nm to catch up with Intel. Intel's doing roughly 2.2x at both 14nm and 10nm, although perhaps slightly less aggressive at 10nm.

I don't doubt that TSMC will have an aggressive 10nm node as well, but they've either seem to have goofed on how they'll stand up against Intel, or they're shooting for something like a 3x improvement.

 

[raghu78]

Sure, but how are the yields? Source? Today I read a recent article predicting Samsung is the supplier of the A8.
That isn't really steep. In fact, most of TSMC's revenue comes from old nodes.

Yields are a challenge for anyone at the bleeding edge. You seem to be oblivious of the fact that Intel delayed the 14nm ramp from Q4 2013 to Q1 2014 due to yield problems. Do you have factual knowledge of Intel's and TSMC's yields. If you don't lets not argue about it.

The world doesn't only consist of Apple. The rest of the world, ~85% or so, will have 20nm only in H1 2015 with the SGS6 etc.

Thats the problem with leading edge capacity. Samsung is getting very aggressive with 14nm FINFET and it looks like they could have a 3 - 6 month lead over TSMC 16FF+ .

https://www.semiwiki.com/forum/content/3546-tsmc-vs-intel-vs-samsung-finfets.html

Fabless companies want TSMC/Samsung/GF to provide massive capacity at leading edge nodes to better compete against Intel.

Not true. Intel's lead is bigger than ever. Intel has 22nm products widely available since mid-2012. 20nm? H1'15. FinFETs? H1'16 or later, 3 years after Intel.

Intel 22nm FINFET density is comparable to TSMC/Samsung/GF 28nm. All of these nodes used single pattern immersion litho. Transistor Performance was much superior with Intel due to FINFET.

TSMC 16FF+ and Samsung 14 FINFET compete with Intel's 14nm FINFET in performance and density. All three have a 64nm Ml 1 gate pitch and use dual pattern immersion litho. There is no significant advantage that Intel has. Intel does have a time-to-market lead of 1 year.

http://www.bnppresearch.com/ResearchFiles/31175/Semiconductors-230414.pdf

Intel is in a unique position. Intel with its ever growing manufacturing leadership will take away all cutting edge revenue by gaining massive market share in all important areas of computing + shrinking the gap between IGPs and dGPUs. While Intel's income will grow, TSMC, Samsung and GlobalFoundries will each fight for the remaining dies. The leading edge market will further consolidate as necessary.

Thats your belief while the fact is the reverse is happening. TSMC and Samsung are reducing the process gap and getting more aggressive at future nodes. The foundries will continue to grow at Intel's expense. The foundries will enable Intel competitors like Apple, Qualcomm, AMD, Nvidia to compete and gain market share in the respective businesses that they compete. The war is between the entire semiconductor tech industry and Intel and make no mistake Intel will not win.

Intel puts 10nm production in 2015 (and 7nm in 2017), or 2 years after when 14nm was originally intended to start production. I'm assume that Intel won't delay 10nm because of 14nm, but I think it won't be more than 24 months.

Intel will have a gap of roughly 30 months from the time ivybridge was first available (Apr 2012) and broadwell is first available (Oct 2014). Future nodes are not getting easier. So the first 10nm products should be available in Q2 - Q3 2017. 7nm products won't be available till late 2019 or early 2020.

 

[Khato]

That article says that the EUV unit fried. The implications are the opposite of the way you took it. A $150 million dollar machine went "kablooey."

You see, with EUV, you want to create an ultraviolet laser by vaporizing droplets of tin with a CO2 laser. You're not supposed to vaporize the equipment. :awe:

Quite correct - the bit about TSMC intending to use EUV on their '10nm' node is in the fifth paragraph of the article though. And as you can likely guess, yes, my choice of articles to convey that intention was quite intentional If they can't even get the equipment that they're intending to use for their '10nm' to not self destruct why precisely should I believe their claim that they're going to have trial production in less than a year and a half?

 

[Homeles]

Intel 22nm FINFET density is comparable to TSMC/Samsung/GF 28nm. All of these nodes used single pattern immersion litho. Transistor Performance was much superior with Intel due to FINFET.

Intel's 22nm density advantage over TSMC/Samsung isn't insignificant -- it's about 25%, comparing their highest densities.

TSMC 16FF+ and Samsung 14 FINFET compete with Intel's 14nm FINFET in performance and density.

Not even close, probably in either metric. Performance has always been something Intel's had over their competitors, and by a significant margin. They've even tended to outperform IBM's SOI processes. You also need to consider that Intel's already will have had 2 and a half years of experience with FinFETs when their 14nm process debuts, while their competitors will have none (comparing product availability dates). Suffice to say, there's not a snowball's chance in hell.

TSMC's claiming a 0.081um2 cell size for 20nm. 16/14nm isn't far off. I think I've heard it's at most 15% denser than 20nm.

Intel's claiming a ~2.2x density increase for their 14nm. They're at 0.092um2 right now, which pins them at ~0.042um2.

 

[Exophase]

Intel puts 10nm production in 2015 (and 7nm in 2017), or 2 years after when 14nm was originally intended to start production. I'm assume that Intel won't delay 10nm because of 14nm, but I think it won't be more than 24 months.

So we're clear, when you talk about Intel launching a product you mean that product is on the shelves, right?

I remember when Ivy Bridge slipped a few months, putting its release around 28 months after Clarkdale. And if you go back to 45nm, the delta between Penryn and Clarkdale was about 26 months.

After IB came out people were saying the same thing you're saying now, that Broadwell will release 24 months after when IB was supposed to come out, putting the actual delta at around 20 months. Instead it's looking more like it'll be out September at the earliest, December at the latest, putting the delta around 28-31 months after when IB did come out. Which is a very different result. So your estimations of 24 months after when Broadwell "should" have come out (I assume about now) look very optimistic and goes against the trend of Intel's product launches at new nodes growing in distance instead of shrinking.

Did you read my link? I think it proved enough, certainly when TSMC's reply confirms it.

Yes, I read it, and I think it does a poor job refuting the claims TSMC made that their 16nm to 10nm will have a higher density improvement than Intel said. Regardless of how either graphs look, TSMC made it clear that they intend to pick up some of the slack in density at 10nm due to not improving the BEOL at 16nm. Which seems plausible given that they'll have had more time than usual between BEOL improvements.

 

[raghu78]

Intel's 22nm density advantage over TSMC/Samsung isn't insignificant -- it's about 25%, comparing their highest densities.

Do you have numbers to back it up ? Baytrail had no significant die size advantage over Apple A7 (Samsung) and AMD Kabini/Temash (TSMC) and Beema/Mullins (GF). All these chips are roughly a billion transistors. The problem is Intel's actual products are not showing the density advantages.

Not even close, probably in either metric. Performance has always been something Intel's had over their competitors, and by a significant margin. They've even tended to outperform IBM's SOI processes. You also need to consider that Intel's already will have had 2 and a half years of experience with FinFETs when their 14nm process debuts, while their competitors will have none (comparing product availability dates). Suffice to say, there's not a snowball's chance in hell.

TSMC's claiming a 0.081um2 cell size for 20nm. 16/14nm isn't far off. I think I've heard it's at most 15% denser than 20nm.

Intel's claiming a ~2.2x density increase for their 14nm. They're at 0.092um2 right now, which pins them at ~0.042um2.

TSMC is on record saying TSMC 16FF+ matches Intel 14nm in performance while being slightly behind in density (10 - 15%).

http://www.tsmc.com/uploadfile/ir/quarterly/2014/1aT1b/E/TSMC 1Q14 transcript.pdf

"Our 16 FinFET plus matches the highest performance among all available 16-nanometer and 14-nanometer technologies in the market today.Compared to our own 20 SoC, 16 FinFET plus offers 40% speed improvement. The design rules of 16 FinFET and 16 FinFET plus are the same; IPs are compatible"

http://electronics360.globalspec.com/article/3974/tsmc-tweaks-16nm-finfet-to-match-intel

Liu said that the 16nm FinFET Plus would match the performance of Intel's 16nm FinFET process. "So from our intelligence, our 16-FinFET plus technology with 15 percent improvement on top of 16-FinFET is about the same as Intel's transistors," he said.

http://investordiscussionboard.com/sites/default/files/post-attachments/113857/apple-tmsc.pdf

"Scaling gap to continue narrowing. TSMC’s newly announced “16nm FF Plus” is expected to be only 10 - 15% behind Intel’s 14nm (on area scaling) - so performance gains at Intel are not significant any more while TSMC may score well on time-to-market. TSMC expects scaling gap to narrow further on 10nm, while timing wise TSMC’s 10nm may only be 3 - 6 month behind Intel’s 10nm, in our view."


TSMC is a year behind at 16 FINFET wrt Intel and reducing the gap to 6 months at 10nm. Samsung is aggressively pursuing 14 FINFET and might be 3 - 6 months ahead of TSMC.

You are skeptical about TSMC's chances while I am not. In fact almost every analyst points out Intel's chances at being a foundry are very difficult as it does not have the process versatility and tools ecosystem to compete against TSMC.

 

[CHADBOGA]

In fact almost every analyst points out Intel's chances at being a foundry are very difficult as it does not have the process versatility and tools ecosystem to compete against TSMC.

The issue of Intel being a successful foundry is a completely different one to whether TSMC will close the gap to Intel's process lead.

It is not helpful to meaningful discussion to conflate the two things.

 

[jdubs03]

@raghu

You're over-estimating the amount of progress TSMC can make against Intel in terms of releasing qualified chips.

The amount of time between Intel's 22nm (and FinFET) release compared to TSMC's 20nm planar will be about 2 years (Apple) to 2.5 years (everyone else).
Intel obviously got delayed for 14nm, but keep in mind they showed 14nm a year ahead of shipping devices Q4 2014. They could surprise and show Cannonlake earlier in the process.

You argued the quotes for TSMC's in regards to 16FF+ in performance (same), but 16FF+ will ship after 16FF (safe guess: 6-12 months). So at least a 1.5-2 year gap to Intel 14nm (using your 1 year baseline). By the time 16FF+ is shipping, Intel's 10nm is not far off. (Q4-2016/Q1-2017 likely, not Q2-Q3 2017).

For 10nm: your argument is that TSMC can easily catch up, but Intel has about a two year lead on 10nm design qualification; along with a functional test chip (according to Ashraf's comb through TSMC's most recent CC, and Intel's IDF). It is unrealistic to think TSMC who is just beginning to set up a R&D team can cut the gap to release by 75%. What's to say Intel's yields won't surprise to the upside and increase the gap? I think the gap is essentially the same for each node transition down to 10nm: 1.75 years with a chance of +/-a quarter. Each subsequent node may follow the same pattern.

 

[Lepton87]

I don't know if the process gap narrowed or got bigger as of late but as the cost of each node shrink increases rapidly the process gap is bound to narrow eventually.

 

[Homeles]

Do you have numbers to back it up ? Baytrail had no significant die size advantage over Apple A7 (Samsung) and AMD Kabini/Temash (TSMC) and Beema/Mullins (GF). All these chips are roughly a billion transistors. The problem is Intel's actual products are not showing the density advantages.

For TSMC:

http://www.realworldtech.com/includes/images/articles/iedm10-10.png

Intel:

http://www.intel.com/content/dam/ww...ilicon-technology-leadership-presentation.pdf (PDF)

 

[raghu78]

@raghu
You're over-estimating the amount of progress TSMC can make against Intel in terms of releasing qualified chips.

Or maybe you are underestimating them. TSMC's 20nm SOC was yielding at 50% in Q1 and given the nature of the yield ramp curve its not difficult to see them at 75 - 80% yields in Q3. The TSMC 20nm ramp is quite steep from Q3 2014 onwards.

http://investordiscussionboard.com/sites/default/files/post-attachments/113857/apple-tmsc.pdf

page 3

"20nm yields for Apple SOC are already hitting 50%, much better than where 28nm was at the similar time of ramp. Wafer out should hit 6 - 7k in May and reach 25 - 27k by July/August. SoC yield is typically more difficult to stabilize than Graphics or FPGA so this is indeed a strong result."

The amount of time between Intel's 22nm (and FinFET) release compared to TSMC's 20nm planar will be about 2 years (Apple) to 2.5 years (everyone else). Intel obviously got delayed for 14nm, but keep in mind they showed 14nm a year ahead of shipping devices Q4 2014. They could surprise and show Cannonlake earlier in the process.

Intel's 22nm FINFET cannot be compared with TSMC 20nm planar. Intel 22nm FINFET uses single pattern immersion litho and has no significant density advantage over foundries 28nm planar.

TSMC 20nm planar uses double pattern immersion litho and provides a 1.9x density increase over TSMC 28nm. TSMC 16FF+ adds another 15 - 20% density increase over TSMC 20nm.

You argued the quotes for TSMC's in regards to 16FF+ in performance (same), but 16FF+ will ship after 16FF (safe guess: 6-12 months). So at least a 1.5-2 year gap to Intel 14nm (using your 1 year baseline). By the time 16FF+ is shipping, Intel's 10nm is not far off.

the actual gap is 3 - 6 months behind TSMC 16FF with the vast majority of volume production at TSMC 16FF+

http://www.tsmc.com/uploadfile/ir/quarterly/2014/1aT1b/E/TSMC 1Q14 transcript.pdf

page 4

"Our 16 FinFET plus matches the highest performance among all available 16-nanometer and 14-nanometer technologies in the market today.Compared to our own 20 SoC, 16 FinFET plus offers 40% speed improvement. The design rules of 16 FinFET and 16 FinFET plus are the same; IPs are compatible."


page 7

Randy Abrams - Credit Suisse - Analyst
I could ask a follow-up on the 16. Could you talk about the timing for the 16 regular version versus the plus version, if there is a difference on timing and also the customer adoptions? Then could you also talk about your expectation at this early stage on market share for the 16 node?

Elizabeth Sun - Taiwan Semiconductor Manufacturing Company Ltd - Director, Corporate Communications
So Randy, your question is with respect to the timing, the availability of the 16 FinFET versus the 16 FinFET plus. And then the way the customer adopts, whether they're more adopting 16 FinFET or the 16 FinFET plus?

Mark Liu - Taiwan Semiconductor Manufacturing Company Ltd - President & Co-CEO
Okay. 16 FinFET plus will be qualified in September. But remember, we and our customer work on 16 FinFET design one and a half years before. So all the customer already design -- the design is on 16 FinFET, okay. So the customer -- for those customers when the product tape out -- for example, we have a first product tapeout this month, it will ride on 16 FinFET process. And for those customers taped out in the second half, mostly, I would say mostly, will be riding on the 16 FinFET plus. So I would think majority of our process customers will run on 16 FinFET plus. And looking into the volume for the next year, I would say that most of the product will be run on 16 FinFET plus. Okay, thank you."

https://markets.jpmorgan.com/research/email/-kjegkq4/GPS-1336259-0

page 3

"16nm designs getting good traction; more interest in 16nm FinFET Plus TSMC’s 16nm FinFET process is getting good traction, with multiple customers likely to tape out in 1H14. Our understanding is that the first silicon shuttle has already been completed successfully in Nov 2013, with good performance. We believe that Xilinx is likely to be the first customer to tape-out 16nm FF and should start wafer-in by late 4Q14, slightly ahead of schedule.

TSMC’s newly announced 16nm FinFET Plus process, which delivers 15% more performance than 16nm FF, is also seeing strong demand from mobile Fabless customers, given the further reduction in die size and increase in transistor performance. We believe that some of the mobile customers could migrate directly down to 16nm FinFET Plus from 20nm, given the additional die shrink makes it an attractive proposition. Contrary to bear- camp observations, however, we believe that there would only be a maximum of two quarter time gap between the 16nm FinFET and 16nm FinFET Plus versions."

For 10nm: your argument is that TSMC can easily catch up, but Intel has about a two year lead on 10nm design qualification; along with a functional test chip (according to Ashraf's comb through TSMC's most recent CC, and Intel's IDF). It is unrealistic to think TSMC who is just beginning to set up a R&D team can cut the gap to release by 75%. What's to say Intel's yields won't surprise to the upside and increase the gap? I think the gap is essentially the same for each node transition down to 10nm: 1.75 years with a chance of +/-a quarter. Each subsequent node may follow the same pattern.

How did you come to the conclusion that TSMC is just now starting on 10nm R&D ? TSMC have stated that 10nm risk production starts in late 2015 which puts it 2 years behind TSMC 16 FINFET which went into risk production in late 2013. This means 10 nm volume production is slated for late 2016 or early 2017. A bleeding edge FINFET process today takes 4 -5 years to develop. So TSMC is well underway with 10nm R&D.

http://www.tsmc.com/uploadfile/ir/quarterly/2014/1aT1b/E/TSMC 1Q14 transcript.pdf

page 4

"For 10 FinFET, 10 FinFET offer TSMC's third generation FinFET transistor, designed to meet the power and the performance requirement of mobile computing devices. 10 FinFET will offer greater than 25% speed improvement, the same total power, compared to 16 FinFET plus. More importantly, 10 FinFET offer greater than 45% total power reduction at the same speed, compared to 16 FinFET plus.10 FinFET will offer 2.2X of density improvement over its previous generation, 16 FinFET plus. So, currently, 10 FinFET development progress is well on track, but risk production will be in 4Q 2015."

You could choose not to believe TSMC while others could choose to believe. Finally the customer products will be the verification of the correctness of the process roadmap. Qualcomm is already shipping 20nm modems and will be available in Samsung Galaxy S5 LTE-A phones in July. When Apple A8 is launched in the iPhone 6s and iPad Air 2, it will be proof of TSMC's execution. Same for A9 at TSMC 16FF+. There is a strong likelihood that Apple multi sources Apple A9 from TSMC/Samsung.

 

[raghu78]

For TSMC:

http://www.realworldtech.com/includes/images/articles/iedm10-10.png

Intel:

http://www.intel.com/content/dam/ww...ilicon-technology-leadership-presentation.pdf (PDF)

Again there is nothing out there comparing actual TSMC 16FF+ and Intel 14nm. There are no papers presented at IEDM or ISSCC events yet. There are no actual product teardowns of Intel 14nm products from chipworks yet.

On the contrary Intel has not even revealed actual die sizes on Baytrail while Apple has quoted 102 mm for A7 and Kabini has been measured at 107 sq mm for Kabini/Temash. Beema/Mullins has not been measured.

http://www.anandtech.com/show/7355/chipworks-provides-first-apple-a7-die-shot

http://www.anandtech.com/show/6977/a-closer-look-at-the-kabini-die

http://www.anandtech.com/show/7314/intel-baytrail-preview-intel-atom-z3770-tested

"Intel isn’t disclosing die size or transistor counts, which is ironic (and disappointing) given that Apple just disclosed both (or at least relative magnitude of one) for its A7 SoC."

Intel would not be so secretive if they had a significant die size advantage. Looks like Intel's process capability and Intel's product design are two entirely different things. :thumbsup:

 

[AtenRa]

Cell sizes (edit : revised)

Intel Cell sizes


45nm = 0,346um2
32nm = 0,171um2 --> ~50% reduction or 2 times more dense
22nm = 0,092um2 --> ~46% reduction or ~1.86 times more dense


14nm = ~0,042um2* --> ~55% reduction or 2.2 times more dense
*14nm cell size was calculated using 2.2 times of density over 22nm communicated by Intel


TSMC Cell sizes

40nm = 0,242um2
28nm = 0,127um2 --> ~47,5% reduction or 1,9 times more dense
20nm = 0,081um2 --> ~36% reduction or 1,57 times more dense
16nmFF = ~0,069um2 --> 15% reduction over 20nm

 

[Arachnotronic]

Cell sizes

Intel Cell sizes


45nm = 0,346um2
32nm = 0,171um2 --> ~50% reduction or 2 times more dense
22nm = 0,092um2 --> ~54% reduction or ~2.2 times more dense


14nm = ~0,051* --> ~55% reduction or 2.2 times more dense
*14nm cell size was calculated using 2.2 times of density over 22nm communicated by Intel


TSMC Cell sizes

40nm = 0,242um2
28nm = 0,127um2 --> ~52,5% reduction or 2.1 times more dense
20nm = 0,081um2 --> ~63,8% reduction or 2.55 times more dense
16nmFF = ~0,069um2 --> 15% reduction over 20nm

You did the math correct for TSMC 16 FinFET (TSMC reported 0.07um^2), though your Intel number seems off.

A 2.2x reduction is 1/(2.2) meaning that you MULTIPLY by 0.455 not 0.55, leading you to a 14nm SRAM cell size for Intel of ~0.042um^2. If this is actually true, then this is denser than the 10nm SRAM cell size that Samsung/GloFo/etc. reported for their 10nm node at the recent VLSI conference (0.052um^2).

I eagerly await proper process disclosures from Intel.

 

[Homeles]

Again there is nothing out there comparing actual TSMC 16FF+ and Intel 14nm. There are no papers presented at IEDM or ISSCC events yet. There are no actual product teardowns of Intel 14nm products from chipworks yet.

On the contrary Intel has not even revealed actual die sizes on Baytrail while Apple has quoted 102 mm for A7 and Kabini has been measured at 107 sq mm for Kabini/Temash. Beema/Mullins has not been measured.

http://www.anandtech.com/show/7355/chipworks-provides-first-apple-a7-die-shot

http://www.anandtech.com/show/6977/a-closer-look-at-the-kabini-die

http://www.anandtech.com/show/7314/intel-baytrail-preview-intel-atom-z3770-tested

"Intel isn’t disclosing die size or transistor counts, which is ironic (and disappointing) given that Apple just disclosed both (or at least relative magnitude of one) for its A7 SoC."

Intel would not be so secretive if they had a significant die size advantage. Looks like Intel's process capability and Intel's product design are two entirely different things. :thumbsup:

Yes, Bay Trail has a bloated die size for what it offers. I pointed that out in another thread. I believe it has less to do with density, and more to do with design decisions and time to market.

But honestly, why are you being so distrusting? Is there some sort of precedent where Intel or others have fudged their numbers at these academic conferences? That's against the spirit of those events...

You did the math correct for TSMC 16 FinFET (TSMC reported 0.07um^2), though your Intel number seems off.

A 2.2x reduction is 1/(2.2) meaning that you MULTIPLY by 0.455 not 0.55, leading you to a 14nm SRAM cell size for Intel of ~0.042um^2.

Yeah. 0.092 / 2.2 = ~0.042.

 

[raghu78]

The issue of Intel being a successful foundry is a completely different one to whether TSMC will close the gap to Intel's process lead. It is not helpful to meaningful discussion to conflate the two things.

Not really. Intel's future strategy revolves around using their process leadership and excess fab capacity to compete against TSMC/Samsung. Also the epic battle between Intel and ARM is played out with the help of the foundries. TSMC and Samsung's future survival relies on reducing the process gap at the leading edge and taking semiconductor business away from Intel. At the leading edge nodes like 14nm and below the sales volume required to sustain process R&D and fab building/equipment costs is going higher and with Intel going after mobile while ARM going after server its an all out war.

These foundries pose a risk for Intel as ARM is taking market share from x86 as does Intel pose a threat to these foundries if they succeed in eating into mobile market share. The traditional x86 PC market faces cannibilization as both Intel and AMD lost more than 2 billions dollars of revenue in the last 2 years to ARM based tablets, phones and notebooks/chromebooks. ARM's entry into servers is a bigger threat and the foundries stand to gain even more by enabling Intel competitors like AMD, Nvidia, Applied Micro to gain server marketshare.

Anybody who realizes where this war is headed knows its Intel vs the rest of the semiconductor industry which includes the architectural licensees like ARM / OpenPOWER , fabless design companies likes Apple, Qualcomm, AMD, Nvidia and foundries like TSMC/Samsung/GF. And there is no dearth of resources or will to take the fight to Intel and succeed.

 

[raghu78]

Yes, Bay Trail has a bloated die size for what it offers. I pointed that out in another thread. I believe it has less to do with density, and more to do with design decisions and time to market.

exactly. Intel's actual products need to show the signs of process leadership. The lead cannot be on paper. So if there is a 100 sq mm Apple A8 and a Broadwell 14nm dual core chip with roughly the same size and both are rated at 5w TDP then Intel should crush the competition. Same for Apple A9 and other SOCs manufactured at TSMC 16 FF+ against Intel's similarly sized and TDP rated SOCs.

But honestly, why are you being so distrusting? Is there some sort of precedent where Intel or others have fudged their numbers at these academic conferences? That's against the spirit of those events...

I don't distrust their numbers if they are made at technical industry events like IEDM, ISSCC. But I would be wary of both TSMC and Intel claims and look for actual products to show their mettle.

 

[Arachnotronic]

Not really. Intel's future strategy revolves around using their process leadership and excess fab capacity to compete against TSMC/Samsung. Also the epic battle between Intel and ARM is played out with the help of the foundries. TSMC and Samsung's future survival relies on reducing the process gap at the leading edge and taking semiconductor business away from Intel. At the leading edge nodes like 14nm and below the sales volume required to sustain process R&D and fab building/equipment costs is going higher and with Intel going after mobile while ARM going after server its an all out war.

These foundries pose a risk for Intel as ARM is taking market share from x86. The traditional x86 PC market faces cannibilization as both Intel and AMD lost more than 2 billions dollars of revenue in the last 2 years to ARM based tablets, phones and notebooks/chromebooks. ARM's entry into servers is a bigger threat and the foundries stand to gain even more by enabling Intel competitors like AMD, Nvidia, Applied Micro to gain server marketshare.

Anybody who realizes where this war is headed knows its Intel vs the rest of the semiconductor industry which includes the architectural licensees like ARM / OpenPOWER , fabless design companies likes Apple, Qualcomm, AMD, Nvidia and foundries like TSMC/Samsung/GF. And there is no dearth of resources or will to take the fight to Intel and succeed.

I find it hilarious that Intel raised guidance and consensus now calls for Intel to grow its top line by about $1.5 billion over 2013. That's even with contra-revenue mostly wiping out any potential tablet revenues (those come back in 2015 when the platform BoM is fixed) and even with cellular baseband/RF down for the year.

By the way, why is ARM/Foundries the only ones that can gain share here? Why is AMCC so poised to gain share in servers, but Intel cannot gain meaningful share in tablets/smartphones/RF?

Anyway, it'll be interesting to see how your predictions play out.

 

[jdubs03]

@raghu

some of the info is here: http://seekingalpha.com/article/1967581-intel-and-taiwan-semiconductor-have-very-different-definitions

the special R&D process* team was from the op.

i compared 22nm FF to 20nm, because FinFET's are clearly more difficult to integrate than planar. you're point with double litho patterning could be one of intel's issues with yields.

if 16FF+ is 3-6 months behind 16FF then that still gives vendors a dilemma; apple could opt to delay their iphone 6s release, so that is a potential late Q4-2015/Q1-2016 release. or they could go 16FF in September 2015, then 16FF+ in 2016. So, it depends obviously on the assumptions. But I don't think I'm underestimating TSMC, but they are clearly behind and its more than a year.

 

[Arachnotronic]

@raghu

some of the info is here: http://seekingalpha.com/article/1967581-intel-and-taiwan-semiconductor-have-very-different-definitions

the special R&D process* team was from the op.

i compared 22nm FF to 20nm, because FinFET's are clearly more difficult to integrate than planar. you're point with double litho patterning could be one of intel's issues with yields.

if 16FF+ is 3-6 months behind 16FF then that still gives vendors a dilemma; apple could opt to delay their iphone 6s release, so that is a potential late Q4-2015/Q1-2016 release. or they could go 16FF in September 2015, then 16FF+ in 2016. So, it depends obviously on the assumptions. But I don't think I'm underestimating TSMC, but they are clearly behind and its more than a year.

I view TSMC 16 FF+ like I view 28nm HPm v.s. 28nm polysilicon.

I think 16 FinFET will ramp in volume during 2016 from guys like Qualcomm, then 16 FinFET+ comes a year later (which is actually more aggressive than what the 28nm poly-si v.s. 28nm HKMG delta looked like).

 

[raghu78]

I find it hilarious that Intel raised guidance and consensus now calls for Intel to grow its top line by about $1.5 billion over 2013. That's even with contra-revenue mostly wiping out any potential tablet revenues (those come back in 2015 when the platform BoM is fixed) and even with cellular baseband/RF down for the year.

Intel's bump in the PC business is due to the XP end of life refresh in the commercial segment and not a sustaining trend. Intel has been facing challenges in its traditional PC business and in the mobile market. Going forward that extends to servers from 2015 onwards as ARM servers compete against Intel for the server business. Also Intel's x86 server market share is 97+% so there is a lot to lose for Intel against the ARM ecosystem. Also companies like Google, Facebook,Amazon are looking at customized server designs for their computing needs based on OpenPOWER / ARM.

http://www.zdnet.com/google-eyes-power-chips-amazon-arm-both-add-up-to-intel-headaches-7000028881/

 

[AtenRa]

You did the math correct for TSMC 16 FinFET (TSMC reported 0.07um^2), though your Intel number seems off.

A 2.2x reduction is 1/(2.2) meaning that you MULTIPLY by 0.455 not 0.55, leading you to a 14nm SRAM cell size for Intel of ~0.042um^2. If this is actually true, then this is denser than the 10nm SRAM cell size that Samsung/GloFo/etc. reported for their 10nm node at the recent VLSI conference (0.052um^2).

I eagerly await proper process disclosures from Intel.

Never make calculations before you drink your coffee in the morning
Everything is wrong not only the Intel numbers
I will revise them all.

 

[raghu78]

@raghu

some of the info is here: http://seekingalpha.com/article/196...semiconductor-have-very-different-definitions

the special R&D process* team was from the op.

i compared 22nm FF to 20nm, because FinFET's are clearly more difficult to integrate than planar. you're point with double litho patterning could be one of intel's issues with yields.

if 16FF+ is 3-6 months behind 16FF then that still gives vendors a dilemma; apple could opt to delay their iphone 6s release, so that is a potential late Q4-2015/Q1-2016 release. or they could go 16FF in September 2015, then 16FF+ in 2016. So, it depends obviously on the assumptions. But I don't think I'm underestimating TSMC, but they are clearly behind and its more than a year.

The difference is you are quoting an Intel uber bull Ashraf Eassa who has no idea of semiconductor manufacturing while I am quoting TSMC's management on a earnings conference call. Who do you want to believe is upto you ?

TSMC is on record stating that the vast majority of volume production of FINFET production in 2015 is at TSMC 16FF+. TSMC 16FF+ looks likely to go into production by Q2 2015 (analysts confirm the same) so Apple can make the A9 at TSMC 16FF+. Also most analyst reports are stating that Apple is looking at multi sourcing A9 from TSMC and Samsung/GF . The 14nm GF licensing from Samsung is to help Apple avoid wafer shortages. You can choose not to believe them. As usual end customer products will reveal if TSMC was right or wrong. :thumbsup: