Discussion Beyond zen 6

[LightningZ71]

There's a modest improvement from N6 to the N5 family in SRAM density. I thought that AMD might go for an N4C based SRAM die, but I've read here a couple of times that AMD isn't exactly enamored with that node for various reasons. I've wondered if Samsung's "2nm" class mode that seems to be hitting HVM might be usable, but I imagine that it would add complications to the stacking process to source it from anything but TSMC.

 

[adroc_thurston]

There's not really that much benefit to going smaller in terms of SRAM cell density.

The benefit is speed.
Cache runs core clock.

 

[Joe NYC]

There's not really that much benefit to going smaller in terms of SRAM cell density. Might help latency a bit, but shaving a few cycles of latency off an L3 isn't that big of a win.

I suppose the price difference between N6 and N4 wafers isn't all that large though. So they might but it isn't going to make all that much difference either way.

I don't think AMD needs any density improvement to fit 96 MB of cache for Zen 6.

The old die that was on top used to be 30 to 36 mm2 and accommodated 64 MB of L3. Now the base die is 75 mm2, so it can fit 128 MB just fine and AMD is only planning to use 96 MB.

AMD must already have some way to have the base die run at lower clock speeds, such as 1/2 of the CPU clock speed. And for that N6 should be just fine.

The issue with going to N4 for Zen 6 probably has more to do with scarcity of that capacity, while N6 should be abundant. That might be a good reason to stay with N6 until AMD gets to Zen 7 and by that time, TSMC should be drowning in N4 capacity.

 

[adroc_thurston]

The old die that was on top used to be 30 to 36 mm2 and accommodated 64 MB of L3. Now the base die is 75 mm2, so it can fit 128 MB just fine and AMD is only planning to use 96 MB.

Not even remotely comparable since Zen5+ X3D base die needs a crapton of feedthru TSVs to deliver all the power into the compute on top.

AMD must already have some way to have the base die run at lower clock speeds, such as 1/2 of the CPU clock speed. And for that N6 should be just fine.

It's L3. AMD L3 runs cclk.

 

[Fjodor2001]

course they will pay.
GPU market already survived a few rounds of ASP hikes and it's doing better than ever

Because perf increase from one generation to the next is much greater for GPUs than CPUs, so it’s worth spending that much more on latest GPU gen.

Yes they do hence why 9800X3D owns the DIY space.

Because X3D monopoly. And because next gen has not been the much more expensive than previous gen (otherwise people would go for previous gen instead). No ridiculous 100% price increase to next gen like you are predicting for Zen7.

 

[Fjodor2001]

MLID had some slides that showed existence of 8c chiplet. Once it exists, it will be used.

First, it’s MLID so speculation.

Second, perhaps used for e.g. server or mobile/laptop only (if it exists).

 

[adroc_thurston]

Because perf increase from one generation to the next is much greater for GPUs

Not anymore they ain't.

so it’s worth spending that much more on latest GPU gen.

People were throwing tantrums about ASP hikes ever since TU102 yet bought it anyway.

Because X3D monopoly. And because next gen has not been the much more expensive than previous gen (otherwise people would go for previous gen instead). No ridiculous 100% price increase to next gen like you are predicting for Zen7.

Yes my child, people do pay top dollar for the best.
And people will stomach ASP hikes just like they did in GPUlandia.

Second, perhaps used for e.g. server or mobile/laptop only (if it exists).

It's primarily for desktop and luggables.
Mobile has 8c monodies just fine.

 

[branch_suggestion]

Because perf increase from one generation to the next is much greater for GPUs than CPUs, so it’s worth spending that much more on latest GPU gen.

Not in gaming, especially if we consider your precious nT perf.
Perf/$ below $500 is not changing much at all, such is the death of Moore's Law.
Only top dies are getting acceptable CAGR these days.

 

[Doug S]

The benefit is speed.
Cache runs core clock.

And that's not a problem regardless of the process being used. If (for example) you had a max clock of 5 GHz with a budget of 12 FO4 delays per cycle you could clock it at 6 GHz if you cut it to 10 FO4 delays. That would have a latency cost since fewer FO4 delays per cycle mean less work happens.

So no, clock rate is not a reason to move off N6. It is a benefit, but not a necessity. That assumes Zen 6 is clocked significantly higher too which remains to be seen. If it is only clocked 5% faster then there is probably room for running the cache at that speed, and if not dropping one FO4 delay and adding a few cycles would be the cost.

Not saying they won't move on from N6, the cost difference with N4 isn't that large. But they don't have to if they don't want to.