Discussion Beyond zen 6

[LightningZ71]

There's a modest improvement from N6 to the N5 family in SRAM density. I thought that AMD might go for an N4C based SRAM die, but I've read here a couple of times that AMD isn't exactly enamored with that node for various reasons. I've wondered if Samsung's "2nm" class mode that seems to be hitting HVM might be usable, but I imagine that it would add complications to the stacking process to source it from anything but TSMC.

 

[adroc_thurston]

There's not really that much benefit to going smaller in terms of SRAM cell density.

The benefit is speed.
Cache runs core clock.

 

[Joe NYC]

There's not really that much benefit to going smaller in terms of SRAM cell density. Might help latency a bit, but shaving a few cycles of latency off an L3 isn't that big of a win.

I suppose the price difference between N6 and N4 wafers isn't all that large though. So they might but it isn't going to make all that much difference either way.

I don't think AMD needs any density improvement to fit 96 MB of cache for Zen 6.

The old die that was on top used to be 30 to 36 mm2 and accommodated 64 MB of L3. Now the base die is 75 mm2, so it can fit 128 MB just fine and AMD is only planning to use 96 MB.

AMD must already have some way to have the base die run at lower clock speeds, such as 1/2 of the CPU clock speed. And for that N6 should be just fine.

The issue with going to N4 for Zen 6 probably has more to do with scarcity of that capacity, while N6 should be abundant. That might be a good reason to stay with N6 until AMD gets to Zen 7 and by that time, TSMC should be drowning in N4 capacity.

 

[adroc_thurston]

The old die that was on top used to be 30 to 36 mm2 and accommodated 64 MB of L3. Now the base die is 75 mm2, so it can fit 128 MB just fine and AMD is only planning to use 96 MB.

Not even remotely comparable since Zen5+ X3D base die needs a crapton of feedthru TSVs to deliver all the power into the compute on top.

AMD must already have some way to have the base die run at lower clock speeds, such as 1/2 of the CPU clock speed. And for that N6 should be just fine.

It's L3. AMD L3 runs cclk.

 

[Fjodor2001]

course they will pay.
GPU market already survived a few rounds of ASP hikes and it's doing better than ever

Because perf increase from one generation to the next is much greater for GPUs than CPUs, so it’s worth spending that much more on latest GPU gen.

Yes they do hence why 9800X3D owns the DIY space.

Because X3D monopoly. And because next gen has not been the much more expensive than previous gen (otherwise people would go for previous gen instead). No ridiculous 100% price increase to next gen like you are predicting for Zen7.

 

[Fjodor2001]

MLID had some slides that showed existence of 8c chiplet. Once it exists, it will be used.

First, it’s MLID so speculation.

Second, perhaps used for e.g. server or mobile/laptop only (if it exists).

 

[adroc_thurston]

Because perf increase from one generation to the next is much greater for GPUs

Not anymore they ain't.

so it’s worth spending that much more on latest GPU gen.

People were throwing tantrums about ASP hikes ever since TU102 yet bought it anyway.

Because X3D monopoly. And because next gen has not been the much more expensive than previous gen (otherwise people would go for previous gen instead). No ridiculous 100% price increase to next gen like you are predicting for Zen7.

Yes my child, people do pay top dollar for the best.
And people will stomach ASP hikes just like they did in GPUlandia.

Second, perhaps used for e.g. server or mobile/laptop only (if it exists).

It's primarily for desktop and luggables.
Mobile has 8c monodies just fine.

 

[branch_suggestion]

Because perf increase from one generation to the next is much greater for GPUs than CPUs, so it’s worth spending that much more on latest GPU gen.

Not in gaming, especially if we consider your precious nT perf.
Perf/$ below $500 is not changing much at all, such is the death of Moore's Law.
Only top dies are getting acceptable CAGR these days.

 

[Doug S]

The benefit is speed.
Cache runs core clock.

And that's not a problem regardless of the process being used. If (for example) you had a max clock of 5 GHz with a budget of 12 FO4 delays per cycle you could clock it at 6 GHz if you cut it to 10 FO4 delays. That would have a latency cost since fewer FO4 delays per cycle mean less work happens.

So no, clock rate is not a reason to move off N6. It is a benefit, but not a necessity. That assumes Zen 6 is clocked significantly higher too which remains to be seen. If it is only clocked 5% faster then there is probably room for running the cache at that speed, and if not dropping one FO4 delay and adding a few cycles would be the cost.

Not saying they won't move on from N6, the cost difference with N4 isn't that large. But they don't have to if they don't want to.

 

[MadRat]

Post-Zen 6 probably means new technologies at the wafer level beyond a shrinking of the process. I wonder if one started with wafer, attached a 50 nm aluminum foil down on the wafer, ensured to smoothed it out across the wafer, then laid down a layer of silicon. The 50 nm layer could be tunneled down to for a ground. More importantly it would conduct heat substantially better than the underlying silicon. You can then build the chip on top of that silicon layer. Maybe the underlying wafer is made out of something other than silicon. Maybe the aluminum is the wafer and then you deposit silicon on both sides and etch chips on both sides. The shape of a non-silicon wafer wouldn't need to be rectangular at that point. Maybe its round or curved like a soft contact for the eye. Imagine how well liquid cooling or thermal heat pipe technology works when its 30-40 nm away from the heat source. Just thinking outside the box.

 

[Fjodor2001]

Not in gaming, especially if we consider your precious nT perf.
Perf/$ below $500 is not changing much at all, such is the death of Moore's Law.
Only top dies are getting acceptable CAGR these days.

Wut. You get better gen to next gen upgrade perf increase for CPU upgrade than GPU upgrade in gaming? Please show benchmarks proving that.

 

[adroc_thurston]

You get better gen to next gen upgrade perf increase for CPU upgrade than GPU upgrade in gaming?

Yeah?

Please show benchmarks proving that.

Any 103 to 103 die is ezpz.

 

[gdansk]

Wut. You get better gen to next gen upgrade perf increase for CPU upgrade than GPU upgrade in gaming? Please show benchmarks proving that.

I think you are generally correct here. But last generation in GPUs was bleak at some segments
Compare TPU summaries
RTX 4080S - $1000 1.00x performance in games
RTX 5080 - $1000* 1.12x performance in games
vs CPUs
7800X3D - $450 1.00x performance in games
9800X3D - $450 1.11x performance in games

* = seemingly a fictional MSRP

Obviously the CPU won't actually make your gaming faster unless paired with a nice GPU. Maybe if you play at stupidly low settings. Some shooter fans might.

 

[Covfefe]

Wut. You get better gen to next gen upgrade perf increase for CPU upgrade than GPU upgrade in gaming? Please show benchmarks proving that.

It's true. CPUs are increasing in perf/$ slightly faster than GPUs, or at least they're on the same pace. The RTX 3080 is 0.63x as fast as the RTX 5080 TPU review. The 5080 costs 25% more. The R7 3700X is 0.64x as fast as the R7 9700X TPU review. The 9700X costs 9% more.

Average annual perf/$ increase works out to 2.4% for GPU and 7.3% for CPU.

GPU (RTX 5080 vs RTX 3080)​	CPU (R7 3700X vs R7 9700X)​	​
4.37​	5.09​	years between releases​
0.63​	0.64​	performance gap​
1.43x​	1.09x​	price change​
1.11x​	1.43x​	perf/$ improvement​
102.44%​	107.31%​	performance/dollar/year​

edit: I'm dumb and misremembered the 3080 MSRP as $800 instead of $700, fixed.

 

[Fjodor2001]

I was talking about perf increase from moving from current gen top SKU to next gen top SKU. E.g. 4090 -> 5090, vs 7950(X3D) -> 9950(X3D). The former (GPU) provides better perf increase than the latter (CPU).

Regardless of $.

But yes, if we throw $ into the equation, things change.

 

[gdansk]

I was talking about perf increase from moving from current gen top SKU to next gen top SKU. E.g. 4090 -> 5090, vs 7950(X3D) -> 9950(X3D). The former (GPU) provides better perf increase than the latter (CPU).

Regardless of $.

But yes, if we throw $ into the equation, things change.

I mean even discarding $, look at the same die size. The last generation AD103 -> GB203 was about the same increase to their potential performance as Zen 4 X3D -> Zen 5 X3D. Both remained at about the same die size as their predecessor.
If that's the new norm then we're in for a garbage gaming future. I hope for a better future but it'll probably only come to pass if someone can disrupt Nvidia's 90-95% market share.

 

[adroc_thurston]

if someone can disrupt Nvidia's 90-95% market share

Lmao

 

[gdansk]

Lmao

Well that's for another thread

 

[Thibsie]

As for zen7 I expect AMD to use vCacje as standard e.g. keep L1 on the die but move L2 and L3 out of it.

Is this reasonable ? I think so but….

 

[adroc_thurston]

As for zen7 I expect AMD to use vCacje as standard e.g. keep L1 on the die but move L2 and L3 out of it.

Dense CCD is a sandwich yes.
Rest, no.

 

[Joe NYC]

As for zen7 I expect AMD to use vCacje as standard e.g. keep L1 on the die but move L2 and L3 out of it.

Is this reasonable ? I think so but….

My prediction is that there will still be a single die desktop client CPU, with 2MB L2, 4 MB L3 per core, but V-Cance die will have 2MB L2 and 8 MB L3 per core.

The dense cores are already moving L3 off the main die. Maybe the next Zen gen will do the same for vanilla cores.

 

[marees]

grok summary

• 7:07–9:27 — Budget desktop variant: Renders of smaller 8-core Silverking chiplets (~half the die size of Silverton, ~56 mm², no V-Cache, reduced bandwidth). These enable cheap AM5 CPUs (e.g., sub-$300 8-core parts) by using "leaky" yields binned for lower clocks/efficiency.
• 9:27–10:49 — Grimlock Point laptop APU: Approximate render of a 20+ core mobile chip, with 12 cores directly on the IOD (200 mm² estimate, evolved from Zen 6 Medusa Point), plus optional added chiplets (e.g., +8 cores). Modular design, efficiency-focused binning.
• 10:49–12:52 — Grimlock Halo (premium laptop APU): Renders of the 36+ core "mega" variant, with ~20 cores on the IOD base (mix of full Zen 7 + dense Zen 7C cores, possibly extra low-power ones), plus two 8-core chiplets added via bridge dies for expansion. Looks superficially similar to Strix Halo (Zen 5), includes monolithic base with GPU compute units. Emphasizes high core counts for future premium laptops.

https://twitter.com/x/status/2027481614268436513

 

[dangerman1337]

Just wonder why Grimlock needs all those CPU cores? Would rather have that die space allocated to the iGPU. Feels tad weird to have like 20 Cores on Grimlock Halo's iGPU/IO Die.

 

[marees]

Just wonder why Grimlock needs all those CPU cores? Would rather have that die space allocated to the iGPU. Feels tad weird to have like 20 Cores on Grimlock Halo's iGPU/IO Die.

the below is only grimlock point 1 (12 cores on iod) & grimlock point 1 high (extra silverking ccd with 8 cores)

Grimlock Point laptop APU: Approximate render of a 20+ core mobile chip, with 12 cores directly on the IOD (200 mm² estimate, evolved from Zen 6 Medusa Point), plus optional added chiplets (e.g., +8 cores). Modular design, efficiency-focused binning.

there is also grimlock point 2, 3, & 4 (goes all the way down to 15 watts)

I am guessing the core count will reduce for the lower variants

 

[Joe NYC]

the below is only grimlock point 1 (12 cores on iod) & grimlock point 1 high (extra silverking ccd with 8 cores)



there is also grimlock point 2, 3, & 4 (goes all the way down to 15 watts)

I am guessing the core count will reduce for the lower variants

It seems like AMD is determined to stay monolithic for vast majority of mobile CPUs. Well into 2030.