[Ashraf] 10nm "Lakefield" SoC with Intel big + little cores

[piokos]

Also we know the maximum Turbo for Tremont is 1.8GHz, while Geminilake can do 2.6-2.7. The MT Geekbench scores are pretty close between Lakefield and Pentium Silver N5000, clock speed differences making up for uarch differences.

But these are totally different products so why exactly are you focusing on max throughput? This is not what these CPUs are about.
Lakefield is meant to work in always-on devices. So the main focus was to make it run on fraction of a Watt. The fact that it scales up to 7W (or 9.5W in boost) is the amazing part. There's no way it'll beat more performance-focused chips in benchmarks.

I'm 99% sure Lakefield will "fails and costs lots of money", that's usually the case when you release bleeding edge product with hope that it's technology will be useful for later generations. After almost 1 year from being announced we get 2 SKUs and so far only 2 design wins. No way it can pay off.

We get as many SKUs as OEMs ordered. Intel could have, obviously, made 20 SKUs and differentiate them by 100MHz in clocks.
It's also targeting pretty much a new niche in computing, so expecting many devices so early is unrealistic.
But remember it's not just Intel who decided to bet on this idea. There's also Microsoft (W10X), there are a few OEMs with new form factors in the works. Clearly, they all think this has a chance to stick.

Other than that - it's also a showcase of what Intel was working on lately:
- heterogeneous x86,
- 3D stacked SoC,
- MCM (with mixed node process),
- POP RAM integration.
1-2 years from now probably every Intel's consumer chip will implement something from this list.

And when Foveros becomes usable in large chips, we may see stacked server processors as well.

I think Intel might have some problems with production/assembly of this chip.

It would be naive to think they don't - given how totally new this thing is.
But keep in mind this is OEM-only. These chips are usually announced with some products. Intel worked with Samsung/Lenovo and probably with Microsoft as well. It's a bit more complex than just rushing a chip for a paper launch (like what often happens in the DIY desktop niche).
Even if it is delayed, we can't be sure who was the last side to deliver.

You sure about that? Atom has never had Turbo Boost 2.0 so the concept of PL2 and PL3 shouldn't exist.

https://www.intel.com/content/www/u...html?grouping=EMT_Content Type&sort=title:asc

 

[Markfw]

But these are totally different products so why exactly are you focusing on max throughput? This is not what these CPUs are about.
Lakefield is meant to work in always-on devices. So the main focus was to make it run on fraction of a Watt. The fact that it scales up to 7W (or 9.5W in boost) is the amazing part. There's no way it'll beat more performance-focused chips in benchmarks.

We get as many SKUs as OEMs ordered. Intel could have, obviously, made 20 SKUs and differentiate them by 100MHz in clocks.
It's also targeting pretty much a new niche in computing, so expecting many devices so early is unrealistic.
But remember it's not just Intel who decided to bet on this idea. There's also Microsoft (W10X), there are a few OEMs with new form factors in the works. Clearly, they all think this has a chance to stick.

Other than that - it's also a showcase of what Intel was working on lately:
- heterogeneous x86,
- 3D stacked SoC,
- MCM (with mixed node process),
- POP RAM integration.
1-2 years from now probably every Intel's consumer chip will implement something from this list.

And when Foveros becomes usable in large chips, we may see stacked server processors as well.

It would be naive to think they don't - given how totally new this thing is.
But keep in mind this is OEM-only. These chips are usually announced with some products. Intel worked with Samsung/Lenovo and probably with Microsoft as well. It's a bit more complex than just rushing a chip for a paper launch (like what often happens in the DIY desktop niche).
Even if it is delayed, we can't be sure who was the last side to deliver.

https://www.intel.com/content/www/u...html?grouping=EMT_Content Type&sort=title:asc

I just have to say... reading your posts is like reading an Intel advertisement. And the two bolded sections and the use of the word "we" sure makes it sound like you work for them. Do you work for them ?

 

[mikk]

I just have to say... reading your posts is like reading an Intel advertisement. Do you work for them ?

This question is so funny since your postings often look like reading an AMD advertisement, do you work for them?

 

[Markfw]

This question is so funny since your postings often look like reading an AMD advertisement, do you work for them?

I am retired from Healthcare. What in the hell makes you think I work for AMD ? Because they currently are the technology leader ? Gee thats what a CPU moderator should know about.

Maybe you work for Intel as well ?

 

[lobz]

And they will all work in Lakefield. Intel stated during development that all big and small cores will be available at the same time (this is called heterogeneous multi-processing / HMP).
It was different with ARM. HMP was implemented few years after big.LITTLE. Before that only half of the CPU was working.

The problem is not in running software on all cores. They share the same ISA.
The hard part is efficient scheduling.
In a homogeneous CPU you can just throw a job to any free core. They're all the same.
In a heterogeneous CPU you have to try to give the "big" tasks to the "big" cores.

The 7-zip example is actually easy, because the threads are independent (much like with rendering). Each one calculates part of the problem, puts it on a stack and gets another one.
The issue is when threads have to be synchronized, i.e. they have to wait for someone else to finish.

Let's say you have a program that runs 2 threads on 2 identical "big" cores:
- A - big job - takes 1s
- B - small job - takes a lot less, like 0.1s
After each round they have to "talk" and then another rounds starts.
In this case cores can be assigned randomly - it doesn't matter.

Now you replace one "big" core with 4 "small" ones. Let's say the total throughput is the same, i.e. one "small" core is 4 times slower.
What we're after is optimal assigning:
- A -> big
- B -> small
because then the whole round still takes 1s.

If task A goes to a small core, performance drops 4 times.
Which means that assigning randomly on a 1+4 architecture, it'll be optimal in just 20% rounds.
So, on average, each round will take 3.4s. And we just lost 2/3 of performance.

Have you ever written software that's not hello world?

 

[DrMrLordX]

But these are totally different products so why exactly are you focusing on max throughput?

There's two reasons for this:

1). It highlights the effects of the low boost clocks for the Tremont cores.
2). It suggests possible problems with Intel's packaging problem wrt heat dissipation, though without temp sensor data there's no way for us to know.

Lakefield is, to date, the only implementation of Foveros that one could realistically hope to buy through normal channels. Anyone who wants to learn more about Foveros (or Tremont for that matter) is going to have an avid interest in this thing.

The greater question, for me, is: if Lakefield can't beat an old Gemini Lake SoC in MT workloads, what exactly is the point of this thing vs. a hypothetical 4c Tremont with boost clocks higher than 1.8 GHz? Was that simply not possible on 10nm?

 

[JasonLD]

I just have to say... reading your posts is like reading an Intel advertisement. Do you work for them ?

Despite his post being all written like Intel promotional material, his post was on topic while yours wasn't. Why are you provoking him to make hostile reply? You are the moderator and you should be the one policing those type of posts you are making. wow.





You may not reference a moderators title in any post . Period. Have an issue? Post a thread in Moderators Discussion


esquared
Anandtech Forum Director

 

[IntelUser2000]

This is a small device but it needs active cooling! It's also much much thicker than the Samsung Galaxy Book S. Because of the active cooling you can be sure this score has been achieved running at 15W. If it would be at 6W the big majority of N5000 devices would be close to this score but they are not.

While you have a point there about the Topjoy device, Geekbench 5 results like all user-submitted results are subject to significant score variance at the exact same settings so you cannot compare the results together.

@JasonLD Exactly. Attack the content not the person. Perhaps he has too much power?

But these are totally different products so why exactly are you focusing on max throughput? This is not what these CPUs are about.

I'm probably more bullish on Lakefield than 95% of the people. Yet I agree with those saying if the Geekbench 5 results are in any way representative of the real thing, then its poor, very poor.

N5000 is in no way a high end device. Minimum viable MT score needs to be the ST score shown here + MT result and end up in the range of ~2500 points.

SAMSUNG ELECTRONICS CO., LTD. 767XCL - Geekbench

Benchmark results for a SAMSUNG ELECTRONICS CO., LTD. 767XCL with an Intel Core i5-L16G7 processor.

browser.geekbench.com

You may not reference a moderators title in any post . Period. Have an issue? Post a thread in Moderators Discussion


esquared
Anandtech Forum Director

 

[coercitiv]

You sure about that? Atom has never had Turbo Boost 2.0 so the concept of PL2 and PL3 shouldn't exist.

From Intel's Pentium Silver datasheet

 

[coercitiv]

The greater question, for me, is: if Lakefield can't beat an old Gemini Lake SoC in MT workloads, what exactly is the point of this thing vs. a hypothetical 4c Tremont with boost clocks higher than 1.8 GHz? Was that simply not possible on 10nm?

It's a bit worse than that, we'd have to compare Lakefield to either 6-8c Tremont or 2c Willow Cove. The second one is coming IRC from the Twitter benchmark leaks, I believe there was a Tiger Lake @ 10W or around that figure.

For Lakefield to positively compare to either of these 2 alternatives, it needs to strike the best possible balance in ST&MT ultra-portable consumer loads. Personally I believe the hybrid approach is definitely the future, but Lakefield is just an altar sacrifice to get there. Two big cores is a must for premium devices today, only then it's worth adding the small cores for additional power and throughput benefits.

 

[IntelUser2000]

@coercitiv What Tigerlake won't top it is in battery life and form factor. So if you want a proper 10-inch or smaller x86 device, Lakefield is it. Based on device reviews Geminilake can't really do that either.

But it needs a bit more than that. My hope is the scheduler is smart enough to have all 5 cores working in MT in real world applications.

 

[TheGiant]

IMO lakefield is the pipecleaner of the foveros real delivery
the breaking point for me is the "always on" devices which @piokos mentioned
this must be the selling point, otherwise the 2C icelake is the same
so far its a little late, its performance isn't ground breaking, but it looks still acceptable

 

[coercitiv]

What Tigerlake won't top it is in battery life and form factor. So if you want a proper 10-inch or smaller x86 device, Lakefield is it. Based on device reviews Geminilake can't really do that either.

Tigerlake being unfit in terms of packaging size doesn't invalidate the 2x SNC core combo choice for Lakefield, unless TGL simply gets beaten in MT by Lakefield while running at ISO power. Low power potential is also debatable, although I concede small cores have an undeniable advantage here. It's just that this advantage should come after ensuring proper performance, and here Apple set the perfect example. In fact, I always believed Intel was on the right path too with their 2 big core Y chips and expected to keep that as foundation for a hybrid approach.

We'll see, I'm trying to keep an open mind about Lakefield, it's just that I started from the opposite side of the expectation spectrum as you did.

But it needs a bit more than that. My hope is the scheduler is smart enough to have all 5 cores working in MT in real world applications.

That might be quite a headache, but at least it's a software headache. The core combo is... set in silicon.

 

[DrMrLordX]

It's a bit worse than that, we'd have to compare Lakefield to either 6-8c Tremont or 2c Willow Cove.

It gets a bit worse when you consider how things worked out. Tremont should have been ready by now to completely replace anything Goldmont/Goldmont+. Okay, maybe 8c Tremont would be out of the question given 10nm yields. But 4c Tremont should have been doable, and it would be a direct upgrade from existing Goldmont/Goldmont+ products assuming it could reach the same clockspeeds. At least 4c Tremont should be doable! But we've seen nothing, until Lakefield, which is itself delayed and sporting very low clocks for its Tremont cores.

Tremont's supposed to be in all kinds of devices by now - comm equipment, automotive (okay, maybe Intel has thrown in the towel there), low-power consumer devices, etc. Isn't Lakefield the first Tremont product to come to market? I think it beat even the comm equipment, though I have no way of knowing since I don't regularly shop for that kind of thing.

In any case we know that Willow Cove on 10nm is just now coming to market. So that wasn't supposed to have been a potential competitor to Lakefield given when Lakefield should have launched - last year. Tremont 8c is completely up in the air since we have no idea how well Intel could do fabbing that on their existing 10nm node. And furthering that thought, why is Tremont being made to compete with Core anyway? Would 2c Willow Cove be able to compete with a Tremont device on battery life?

Two big cores is a must for premium devices today, only then it's worth adding the small cores for additional power and throughput benefits.

I don't know if I absolutely agree with that. But let's see whether or not Intel can get theri Atom clocks back to where Goldmont+ was and what Tremont's successor brings to the table.

edit: if I had to guess, I would say that a 4c Tremont running with the same clocks as a J5005 (for example) would score ~630 ST and ~2080 MT in GB5. Whether or not that's better than what we see from Lakefield is really up to what you want out of the device.

 

[piokos]

Have you ever written software that's not hello world?

Yeah, some. You?

@JasonLD Exactly. Attack the content not the person. Perhaps he has too much power?

I see your post was moderated as well.
IMO @Markfw pretty much owns the forum. It doesn't matter if he is biased or not on the actual products. This is way out of line.

You may not reference a moderators title in any post . Period. Have an issue? Post a thread in Moderators Discussion

Done.

You are not allowed to publically discuss moderation actions, and you are also
not allowed to call out moderators. You already know this.

AT Mod Usandthem

 

[Gideon]

Regarding the PL2 situation, this is also relevant:

https://twitter.com/x/status/1271000575426134016

I just checked my notes. At Intel Investor Day 2019, they said Lakefield turbo power was 27 W. Yesterday they said it was 9.5 W. I asked repeatedly for Tau. The Intel spokesperson said 'we're not making this detail public'.

 

[piokos]

For Lakefield to positively compare to either of these 2 alternatives

As a compromise - it does. It's a "hot hatch" of CPUs right now - trying to balance between performance in mainstream tasks and frugality - whereas you're saying it's not great because sports cars are faster and family wagons can carry more furniture.
It's fundamentally not possible for a "balanced" product to beat specialized alternatives.
[/QUOTE]
Two big cores is a must for premium devices today, only then it's worth adding the small cores for additional power and throughput benefits.
[/QUOTE]
Not really. The point here was to deliver tiny idle/low load power consumption combined with high single-thread potential (for browsing, opening files, playing multimedia). You only need one big core for that.
This SoC is aimed at "casual" devices - not workstations or high-end gaming laptops. Here, smooth operation is more important than throughput.

Second:
Assuming the 12x12mm form factor was enforced by OEMs, there's basically no space left on the compute die. They couldn't add a second big core without sacrificing the GPU.
And just in case you've missed it: the announced SKUs are i3 and i5.
i7 is still missing. You may be pleasantly surprised very soon.

 

[lobz]

@JasonLD Exactly. Attack the content not the person. Perhaps he has too much power?

No, not exactly. I have never seen any mods here moderating their own discussions. Unlike other forums, mods here actually follow their own guidelines, and outside of their 'job' they are just people who are free to argue what they want. If you guys call their title out instead of disputing what's been written, that really just tells a poor story about your arguments.
In that light it's pretty funny to write: attack the content, not the person. It should alao be: attack the content, not the title.

Sorry for off topic.

 

[piokos]

Regarding the PL2 situation, this is also relevant:

https://twitter.com/x/status/1271000575426134016

For 27W the single Sunny Cove core would have to pull 20W. It's probably possible (>4GHz), just doesn't make sense in the announced SKUs.
i3-L13G4 and i5-L16G7 are made for devices that could dissipate 27W.

27W could be the figure we'll see in an i7 - either clocked very high or with 2 big cores.

 

[piokos]

No, not exactly. I have never seen any mods here moderating their own discussions.

Well, I reported his posts and asked (on Moderator Discussions) who did the moderation in the posts above. I hope someone will answer - nothing yet.

outside of their 'job' they are just people who are free to argue what they want

But following the rules.
Also, I don't think this is the case on other forums. Mods are usually expected to lead by example - also off-duty (i.e. on forums they don't supervise).
So aside of following the rules (obviously), mods also try to dial discussions down and shift them towards the topic / facts.
This is absolutely not what happened here (and it's not like that's the first time).

I may be biased because I'm the one attacked (repeatedly). But others noticed the issue as well.

Public moderation call outs/discussion are not allowed.
If you have an issue with moderation, create a thread in
moderator discussions.

You do not create a thread in moderation discussions,
and then continue to discuss it in the regular forums.

AT Mod Usandthem

 

[DrMrLordX]

As a compromise - it does. It's a "hot hatch" of CPUs right now - trying to balance between performance in mainstream tasks and frugality - whereas you're saying it's not great because sports cars are faster and family wagons can carry more furniture.

Ugh. Car analogies.

The balance is off. Let's look back to the Lakefield GB5 numbers above. I wish we had something better than GB5 but what can you do?

ST 868
MT 1656

Now let's look at a J5005 Windows result:

https://browser.geekbench.com/v5/cpu/2424970

ST 480
MT 1622

(if you add .gb5 it'll show you that the chip was well-cooled and running at close to 2750 MHz for most of the run)

Assuming Tremont is 30% better than Goldmont - which I THINK is accurate - and lowering clocks from 2750 MHz to 1800 MHz, you get an MT score of 1380. If I'm being pessimistic and I assume that Tremont is only 20% faster per clock than Goldmont, I get an MT score from those four cores of ~1270. Even with that reduced figure . . . why is it that the Sunny Cove core only appears to be adding ~330 points (or less) to the MT score? Something is very much not right here. If we dig juuuust a little deeper:

https://browser.geekbench.com/v5/cpu/1899203.gb5

it looks like the Sunny Cove core maintains clocks of around 2.9 GHz for most of the run, with the exception of a few dips (see entries 11-13). What's going on here? Can the Tremont cores not hold 1.8 GHz in the MT segment? If so, why not?

 

[jpiniero]

https://www.intel.com/content/www/u...html?grouping=EMT_Content Type&sort=title:asc

Weird, maybe it references something other than SoC power. Almost all of the n5000 devices on the market are fanless so they wouldn't last very long above 6 W if actually allowed to. But at the same time the devices that NBC didn't really throttle, although most were around 2 Ghz in R15 MT than the 2.6 allowed.

 

[IntelUser2000]

Low power potential is also debatable, although I concede small cores have an undeniable advantage here.

We know its not just because of small cores. You remember Haswell right? It offered 50%+ battery life gains, and not really due to the CPU. Yet they still have lot more work to do. I know they can do better. Because back in the Tablet Atom days they in fact did much better. Do you remember Medfield? Same uarch, but 2x+ battery life. I also have an older Atom device that does no better than 15W Ivy Bridge did.

I have a Haswell device. You can get the CPU to be at 0.6W, but its extremely easy to get it off that state. And its more than the CPU. Rest of Platform will use more power as well. And it takes many seconds to come back down to the low power state. So what will happen is for the same device, it'll be very easy for two different users to have very different experience for battery life.

Lakefield again addresses things that you won't see in Tigerlake. I believe Tigerlake will improve on things, but only because its power/frequency curve will improve due to Icelake's 10nm being subpar and Tigerlake improving it on a lot(as evidenced by frequency and IccMax leaks). And maybe the lowest, C10 standby which is only relevant for Modern Standby may improve. But nothing fundamentally changes.

The balance is off. Let's look back to the Lakefield GB5 numbers above. I wish we had something better than GB5 but what can you do?

ST 868
MT 1656

Now let's look at a J5005 Windows result:

https://browser.geekbench.com/v5/cpu/2424970

ST 480
MT 1622

The following picture is why I don't believe Sunny Cove is active:

https://www.cnx-software.com/wp-content/uploads/2019/10/Intel-Lakefield-Performance-Power.png

The gap in every Lakefield leak is in the 2x range. Just like the presentation.

https://browser.geekbench.com/v5/cpu/1899203 (90%)
https://browser.geekbench.com/v5/cpu/1483770 (116%)
https://browser.geekbench.com/v5/cpu/195858 (107%)

 

[coercitiv]

I have a Haswell device. You can get the CPU to be at 0.6W, but its extremely easy to get it off that state. And its more than the CPU. Rest of Platform will use more power as well. And it takes many seconds to come back down to the low power state. So what will happen is for the same device, it'll be very easy for two different users to have very different experience for battery life.

My Haswell U and H CPUs are exactly the reason I said low power is debatable. The biggest problem with Haswell's idle power consumption was indeed the package, not the isolated cores. Cores entered sleep far more easier than the entire package.

At one time I lost quite a bit of time trying to understand why my Toshiba laptop decided to idle at ~2-3W package power, with CPU cores in deep C state sleep but very low C2/C3 Package Residency. It turns out it was a combination of the laptop being connected to an external monitor and also the Windows Power Plan (the Toshiba power plan made it much easier and reliable to obtain high C state residency, there were also clear differences between Power Saver and Balanced IRC).

 

[lobz]

Well, I reported his posts and asked (on Moderator Discussions) who did the moderation in the posts above. I hope someone will answer - nothing yet.

But following the rules.
Also, I don't think this is the case on other forums. Mods are usually expected to lead by example - also off-duty (i.e. on forums they don't supervise).
So aside of following the rules (obviously), mods also try to dial discussions down and shift them towards the topic / facts.
This is absolutely not what happened here (and it's not like that's the first time).

I may be biased because I'm the one attacked (repeatedly). But others noticed the issue as well.

You're getting attacked because of your highly inflammatory tone. On AT forums you must read the rules before commenting on the forum, so I'd really refrain from telling in a CPU topic, what mods are expected to do... I got corrected multiple times and I try to learn from it. Why don't you?