AMD X399 ！！！！！

[OrangeKhrush]

I posted in the "technical thread" on Ryzen from my source that the recent TR leak of supported memory speeds was half true, AM4 current boards do not go beyond 3200Mhz, but he stated that there is a new platform coming, also that Revision 2 and 3 silicon was specially designed for this platform.

I wonder if this is a true high end platform or server platform or APU platform.

 

[french toast]

I posted in the "technical thread" on Ryzen from my source that the recent TR leak of supported memory speeds was half true, AM4 current boards do not go beyond 3200Mhz, but he stated that there is a new platform coming, also that Revision 2 and 3 silicon was specially designed for this platform.

I wonder if this is a true high end platform or server platform or APU platform.

Easiest thing for amd to do is re jig SP3 and launch a single socket naples HEDT with quad channel ram.
Call it R9 1800x.

 

[Hans de Vries]

Looking at the first official roadmap in this thread longside AMD tock tock comments as well as reason stated above we must surely conclude pinnacle ridge = zen 2.

The micro architecture design of znver2 was already finished in 2015....
http://www.kitguru.net/components/c...croprocessor-developer-jim-keller-leaves-amd/

“Architecture decisions are many years in advance of products,” explained the representative for AMD. The development of “Zen” (znver1) and “Zen+” (znver2) micro-architectures – which AMD has disclosed – has been completed a long time ago.

 

[Puffnstuff]

I respectfully disagree. Pinnacle Ridge could be a circuit/process optimization of Summit Ridge.

This is what I hope it is to further refine the cpu by making incremental improvements in all measurable metrics. I really hope that cache throughput is increased to match or best Intel's best chips.

 

[french toast]

The micro architecture design of znver2 was already finished in 2015....
http://www.kitguru.net/components/c...croprocessor-developer-jim-keller-leaves-amd/

Awesome it looks likely PR is zen2.
Honestly zen could benefit having double l2 to 1mb per core, dropping l3 entirely and using HBM as a replacement, optimise the circuitry for low latency, have maybe 512-1GB on die as a replacement L3/L4, that would really help with this ccx penalty imo.

 

[Atari2600]

Awesome it looks likely PR is zen2.
Honestly zen could benefit having double l2 to 1mb per core, dropping l3 entirely and using HBM as a replacement, optimise the circuitry for low latency, have maybe 512-1GB on die as a replacement L3/L4, that would really help with this ccx penalty imo.

Given the sensitivity to memory speeds - am I right in assuming that the L3 cache and RAM access are operating at the same frequency?

If they could de-couple that, and run the internal CPU memory (i.e. cache) at a faster frequency, then it might make the L3 latency problems go away.

 

[french toast]

Given the sensitivity to memory speeds - am I right in assuming that the L3 cache and RAM access are operating at the same frequency?

If they could de-couple that, and run the internal CPU memory (i.e. cache) at a faster frequency, then it might make the L3 latency problems go away.

not sure,Would that only work if there was a bandwidth issue? We know L3 bandwidth is very good on ryzen.
If not then yes could be an option.

 

[formulav8]

If it were Zen 2, it would say something like:

Not necessarily. That roadmap is very lean on details.

 

[OrangeKhrush]

This came from my source so it is almost set in stone

Public knowledge by now but AMD has a new HEDT platform coming out in a couple of months
You'll see more of it at Computex I believe.
It's a 16 core /32 Thread, quad channel behemoth. And it is insanely quick in the tests that Ryzen is already excelling at. So Cinebench, and all other related productivity programs. The gaming issues that were causing the Ryzen AM4 CPUs to behave erratically to say the least have been ironed out. It's akin to a newer revision on a newer platform. This should be competing with the Xeon and of course 6950X Intel offers for $1700~$1800USD, but at about $1,000 USD if not less for some Skews. Coming soon.
CPSs are pretty big physically, about twice the size of surrent 6950X CPUs and a bit more perhaps.
And if you were hoping for pins, nope it's strictly LGA!
IT's NOT 8 channel, but Quad.

Will be a splendid competition between X299 and this AMD platform. Skylake-X is pretty good, not revolutionary but a meaningful step up in IPC and the clocks are pretty high as well. If Intel will have a 32 core part to compete on X299 remains to be seen, but the HEDT platform is going to change quite a bit in the next 4 to 6 months.

AMD's first genuine HEDT system, what he did talk privately about was the new silicon rivisions will trickle down from X399 right the way to R3 1100 for ironed out performance. But dayumn quad channel Ryzen

 

[imported_jjj]

Given the sensitivity to memory speeds - am I right in assuming that the L3 cache and RAM access are operating at the same frequency?

If they could de-couple that, and run the internal CPU memory (i.e. cache) at a faster frequency, then it might make the L3 latency problems go away.

The L3 is in sync with the highest clocked core in its CCX.
The data fabric is in sync with the memory.

 

[.vodka]

This came from my source so it is almost set in stone



AMD's first genuine HEDT system, what he did talk privately about was the new silicon rivisions will trickle down from X399 right the way to R3 1100 for ironed out performance. But dayumn quad channel Ryzen

Holy crap. What a 2017 if this ends up materializing. What a comeback.


If the polished revision trickles down to AM4 later in the form of, say Rx xx50 CPUs, then that's what I'm upgrading to. By this time motherboards should be more than stable.


Do you by any chance know if this newer revision is Pinnacle Ridge, or is it just a minor bugfix/ironed out Summit Ridge?

 

[inf64]

Holy crap. What a 2017 if this ends up materializing. What a comeback.


If the polished revision trickles down to AM4 later in the form of, say Rx xx50 CPUs, then that's what I'm upgrading to. By this time motherboards should be more than stable.


Do you by any chance know if this newer revision is Pinnacle Ridge, or is it just a minor bugfix/ironed out Summit Ridge?

That all sounds like Naples 16C/32T parts for the masses (if anything of that is true of course). I suppose at 1K dollars and IF the clocks can be in 2.7-3Ghz range, AMD could sell a lot of these SKUs to power users that need insanely high throughput for their content creation workloads.

 

[Opcode]

Pinnacle Ridge is Zen, not Zen2. Looks like another Bristol Ridge/Kaby Lake kind of deal here.

Why would AMD release the same exact processor lineup twice? They likely call it "Zen" because there is no other name for new Zen revisions. AMD just differentiates them with a revision number (aka Zen 2). As noted it would make no sense to launch a Ryzen 7 1800X and then a year later launch it again as a Ryzen 7 2800X with exactly no changes. These will more than likely have the newer Zen 2 cores with higher IPC and performance. Meanwhile hopefully with a lot more focus on polishing the intra-CCX links to reduce latency.

 

[cekim]

Meanwhile hopefully with a lot more focus on polishing the intra-CCX links to reduce latency.

I'll see this rumor when I believe it...
The SMT issue might remain for some time as it appears inherent to the structure of the chip as collection of 4-core clusters. Some apps won't care, others can work around it, but from the more detailed analysis of inter-SMT-thread latency I've seen seems to suggest that there's only so much the OS kernel can do and the rest will be up to the application and that will have its limits.

We know how well the application space does with NUMA style optimizations (not very in many cases). Even now, Adobe routinely ignores the second processor on a dual socket system and horrifically under utilizes cores on the first once they go beyond just a few.

To be fair... it's hard. The structure of a single threaded vs a multi-threaded vs a numa-aware app is often very different and tuned to one, runs poorly on others...

re: 200W - Intel has OEM xeons at 180-200W. I'm all for this. Given newer designs' closed loop TDP behavior (measuring current/temp in real time and adjusting clocks accordingly), the idea of a chip that performs to its thermal and power provision limit scaled to whatever absurdity the silicon will support, creates awesome flexibility for end-users and system-integrators to scale to each users's use-case and day-to-day changes in it. It only uses 200W when you ask it to use 200W. It only uses 200W if you have 200W of cooling provided.

 

[Arachnotronic]

Why would AMD release the same exact processor lineup twice? They likely call it "Zen" because there is no other name for new Zen revisions. AMD just differentiates them with a revision number (aka Zen 2). As noted it would make no sense to launch a Ryzen 7 1800X and then a year later launch it again as a Ryzen 7 2800X with exactly no changes. These will more than likely have the newer Zen 2 cores with higher IPC and performance. Meanwhile hopefully with a lot more focus on polishing the intra-CCX links to reduce latency.

Richland. Bristol Ridge.

 

[itsmydamnation]

Richland. Bristol Ridge.

But then you are ignoring what papermaster has said, yearly uarch update. Given that zepplin follow on soc serves so many markets it will be the first soc to be released.

 

[CatMerc]

CPSs are pretty big physically, about twice the size of surrent 6950X CPUs and a bit more perhaps.

?

 

[Ajay]

Richland. Bristol Ridge.

IMHO...It's looking to me like AMD finally got the stick out of its butt and is moving forward with a new impetus. Jim Keller's most significant impact, from what I've read, was the implementation of improved work flow and more rigorous processes from design through silicon verification. I don't think AMD has all the kinks ironed out yet, but I think they will if this turn around is successful (increased sales == increased budgets). AMD has also been sandbagging of late, rather than bragging - so I don't expect anything interesting to show up in a roadmap.

It appears that there is already a new spin coming out fixing a few critical features (necessary as Naples can't afford as many teething issues as Zen). So, AMD is spending money to improve the Zen uarch - I don't see how they can afford not to take an opportunity to improve it further next year. With the recent reorganization at Intel, I doubt they are sitting still.

 

[NostaSeronx]

Richland. Bristol Ridge.

Richland & Godavari. These two were fabricated on the same process as Trinity/Kaveri.

Bristol Ridge has everything that is in Stoney Ridge. VCE/UVD/PSP/HDMI2/4K HDCP/etc. While Bristol/Stoney were fabricated on a similar node to Carrizo with an enhanced source/drain/gate implants. (all that extra electron mobility, woo!)

Expect, Carrizo -> Bristol Ridge or Zambezi -> Vishera. Not Trinity -> Richland or Kaveri -> Godavari.

 

[Arachnotronic]

But then you are ignoring what papermaster has said, yearly uarch update. Given that zepplin follow on soc serves so many markets it will be the first soc to be released.

I'm not ignoring what Papermaster said, but people may be reading into what he said incorrectly.

Tock does not necessarily imply a new CPU core, and the roadmap that just leaked just showed it.

Process and circuit optimization is a totally and completely legitimate way to gain more performance. If 1800X could OC to 4.4GHz on all cores reliably, rather than the 4GHz-ish, then that'd be a solid improvement, no?

 

[itsmydamnation]

I'm not ignoring what Papermaster said, but people may be reading into what he said incorrectly.

Tock does not necessarily imply a new CPU core, and the roadmap that just leaked just showed it.

Process and circuit optimization is a totally and completely legitimate way to gain more performance. If 1800X could OC to 4.4GHz on all cores reliably, rather than the 4GHz-ish, then that'd be a solid improvement, no?

http://www.pcworld.com/article/3155...hitecture-is-expected-to-last-four-years.html

While Anderson’s responsible for bringing Ryzen to market—“you don’t have any idea how many hours I and my team have spent on this,” Anderson said—it’s Papermaster who has to think of the future. When asked how long Zen would last, compared to Intel’s two-year tick-tock cadence, Papermaster confirmed the four-year lifespan and tapped the table in front of him: “We’re not going tick-tock,” he said. “Zen is going to be tock, tock, tock.”

There is no tick/tock/optimize/ optimize in the quote. AMD almost kept 1 year between each BD mirco uarch upgrade with all the roadmap and target changes ,

BD 10-2011
PD 10-2012
SR 06-2014
CR 06-2015

why does it now change for Zen?
Remember BD to PD saw a ~400mhz clock bump on top of the 5-7% IPC bump

 

[Ajay]

Seems to me that this is a question of degree. Zeppelin was the first implementation of a new x86 uarch. The next version will be based on that architecture. The unknown, ATM, is what does AMD consider a 'tock' to be.

Conditioned by the recent sluggishness in IPC increases, we might be very happy with a 5-7% plus increases and a 10% jump in clocks - but that isn't necessarily what AMD means by a tock. Until we get some info on Zenver2, we are just tossing rocks into murky waters.

At this point, I'd just like to know if Zen2 has taped out. Heck, I'd settle for knowing the changes in the latest stepping of Zeppelin/Naples.

 

[Mockingbird]

Why would AMD release the same exact processor lineup twice? They likely call it "Zen" because there is no other name for new Zen revisions. AMD just differentiates them with a revision number (aka Zen 2). As noted it would make no sense to launch a Ryzen 7 1800X and then a year later launch it again as a Ryzen 7 2800X with exactly no changes. These will more than likely have the newer Zen 2 cores with higher IPC and performance. Meanwhile hopefully with a lot more focus on polishing the intra-CCX links to reduce latency.

Why not?

Intel did the same thing with Kaby Lake.

 

[Atari2600]

The L3 is in sync with the highest clocked core in its CCX.
The data fabric is in sync with the memory.

OK - thank you.

Can I rephrase my last statement.

If the the local (on die) data fabric could run at the same speed as the L3, then would that not remove the snooping delay?

The question is then integrating the wider data fabric into this.

 

[french toast]

Why not?

Intel did the same thing with Kaby Lake.

Kabylake had a different process revision, unless AMD moves to 14nm LPU ot 14nm HP i cant see the parallels.