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AMD X399 !!!!!

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nix_zero

Junior Member
Mar 19, 2017
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Snowy Owl might be APU but aside from that yes it should be a server SKU (more or less) brought to consumer just like Intel HEDT is. In the end even Summit Ridge is a server die.
The interesting bit would be if the x399 platform is unlocked and it better be or there isn't a point to it.
Chilled water anyone?:)

the idea about it being an apu comes from a march 2016 rumor that placed it on am4 - which cant route 4 memory channels signals afaik.
I dont think that was a reliable source, only the name was right.

later sources described it as 16/32 mcm on sp4 lga without any mention of the apu part which looks right on the spot for this new HEDT.
 

Ajay

Diamond Member
Jan 8, 2001
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If that is 3.1 GHz base and 3.6 GHz turbo - it going to be one heck of HEDT/Workstation CPU. Plus Quad channel RAM and, I would assume, 32 GP PCIe lanes.
 
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TimCh

Member
Apr 7, 2012
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If that is 3.1 GHz base and 3.6 GHz turbo - it going to be one heck of HEDT/Workstation CPU. Plus Quad channel RAM and, I would assume, 32 GP PCIe lanes.
I would assume 40+ PCIe lanes.

Sendt fra min SM-G928F med Tapatalk
 

IEC

Elite Member
Super Moderator
Jun 10, 2004
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I would assume 40+ PCIe lanes.

Sendt fra min SM-G928F med Tapatalk
I think that's a safe bet. The 32-core Naples processor is supposed to be 8-channel memory, 128 PCIe 3.0 lanes. A 16-core HEDT processor with quad channel support could potentially have up to 64 PCIe 3.0 lanes.
 

AtenRa

Lifer
Feb 2, 2009
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Ajay said 32 GP lanes and i believe he is right, but those will split in to two 16x pairs that will communicate via Infinity Fabric.
 
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dnavas

Senior member
Feb 25, 2017
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If that is 3.1 GHz base and 3.6 GHz turbo - it going to be one heck of HEDT/Workstation CPU. Plus Quad channel RAM and, I would assume, 32 GP PCIe lanes.
For the TDP, the turbo is actually low, but that depends on how it works (and whether and by how much it'll OC). Only one core in all 16? One in each die? One in each CCX (which is the way I woulda thunk it would have worked in the current processors)? On water you can get a 6950K over 4.5, and there's precious little difference between 16 cores at 3Ghz and 10 cores at 4.5Ghz even with perfect multithreaded scaling. Pricing will be AMD's main advantage unless clocks can rise pretty significantly without busting the power budget. Unfortunately for AMD, the pricing of the processor may well be of minimal concern if you're also sporting dual high-end video cards, dual 10 GbE, a Decklink 4k Extreme 12g (or similar acquisition card), high-end camera gear, etc. A decent pair of Schoeps can run you about what a 6950k costs....

It will be interesting to see what happens. I'm definitely interested in the possibility (both quad channel and pcie lanes), but the usefulness of higher clocks for workstation users should not be underestimated. AMD is hopefully already talking to high-end software providers (just like it is for game devs). I know Edius devs need a call :)
 

Ajay

Diamond Member
Jan 8, 2001
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I think that's a safe bet. The 32-core Naples processor is supposed to be 8-channel memory, 128 PCIe 3.0 lanes. A 16-core HEDT processor with quad channel support could potentially have up to 64 PCIe 3.0 lanes.
Unless I've missed something - for PCIe 3.0 there are 16 GP lanes, 4 lanes dedicated to NVMe and 4 lanes for the chipset. Did I miss something?
 

IEC

Elite Member
Super Moderator
Jun 10, 2004
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Unless I've missed something - for PCIe 3.0 there are 16 GP lanes, 4 lanes dedicated to NVMe and 4 lanes for the chipset. Did I miss something?
Sorry, was just going off of AnandTech's article on Naples where it mentioned 128 lanes for the 32c Naples. I might be confusing things.
 

Snarf Snarf

Senior member
Feb 19, 2015
399
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For the TDP, the turbo is actually low, but that depends on how it works (and whether and by how much it'll OC). Only one core in all 16? One in each die? One in each CCX (which is the way I woulda thunk it would have worked in the current processors)? On water you can get a 6950K over 4.5, and there's precious little difference between 16 cores at 3Ghz and 10 cores at 4.5Ghz even with perfect multithreaded scaling. Pricing will be AMD's main advantage unless clocks can rise pretty significantly without busting the power budget. Unfortunately for AMD, the pricing of the processor may well be of minimal concern if you're also sporting dual high-end video cards, dual 10 GbE, a Decklink 4k Extreme 12g (or similar acquisition card), high-end camera gear, etc. A decent pair of Schoeps can run you about what a 6950k costs....

It will be interesting to see what happens. I'm definitely interested in the possibility (both quad channel and pcie lanes), but the usefulness of higher clocks for workstation users should not be underestimated. AMD is hopefully already talking to high-end software providers (just like it is for game devs). I know Edius devs need a call :)
99% of workstation users aren't going to be overclocking. The stock ACT is going to be what really sells this platform to consumers. My estimate is they want it to clock as closely to the 1800x as possible at about ~200-225W max, 200 would be ideal.
 
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KompuKare

Senior member
Jul 28, 2009
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Unless I've missed something - for PCIe 3.0 there are 16 GP lanes, 4 lanes dedicated to NVMe and 4 lanes for the chipset. Did I miss something?
I don't think so, but hasn't this question been asked before about Naples?
In theory four Naples is Ryzen 7 (or 8 quad core CCX's), but from what we've heard in the various Naples articles (the Anandtech one and I think the ComputerBase one too) it has 128 PCIe lanes, not the 96 (16+4+4 times four) we expect from Ryzen 7.
 

imported_jjj

Senior member
Feb 14, 2009
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I am not convinced they don't have 32 lanes per die. Even if they got only 24, they could make 40 usable, 4 for M.2 and 4 for the chipset.

CPC mentions that it's ES not QS because it means that specs can change. QS tend to be what ends up in retail. Hard to say if they add XFR here too.
Aside from that, they should have more than one SKU and hopefully they are unlocked.
 

dnavas

Senior member
Feb 25, 2017
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My estimate is they want it to clock as closely to the 1800x as possible at about ~200-225W max, 200 would be ideal.
I agree, I'm sure that's what they want. In fact, I'm sure they wanted the 1800X to base closer to 4Ghz. :)
I will be surprised if they get above 1700X specs no OC. That's a fair 190W + some overhead for additional watts lost on the interposer.
As for OC, my 3.9G 1800X will pull 240W out of the wall on Prime95. Pulling 300+W off of a CPU would be something to see....
 

Ajay

Diamond Member
Jan 8, 2001
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I am not convinced they don't have 32 lanes per die. Even if they got only 24, they could make 40 usable, 4 for M.2 and 4 for the chipset.

CPC mentions that it's ES not QS because it means that specs can change. QS tend to be what ends up in retail. Hard to say if they add XFR here too.
Aside from that, they should have more than one SKU and hopefully they are unlocked.
I haven't seen a full labelled die shot of Zeppelin (or block diagram) showing all the available interfaces - so yes, there could be another 8 lanes per die that we don't know about. Where's Hans de Vires when we need him ;)
 
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HurleyBird

Platinum Member
Apr 22, 2003
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My educated guess is that Zen has 48 physical lanes. Naples has 128 lanes coming out of the CPU in a 1P configuration, but that doesn't count communication between the four dies which uses the same infinity fabric infrastructure. In a 2P configuration 64 lanes per CPU go into communicating to the other socket, or 64/4 = 16 lanes per chip. Since it wouldn't make sense to have less bandwidth for the processors within a socket compared to the processors outside of a socket, it's a logical assumption that each Zen chip in a Naples module has 16 lanes (or more) dedicated to inter-module communication.

Now why so few lanes are exposed on the consumer platform, I have no idea...

EDIT: Actually, since there's four dies to talk to in the other socket and only three other dies in the MCM, the minimum would be 12 lanes dedicated to inter-module communication, not 16 as I originally stated. So the number of physical lanes per die could be as low as, and probably is, 44.
 
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Doom2pro

Senior member
Apr 2, 2016
587
619
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My educated guess is that Zen has 48 physical lanes. Naples has 128 lanes coming out of the CPU in a 1P configuration, but that doesn't count communication between the four dies which uses the same infinity fabric infrastructure. In a 2P configuration 64 lanes per CPU go into communicating to the other socket, or 64/4 = 16 lanes per chip. It wouldn't make sense to dedicate more lanes. Since it wouldn't make sense to have less bandwidth for the processors within a socket compared to the processors outside of a socket, it's a logical assumption that each Zen chip in a Naples module has 16 lanes (or more) dedicated to inter-module communication.

Now why so few lanes are exposed on the consumer platform, I have no idea...
My guess is, if that is true it might be binning redundancy? Then again how likely are PCI-E lanes to be defective?
 
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Ajay

Diamond Member
Jan 8, 2001
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Well, that's a block diagram alright. I don't know where it came from. There are some oddities to it (i.e. the PCIe lanes and memory config).
Oh, and I think you posted two of the same pic.
 

Doom2pro

Senior member
Apr 2, 2016
587
619
106
Well, that's a block diagram alright. I don't know where it came from. There are some oddities to it (i.e. the PCIe lanes and memory config).
Oh, and I think you posted two of the same pic.
I edited it an hour ago to fix it, no idea why you are seeing the old version.
 
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moonbogg

Diamond Member
Jan 8, 2011
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On water you can get a 6950K over 4.5 :)
Say WHAT now? Over 4.5 means 4.6, and I haven't seen or heard of any Broadwell chip reliably going over 4.4 and really high voltages. I don't think people would spend $1700 on a chip that needs to run reliably and push it to the point of failure at 4.5+. A 16 core Ryzen, if priced around $1000, or maybe even a little under for shock value, would be a stunner and lay waste to the entire consumer workstation market. The Ryzen would be competing with 6950X chips @ 4.2ghz for those who OC.
Now, if we see Skylake-X chips clocking to a steady 4.6, then that would be something alright.
 
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