AMD X399 !!!!!

Page 18 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Elixer

Lifer
May 7, 2002
10,376
762
126
How do you know?
Made at gf?
When?
They have been using Samsung tech for pretty much everything, and they made a agreement with GF for them to be able to use "other fabs" which basically means, they can now use Samsung fabs to make stuff.

GF can't make Polaris & Vega & Ryzen & threadripper & Epyc (not enough production capability), so AMD will use Samsung fabs/tech.
TSMC is for consoles so far.
 
Last edited:

IEC

Elite Member
Super Moderator
Jun 10, 2004
14,323
4,904
136
Even server based cpu's seem's to be unlocked.

That sounds like a challenge... CHALLENGE ACCEPTED!

I hope EK makes a waterblock for the SP3 socket. Could actually use some water cooling for this beast...
 
  • Like
Reactions: Drazick

raghu78

Diamond Member
Aug 23, 2012
4,093
1,475
136
The roadmap with Zen at 14nm and 14nm+ , Zen 2 at 7nm and Zen 3 at 7nm+ looks promising. I think this is how it will play out.

Zen - 14nm - H1 2017
Zen - 14nm+ - H1 2018
Zen 2- 7nm - H1 2019
Zen 3 - 7nm+ - H1 2020

Hopefully AMD can get Zen clocks to atleast 4.5 Ghz or higher with 14nm+ . Thats going to be the key before Zen 2 arrives at 7nm in 2019.
 
  • Like
Reactions: Drazick
Feb 27, 2014
47
38
91
Fastest Xeon? Not so fast!
9f2d7de7-fde8-4ad7-afa4-1e3567cca038-original.jpeg
 
  • Like
Reactions: Drazick and prtskg

raghu78

Diamond Member
Aug 23, 2012
4,093
1,475
136
Fastest Xeon? Not so fast!
9f2d7de7-fde8-4ad7-afa4-1e3567cca038-original.jpeg

That linux kernel compile benchmark ran on the EPYC 32C/64T 2S system at roughly 70% of the time taken on the fastest Intel Broadwell Xeon 2S system using the E5-2699 V4

http://ark.intel.com/products/91317/Intel-Xeon-Processor-E5-2699-v4-55M-Cache-2_20-GHz.

If you consider that to cut compile time by 30% you have to be 60% faster (because a 100% faster system would cut compile time by 50%) its an impressive achievement by the 3C/64T EPYC chip within a 180W TDP. To be fair the Intel E5-2699v4 has a 145w tdp running 22 Broadwell cores at 2.2 Ghz. Even if we account for the fastest Skylake-Xeons at 28C/56T running at 2.5 Ghz which would roughly be the same TDP as the EPYC 32C/64T chip this should be a very close contest. In fact EPYC should be extremely competitive for the vast majority of server workloads which require high integer throughput performance. For FP the Skylake Xeons would be in a completely untouchable league. But for FP performance AMD is going to use Radeon Vega Instinct (4-8 GPUs per system).

I think the big disruption is going to come from AMD bringing the entire feature set - 32C/64T max core count, 8 channel memory, 2TB memory support to 1S systems. Intel has always artificially segmented the 1S and 2S markets by not selling the chips with higher core counts and memory channels in the 1S market and demanding higher prices on the higher core count chips which are only sold in 2S systems. AMD is going to basically exploit that artificial segmentation by Intel and deliver disruptive performance, core counts and memory support for 1S systems at much lower TCO. Long term AMD might force Intel to sell much higher core count chips in 1S systems and we could see 1S growing share against 2S in the overall server market.
 
Last edited:
Mar 10, 2006
11,715
2,012
126
The roadmap with Zen at 14nm and 14nm+ , Zen 2 at 7nm and Zen 3 at 7nm+ looks promising. I think this is how it will play out.

Zen - 14nm - H1 2017
Zen - 14nm+ - H1 2018
Zen 2- 7nm - H1 2019
Zen 3 - 7nm+ - H1 2020

Hopefully AMD can get Zen clocks to atleast 4.5 Ghz or higher with 14nm+ . Thats going to be the key before Zen 2 arrives at 7nm in 2019.

Didn't I say that Pinnacle Ridge would use regular Zen cores not Zen2? :)
 

raghu78

Diamond Member
Aug 23, 2012
4,093
1,475
136
Didn't I say that Pinnacle Ridge would use regular Zen cores not Zen2? :)

But you also said Pinnacle Ridge would use the same 14LPP process. I think we are looking at a better process probably like what we saw from Intel 14 to Intel 14+. The improved process should allow Zen to overcome its most important limitation - clock speeds.
 
  • Like
Reactions: Drazick
Mar 10, 2006
11,715
2,012
126
But you also said Pinnacle Ridge would use the same 14LPP process. I think we are looking at a better process probably like what we saw from Intel 14 to Intel 14+. The improved process should allow Zen to overcome its most important limitation - clock speeds.

The process sounds like it should be improved, yeah, which is good. Actually didn't I say that it would be an optimization just like Skylake -> Kaby Lake or Kaby Lake->Coffee Lake?

I wonder if people will continue to have such an unfavorable view of these types of optimizations now that it's clear AMD is doing them too (well actually AMD did it in going from Carrizo to Bristol Ridge, but when I pointed this out and said we could see something similar with Pinnacle Ridge, I was attacked). It really is a good idea.
 

blue11

Member
May 11, 2017
151
77
51
For FP the Skylake Xeons would be in a completely untouchable league. But for FP performance AMD is going to use Radeon Vega Instinct (4-8 GPUs per system).
If you run a "FP" workload 20% of the time, why would you buy 4-8 GPUs that would sit idle most of the time? What Xeon E5/SP offer is flexibility to use the same system for many types of workloads.

I think the big disruption is going to come from AMD bringing the entire feature set - 32C/64T max core count, 8 channel memory, 2TB memory support to 1S systems.
Nothing is stopping you from using E5s or SPs in 1S configurations. 8 channel memory is useless without compute* performance, which Naples lacks, given that it doesn't have AVX, let alone AVX-512. In fact, the reason there are 8 memory channels is likely because each die on the package is essentially its own independent processor, making Naples essentially a 4S configuration per package. We all know how well 4S/8S Intel systems perform (poorly). For power efficiency and latency, Naples should really only have 4 memory channels, but the lack of a unified uncore makes it impossible.

* As in throughput-computing (e.g. HPC).

Intel has always artificially segmented the 1S and 2S markets by not selling the chips with higher core counts and memory channels in the 1S market and demanding higher prices on the higher core count chips which are only sold in 2S systems. AMD is going to basically exploit that artificial segmentation by Intel and deliver disruptive performance, core counts and memory support for 1S systems at much lower TCO. Long term AMD might force Intel to sell much higher core count chips in 1S systems and we could see 1S growing share against 2S in the overall server market.
There has never been any restriction from Intel on using a 2S-capable CPU in 1S configuration.

Naples will probably see some adoption (can't do worse than 0% market share), but Skylake-SP isn't going anywhere. AMD will have to deliver a better integrated chip that covers all usage scenarios for the successor to really succeed in the datacenter market. The real problem Naples has to overcome isn't Skylake-SP, but Xeon D. For running multiple instances of lightly threaded workloads, where the MCM/CCX overhead is avoided, Xeon D offers amazing cost effectiveness.
 
Last edited:
  • Like
Reactions: Drazick

tamz_msc

Diamond Member
Jan 5, 2017
3,708
3,554
136
If you run a "FP" workload 20% of the time, why would you buy 4-8 GPUs that would sit idle most of the time? What Xeon E5/SP offer is flexibility to use the same system for many types of workloads.


Nothing is stopping you from using E5s or SPs in 1S configurations. 8 channel memory is useless without compute* performance, which Naples lacks, given that it doesn't have AVX, let alone AVX-512. In fact, the reason there are 8 memory channels is likely because each die on the package is essentially its own independent processor, making Naples essentially a 4S configuration per package. We all know how well 4S/8S Intel systems perform (poorly). For power efficiency and latency, Naples should really only have 4 memory channels, but the lack of a unified uncore makes it impossible.

* As in throughput-computing (e.g. HPC).


There has never been any restriction from Intel on using a 2S-capable CPU in 1S configuration.

Naples will probably see some adoption (can't do worse than 0% market share), but Skylake-SP isn't going anywhere. AMD will have to deliver a better integrated chip that covers all usage scenarios for the successor to really succeed in the datacenter market. The real problem Naples has to overcome isn't Skylake-SP, but Xeon D. For running multiple instances of lightly threaded workloads, where the MCM/CCX overhead is avoided, Xeon D offers amazing cost effectiveness.
AMD has historically been far more comfortable with NUMA and NUMA-like than Intel. The biggest problem in HPC is that you run out of memory much before you run out of compute. Not all workloads can be AVX accelerated either. Naples should do very well in I/O bound applications, of which there are many.
 
  • Like
Reactions: Drazick

Topweasel

Diamond Member
Oct 19, 2000
5,436
1,654
136
Also while we dont know what the MCM implementation will have on cache latency. Im not sure the original theories of the Latency causing major performance issues are founded. There have been several more pressing and more external issues that affected it's performance.

Also almost everything Professional ran fantastically on Ryzen. As long as there is a core advantage with the clock speed being closer on the server chips. I think that performance will be pretty good, more then enough to make people at least hesitate in their purchase.

Sent from my Pixel XL using Tapatalk
 

IntelUser2000

Elite Member
Oct 14, 2003
8,686
3,785
136
If you run a "FP" workload 20% of the time, why would you buy 4-8 GPUs that would sit idle most of the time? What Xeon E5/SP offer is flexibility to use the same system for many types of workloads.

Xeon will continue to have an advantage there. Intel knows that most customers don't like to transition to new platforms even if its much faster. Which is why they continue to use Xeon despite GPUs being faster. Because of that Intel keeps beefy FP units on board. Of course they know that can't be the sole defense against newcomers, which is why they have chips like Xeon Phi.*

Nothing is stopping you from using E5s or SPs in 1S configurations. 8 channel memory is useless without compute* performance, which Naples lacks, given that it doesn't have AVX, let alone AVX-512. In fact, the reason there are 8 memory channels is likely because each die on the package is essentially its own independent processor, making Naples essentially a 4S configuration per package. We all know how well 4S/8S Intel systems perform (poorly). For power efficiency and latency, Naples should really only have 4 memory channels, but the lack of a unified uncore makes it impossible.

* As in throughput-computing (e.g. HPC).

I think we shouldn't try to fit the world within one picture. There are of course scenarios where the extra memory bandwidth comes useful. Also because of those extra channels, their platform supports 33% more memory capacity than Intel as well(true against both Broadwell and Skylake). There are enough programs that aren't bound by vector unit performance but memory bandwidth.

And relatively its power efficient enough. A 32 core AMD EPYC is at 180W with 8 memory channels, 64 PCIe lanes per CPU(if used in 2P) at probably near 3GHz clock speeds. That compares extremely favorably against Skylake SP, which is 28 cores, 205W, 6 memory channels, 48 PCIe lanes and 2.5GHz clocks. Dare I say Intel might need a rumored 32 core version if they want to keep the performance halo.


Naples will probably see some adoption (can't do worse than 0% market share), but Skylake-SP isn't going anywhere. AMD will have to deliver a better integrated chip that covers all usage scenarios for the successor to really succeed in the datacenter market.

Ok, if you are definiting success as an overnight one where it starts taking 30% in the first year, sure, you are right. But that almost never happens. But it'll dent Intel's growth enough that their projections of datacenter having "high single digit growth" will disappear. And I've seen its in servers where in an extremely short time(1-2 years) 100% customers buy the latest generation CPUs. Because unlike in PCs where performance is "wanted", in servers its needed. So it can happen rapidly.
 
Last edited:
  • Like
Reactions: Drazick

Elixer

Lifer
May 7, 2002
10,376
762
126
No they won't. In the Q&A an analyst asked what foundries is AMD going to use at 7nm, the answer was GF & TSMC. And no, GF won't use Samsung 7nm because they developed their own on top of IBM's.
Hmm, seems so, but, I don't follow their logic here.
They payed GF to amend the WSA contract, and to use other fabs, and they already were using TSMC for consoles.
That would have seem to indicate that they were going to dual source GF & Samsung (since they are using the same tech) since, it really isn't possible for GF to make enough chips for them.
They have been burnt by GF new node process in the past as well, which is why I find this very odd.
Why go through all the hoops, pay GF $100 Million + the wafers they use at other foundries, if they are going to stick with a single source until 2020?
 

Ajay

Lifer
Jan 8, 2001
15,332
7,792
136
Forrest "Datacenter leadership" !

That is a radical statement and priority

Too radical, IMHO. The infrastructure that Intel and partners have put in place is huge. It will take a while for AMD to move that market significantly.
It will be interesting to see where Naples server sales are this time next year.
 

beginner99

Diamond Member
Jun 2, 2009
5,208
1,580
136
Naples should do very well in I/O bound applications, of which there are many.

And virtualization. Companies have tons of applications that have very low usage / requirements and hence virtualization is used a lot. For management purposes you still don't want to deploy all these apps on the same server so you run multiple virtual OS/servers on 1 physical server but each one of them requires RAM so you need tons of RAM but only little computing / CPU power or only in bursts. So yeah 1S naples with lots of RAM sounds like a good solution for this very common problem.
 

blue11

Member
May 11, 2017
151
77
51
Xeon will continue to have an advantage there. Intel knows that most customers don't like to transition to new platforms even if its much faster. Which is why they continue to use Xeon despite GPUs being faster. Because of that Intel keeps beefy FP units on board. Of course they know that can't be the sole defense against newcomers, which is why they have chips like Xeon Phi.*
It has nothing to do with GPUs being "faster". It makes no sense to buy extra hardware for a workload that you only run a fraction of the time. That's why you don't see datacenters being loaded up with GPUs, except in a few use cases. In addition, there are vectorized workloads that can't be run on GPUs, either because of control logic (video encoders) or memory requirements.

I think we shouldn't try to fit the world within one picture. There are of course scenarios where the extra memory bandwidth comes useful. Also because of those extra channels, their platform supports 33% more memory capacity than Intel as well(true against both Broadwell and Skylake). There are enough programs that aren't bound by vector unit performance but memory bandwidth.
I can't think of any workload that needs 300 GB/s of memory bandwidth yet isn't vectorized. You can't even access memory that quickly without using SIMD, other than through bulk memory copy.

And relatively its power efficient enough. A 32 core AMD EPYC is at 180W with 8 memory channels, 64 PCIe lanes per CPU(if used in 2P) at probably near 3GHz clock speeds. That compares extremely favorably against Skylake SP, which is 28 cores, 205W, 6 memory channels, 48 PCIe lanes and 2.5GHz clocks. Dare I say Intel might need a rumored 32 core version if they want to keep the performance halo.
If you really think Naples is 60% more energy efficient (32 * 3 / 180 vs 28 * 2.5 / 205) than Skylake, despite Zen drawing as much power as Broadwell-E, there's nothing to discuss.

Ok, if you are definiting success as an overnight one where it starts taking 30% in the first year, sure, you are right. But that almost never happens. But it'll dent Intel's growth enough that their projections of datacenter having "high single digit growth" will disappear. And I've seen its in servers where in an extremely short time(1-2 years) 100% customers buy the latest generation CPUs. Because unlike in PCs where performance is "wanted", in servers its needed. So it can happen rapidly.
I expect to see Naples fail to reach wide adoption due to extreme NUMA overhead (2S * 4 die * 2 CCX, or 16 nodes to reach parity with Intel 2S platform).
 
Last edited:

dnavas

Senior member
Feb 25, 2017
355
190
116
The roadmap with Zen at 14nm and 14nm+ , Zen 2 at 7nm and Zen 3 at 7nm+ looks promising. I think this is how it will play out.

Zen - 14nm - H1 2017
Zen - 14nm+ - H1 2018
Zen 2- 7nm - H1 2019
Zen 3 - 7nm+ - H1 2020

Hopefully AMD can get Zen clocks to atleast 4.5 Ghz or higher with 14nm+ . Thats going to be the key before Zen 2 arrives at 7nm in 2019.

Yeah, that's what the roadmap looked like to me as well. I also hope they can get to 4.5G, but 25% clock speed improvement has got to be a tricky proposition for 14 -> 14+. I also find it odd that 14 -> 14+ has no Zen bump, but the move from 7nm to 7nm+ is a Zen2 to Zen3 move. Maybe Zen2 is a bunch of architecture, while Zen3 ups the core counts?