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Discussion AMD SoC Halo series GPU discussion

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adroc_thurston said:
Or you can just quadruple the MALL with SoIC magicwaffen.
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If Medusa Halo stays with 256 bit LPDDR5, and assuming GPU will be more capable, the only way to avoid the GPU being bandwidth bottlenecked all the time would be to have massive MALL / Infinity cache.

If the both top and bottom die were to be ~250 mm2 die size, than MALL could be 256 MB and leave a plenty of room on the bottom die for other things.
 
More than a bottleneck, it is probably a case of heavily diminishing returns for a noticeable increase in costs. I remember a graph about the hit rate of the cache against the size , which returned the bandwidth multiplier factor, and while the hit rate always increase with size, the increase went rapidly down after a certain amount of cache. 256 Mbytes was never used by AMD, even in the N21 case (128). N31 used 96 Mbytes for a 384 bit bus - and both these GPUs are classes above what Halo GPU is. 7800XT uses 64 Mbytes. I don't see Halo using more than 32 Mbytes for the reasons above.
 
leoneazzurro said:
More than a bottleneck, it is probably a case of heavily diminishing returns for a noticeable increase in costs. I remember a graph about the hit rate of the cache against the size , which returned the bandwidth multiplier factor, and while the hit rate always increase with size, the increase went rapidly down after a certain amount of cache. 256 Mbytes was never used by AMD, even in the N21 case (128). N31 used 96 Mbytes for a 384 bit bus - and both these GPUs are classes above what Halo GPU is. 7800XT uses 64 Mbytes. I don't see Halo using more than 32 Mbytes for the reasons above.
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The cache hit rates reached diminishing returns in that chart, depending on resolution. and the hit rate was only in 50-60% range mostly, in 1440p and 40-50% in 4k.

It would be interesting to see the effect on actual FPS in a system that has a balanced bandwidth to GPU performance and then in one that is severely bandwidth starved.

1739870398580.png
 
I think after that graph AMD modified the caches in N3x and following, because with RDNA3 the cache size went down while they kept the efficiency at the same level. IIRC I did never see a similar graph for the RDNA3 architecture. Also, Strix Halo is not made for gaming at 4K for sure.
 
leoneazzurro said:
I think after that graph AMD modified the caches in N3x and following, because with RDNA3 the cache size went down while they kept the efficiency at the same level. IIRC I did never see a similar graph for the RDNA3 architecture. Also, Strix Halo is not made for gaming at 4K for sure.
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RDNA3 went from 256 bit max to 384 bit max, memory clocks went up as well.
 
@igor_kavinski Would like to see long idle tests to see if the rumored LPE cores are a thing (haven't seen any official material on it so it seems like it isn't true). The heavy load test is also very interesting as the M4 is supposed to have a significantly lower power limit and has a bigger battery, but is still showing less battery life. Probably the lowered scores for the AMD systems on battery is because they are reducing the power limit to have better battery life when under load whereas the Macbook doesn't lower the power limit (or not nearly as much) so performance doesn't drop significantly on battery, but then battery life takes a much bigger hit when under heavy load.
 
Hitman928 said:
@igor_kavinski Would like to see long idle tests to see if the rumored LPE cores are a thing (haven't seen any official material on it so it seems like it isn't true). The heavy load test is also very interesting as the M4 is supposed to have a significantly lower power limit and has a bigger battery, but is still showing less battery life. Probably the lowered scores for the AMD systems on battery is because they are reducing the power limit to have better battery life when under load whereas the Macbook doesn't lower the power limit (or not nearly as much) so performance doesn't drop significantly on battery, but then battery life takes a much bigger hit when under heavy load.
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Well the SoC tile is N4P so you can probably figure out why it isn't there.
Plans changed or the N3E info was complete bogus.
It does just fine vs M4 Pro when you consider the node disadvantage and the chassis being not ideal.
 
branch_suggestion said:
Well the SoC tile is N4P so you can probably figure out why it isn't there.
Plans changed or the N3E info was complete bogus.
It does just fine vs M4 Pro when you consider the node disadvantage and the chassis being not ideal.
Click to expand...

Right, seems like the leaks were wrong or, at the least, very outdated info.
 
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