AMD sheds light on Bulldozer, Bobcat, desktop, laptop plans

[Idontcare]

idontcare, would you take it as a good or bad thing to be going to immersion earlier? I had the impression it was a trick you'd keep in your back pocket for as long as possible and that dry was preferable, even if it required double-exposure (but I'm not a process guy, and I may have been mislead by marketing-disguised-as-research).

Its a matter of what you are willing to take for tradeoffs.

From Intel's perspective in 2004-2005 timeframe when they were looking at committing to a litho platform for 45nm with an eye on the risk of that platform causing delay to a node release timeline of autumn 2007 the immersion-litho integration was simply too immature and too risky.

AMD's decision makers had the luxury of having a whole extra year there for immersion-litho to mature before needing to make a risk-based decision on whether or not to lock-in the use of that technology for their 45nm which wasn't to debut till mid to late 2008.

From a technology vs. cost viewpoint the immersion litho tools are definitely more expensive, if you can get away with using cheaper dry litho tools then all the better.

The question of dual-pattern w/dry-litho vs. single-pattern w/immersion-litho definitely favors the immersion lith provided that the immersion-litho process and equipment have been tweaked and optimized to deliver "entitlement" levels of intrinsic defect-density.

But there is nothing I can write that would do the topic justice because of the inter-play between the tradeoffs in process and integration that are involved with double-pattern vs. immersion-litho.

Depending on your willingness to tolerate more or less misalignment in your design rule specs versus elevating the rework rate versus the actual design critical dimensions that you are trying to hit in the first place you can engineer your process integration and chip design to be more tolerant (at the expense of clockspeed and/or xtor density, etc) such that double-patterning is a cheaper integration approach than immersion-litho. Conversely you could strive to make the most out of immersion-litho, accept higher production costs but in pursuit of higher ASP SKUs so the gross margins work out favorably.

Either strategy has its pros and cons and neither is the wrong way to go unless you happen to make the choice for the wrong reasons (e.g. don't go immersion litho if your critical dimensions are 0.5um ).

But definitely don't go down the road of viewing Intel's use of double-pattern as a sign of inferiority versus AMD's immersion-litho...the one-year delta between the two in their respective 45nm node development milestones forced decisions there that entirely made sense when overlaid with the development timeline of immersion-litho itself.

That said, if anyone was going to be able to put immersion-litho into production in 2008 it was going to be AMD with their APM. Immersion-litho was right at the hairy-edge of manufacturable in 2008, defect density was just outrageous. Its no wonder that despite having Shanghai released in 2008 AMD waited till early 2009 to get volume ramped up enough to support releasing the higher volume PhenomII consumer parts.

 

[cbn]

Depending on your willingness to tolerate more or less misalignment in your design rule specs versus elevating the rework rate versus the actual design critical dimensions that you are trying to hit in the first place you can engineer your process integration and chip design to be more tolerant (at the expense of clockspeed and/or xtor density, etc) such that double-patterning is a cheaper integration approach than immersion-litho. Conversely you could strive to make the most out of immersion-litho, accept higher production costs but in pursuit of higher ASP SKUs so the gross margins work out favorably.

So immersion litho can produce faster and more dense chips? (with the possible penalty of higher production costs).

If so this will be a good thing for AMD considering they seem to want to focus on energy efficiency at larger node sizes.

 

[cbn]

I have seen details of Llano (on twitter) being a Fusion of 32nm Phenom II and IGP.

Are non-fusion 32nm Phenom IIs planned for current AM3 sockets?

 

[Idontcare]

So immersion litho can produce faster and more dense chips? (with the possible penalty of higher production costs).

No, not quite like that. Single-pattern immersion litho and double-pattern dry-litho can be viewed as simply different means towards the same end.

Immersion litho doesn't "produce" anything per say, it enables engineering margin in the pursuit of printing lines within certain tolerances. Depending on the target dimensions and the allowed manufacturing tolerances you have what is generically referred to as "process variation".

Process variation with immersion-litho is capable of being intrinsically lower than that of double-pattern litho owing to the misalignment that occurs between successive patterning steps.

What you do with your intrinsically lower process variation at litho is a matter of your priorities. If you want to leverage that advantage into targeting ever smaller design rule features to increase density and circuit FOM (figure of merit, like switching time + line latency, etc) then so be it. Alternatively you might leverage that advantage into slightly less aggressive design rule targets and instead pursue higher cycle time (both in terms of the tool and process time per wafer as well as lower rework rates) so that your capital utilization is higher and functional yields are higher.

Both double-pattern and immersion-litho are capable of enabling the production of equally dense design rules (the same end), but depending on the integration approach the journey to getting there can have a different cost structure as well as different risk-to-production profile.

If you were looking at needing a HVM (high volume manufacturing) litho solution for late 2007 to early 2008 the immersion-litho path represented unacceptably high risk versus pursuing an integration pathway using double-pattern dry litho. A year later and the risk profile changes enough to favor the immersion litho path.

Other than Intel I don't know of any IDM/foundry using double-pattern dry litho at 40/45nm, they all use immersion litho for their most critical dimension patterning steps, but then again Intel was the only one bringing 45nm to HVM in late 2007 and early 2008.

 

[Idontcare]

I have seen details of Llano (on twitter) being a Fusion of 32nm Phenom II and IGP.

Are non-fusion 32nm Phenom IIs planned for current AM3 sockets?

There's nothing on the official PR slides and public roadmaps but looking at how many different SKU's AMD supports between the X2/X3/X4 variants of both Phenom II and Athlon II I think we certainly have every reason to expect AMD to release a non-Fusion PhenomIII/AthlonIII something or other at some point on 32nm.

They've already invested the expense of shrinking the K10 architecture to 32nm, it is a relatively smaller cost adder at that point to tapeout additional 32nm derivatives of cut-and-paste core combos.

 

[IntelUser2000]

Well, certainly Intel isn't planning 2 core sans IGP part(Clarkdale) even though it would be easier than Fusion to create such a part, is it hard to expect AMD would do otherwise? On a low end where Llano will be targeted at, IGP is pretty important.

Unless they decide to branch in another direction - charge more for the IGP cores, not just $5 more but $30-40.

 

[cbn]

There's nothing on the official PR slides and public roadmaps but looking at how many different SKU's AMD supports between the X2/X3/X4 variants of both Phenom II and Athlon II I think we certainly have every reason to expect AMD to release a non-Fusion PhenomIII/AthlonIII something or other at some point on 32nm.

They've already invested the expense of shrinking the K10 architecture to 32nm, it is a relatively smaller cost adder at that point to tapeout additional 32nm derivatives of cut-and-paste core combos.

If I could eventually get a 32nm 12mb L3 cache Phenom II/III quad core for AM3 I would be happy. This would be a good swap for my current ATX rig.

I even wonder if the extra L3 cache being closer to the AM3 cores would be a benefit compared to Core i9? (On Gulftown with 2 cores deactivated or not being used some of the L3$ would be farther away)

But you are right. Looking at the Current AMD Roadmap I don't see anything involving 32nm until 2011. I just naturally assumed they would release old architecture on the new node first.

 

[Idontcare]

Well, certainly Intel isn't planning 2 core sans IGP part(Clarkdale) even though it would be easier than Fusion to create such a part, is it hard to expect AMD would do otherwise? On a low end where Llano will be targeted at, IGP is pretty important.

Unless they decide to branch in another direction - charge more for the IGP cores, not just $5 more but $30-40.

I thought they were, for Apple.

 

[IntelUser2000]

Oh wait, Clarkdale has a reason for doing that. The other die also contains the memory controller and the PCI Express controller. Without it, it would not work at all.

I guess they can disable the IGP for Apple, but with Nvidia Intel chipsets being canned, what's the point? Besides, if you plug in a discrete card, the IGP would stop working anyway.

With Llano? Maybe, but IMO more likely not.

 

[cbn]

JFAMD,

You mentioned improved "scheduling" possibly being more important that individual core strength earlier.

How well would this improved task scheduling scale at lower core counts? At the dual module (quad core) level?

Or is this something that really only shines at really high core counts?

 

[JFAMD]

The more cores you have, the more critical scheduling is.

 

[Idontcare]

Are we talking hardware-level scheduling (as in instruction scheduling) or software-level scheduling (as in thread scheduling)?

 

[JFAMD]

Thread scheduling. I don't know about HW scheduling.

 

[Idontcare]

Is bulldozer taking more of a controlling position on thread scheduling or is it still at the mercy of the OS and AMD is working with Microsoft and the linux community to get a more sophisticated thread-scheduler in place?

 

[JFAMD]

Can't say, don't know.

We do work closely with all of the OS vendors.

 

[evolucion8]

Since most code uses int processing and not FPU, I don't see AMD approach as a bad one, in the end, heavy FPU code should run with the GPU inside of the future AMD Fusion. And slowdowns in SMT code should be less recurrent compared to Hyper Threading.

 

[cbn]

http://www.channelregister.co.uk/2009/12/14/amd_bulldozer_preview/page2.html

16 core @ 55 watt, 75 watt and 105 watts?

What kind of TDPs can we expect for the the smaller Desktop Bulldozers?

 

[Idontcare]

http://www.channelregister.co.uk/2009/12/14/amd_bulldozer_preview/page2.html

16 core @ 55 watt, 75 watt and 105 watts?

What kind of TDPs can we expect for the the smaller Desktop Bulldozers?

As it turns out, this sharing of components across the cores impacts performance. Fruehe says that a pair of Bulldozer "cores" will yield about 1.8 times the performance of what a single, whole core would have.

That should be "1.8 times the performance of what two independent cores would have"...

 

[jvroig]

16 core @ 55 watt, 75 watt and 105 watts?

Are these the current TDPs of the six-core Istanbul opterons? If so, and those are the same TDP targets for their 16-core Interlagos, that's just amazing. Then again, that says nothing about performance, but I'm assuming they wouldn't be putting out too little performance - after all. this is still more than a year away, they probably wouldn't be clocking their 16-core monster at <1Ghz just to remain @ 55w.

What kind of TDPs can we expect for the the smaller Desktop Bulldozers?

Wouldn't that depend on how many cores they will offer and the clockspeed? Since we don't know both, we probably can't tell. That's almost two years away, so hard to tell. Interlagos will come out first, then speculations about desktop Bulldozer will proably abound or be leaked or previewed, since AMD releases for the server space first.

 

[jvroig]

That should be "1.8 times the performance of what two independent cores would have"...

No, he said "cores", so he meant "one Bulldozer module" when he said "two Bulldozer `cores`" in the article. So 1 Bulldozer module (a.k.a. 2 Bulldozer cores) will be "1.8 times the performance of what a single, whole core would have".

If you say "1.8 times the performance of what two, independent cores would have", then that would be 1.8 * 2 = 3.6x. So one module will have 3.6x the performance of a single core, in other words, one module will rival a quad-core.

 

[cbn]

Wouldn't that depend on how many cores they will offer and the clockspeed? Since we don't know both, we probably can't tell. That's almost two years away, so hard to tell. Interlagos will come out first, then speculations about desktop Bulldozer will proably abound or be leaked or previewed, since AMD releases for the server space first.

I asked that question because I am wondering if they will be able to get smaller versions (fewer modules) of this chip into either Xbox 3 or mini-dtx.

The real wild card in my newbie opinion will Google OS. If that eventually ends up as a decent gaming platform a lot of things could change.

Low cost OS (Google) + Low cost platform (mini-dtx) seems like a good match to me.

 

[Martimus]

That should be "1.8 times the performance of what two independent cores would have"...

I think the original quote was correct. Imagine if it did 80% more than two full cores with less than two full cores. While it may get a performance gain in some situations due to possibly less latency, I would expect two fully functioning cores to have superior performance to a hybrid 1/2 core system like the BD module.

I think you just meant "0.9 times the performance of what two independent cores would have". I only posted to clear up any confusion and to make sure I removed any doubt that I am an idiot. I have the foot in the mouth feeling lately, and I decided to just go with it.

 

[Idontcare]

yeah you guys are right, I read it wrong

 

[cbn]

When AMD mentions the 2.1 GHz 8 core Bulldozer being 60-80&#37; faster than Thuban are they are talking about the 2.8 Ghz hexcore?

If so that is quite an improvement in IPC.

In fact, I am beginning to wonder if AMD will achieve what I was hoping for in post #239:

http://forums.anandtech.com/showpost.php?p=28983632&postcount=239

and post #243:

http://forums.anandtech.com/showpost.php?p=28983947&postcount=243

 

[jvroig]

When AMD mentions the 2.1 GHz 8 core Bulldozer being 60-80&#37; faster than Thuban are they are talking about the 2.8 Ghz hexcore?

If so that is quite an improvement in IPC.

I'm pretty sure that is what they meant, and yes, one of their highlights for Bulldozer was a much improved Int crunching power. I believe Johan made sure to mention that in his Bulldozer article for enterprise IT at AnandTech (the real site, of course, not here). I haven't done the math yet, so I can't say how impressive the actual IPC gains are (adding two cores (going from 6 core to 8 core) is already a ~33% gain (perfect scaling assumed) so I'm not sure how much IPC improvement (per core) is needed to get the additional 30-50% gain), but it has been clearly mentioned as one of the "wins" Bulldozer brings to the table aside.