I was reading the detailed papers that i have not read and i found new details:
- The statistics is used to construct a voltage frequency temperature table (10 bit per entry, 10x8 entries, encoding the optimum voltage), so that the statistics must not be performed too often, because the table includes more operating points. The statistics calculate gaussians for various type of circuits and include guard bands. The circuit replica is checked for the results delay and the "near miss" are counted. Near miss are results that are arrived just in time and would be too late if only the Vcore is slightly lower.
- There is one table for each core so the Vcore is calibrated for each and so die inhomogeneity is taken into account (it is possible to have different Vcore for each core, see DLDO specification)
This is why I asked for the table details.
There's always a table, and usually it will be accessible... Overwriteable
How often it is updated and what exact conditions it needs for an upshift/downshift are key.
K10Stat Dev needs to come out of hiding
Different VID/FIDs and power planes have been on AMD CPUs for a long time.
Typically, FPUs are littered with the highest number and most sensitive digital sensors, as it's a region that heats up quicker than any, hence a single point of failure that is well monitored.
But this region is also typically far hotter than the rest of the chip. So I'm wondering if anything has been done to mitigate this.
30W for a core should be perfectly allowable as it has been previously, providing leakage currents are well controlled.
There will always be a priority weighting for such table based schemas, and VID bandings are usually inflexible and strict, being too safe on the side of caution (causing more heat that necessay).
I'll have a full read of the papers now.
Sent from HTC 10
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