AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[itsmydamnation]

but if they maintain around the same number of pipeline stages ( i would expect simlar) they should still be able to clock high (assuming you can keep it cool). CON cores are never clock limited by the Core. On the other hand GCN has a very short pipeline (much shorter then Nvidia's) and is potentially a big part of the clocking limiting equation.

Remember a lot of quite wide cores (A57,A72,Moongoose etc) run on mobile platforms in the 2ghz range at a way lower power budget per core then 180watt/32core.

 

[mikk]

Google translation from Benchlife:

Back Zen architecture "Summit Ridge" section, if there is not much else, then, AMD will be on sale in February 2017 related to the motherboard and processor, now know, "Summit Ridge" platform corresponds to the wafer 3, respectively is "X370", "B350" and the low-level "A320."

https://benchlife.info/update-for-intel-kaby-lake-and-amd-summit-ridge-09112016/


On sale in February 2017, but this can be delayed further. The chipset naming reminds me of Intels, somehow expected that AMD tries to copy Intels. I guess we will see Zxxx or Hxxx when Raven Ridge comes.

 

[The Stilt]

Hmm, I hadn't thought of that. It would certainly make things harder, 4x200 mm2 dies at CPU yield is not going to be cheap. They might still want to do 4x4C simply because of being able to put it into two sockets.

Do all of the dies have to have the same number of cores?

AFAIK all dies in all CPUs must have: same number of cores in same number of CCXs and same amount of L3.

 

[Abwx]

There's no such 'v^2 law'. You guys are arguing over nothing.

Lol, denial of laws of physics..

https://en.wikipedia.org/wiki/MOSFET

The chipset naming reminds me of Intels, somehow expected that AMD tries to copy Intels.

Numbers are patented by Intel.??.

Anyway that s a ridiculous statement, it s not like Intel didnt use the term HD4000, just like AMD s GPUs, but hey, that doesnt count...

Indeed that s in line with the rest of your post, that i didnt quote, and where you re just expressing your hope that Zen could be eventually delayed, to summarize you dont put your hopes on Intel improving their design but on their competitor failing to deliver on time, it s much telling about your mentality, not that you re alone, i often read here such kind of "opinion" and other wishfull thoughts..

 

[lolfail9001]

Lol, denial of laws of physics..

At least read articles you're quoting:

Modern MOSFET characteristics are more complex than the algebraic model presented here

I'll keep the part where you skip the connection between current in ohmic mode and switching frequency, on you.

 

[Abwx]

At least read articles you're quoting:

I'll keep the part where you skip the connection between current in ohmic mode and switching frequency, on you.

No need to go in the details, and i skip nothing since the linear part is what matters as the device is in its linear region during the rising and falling hedges, and if it s not the case it means that your device is not adequate..

Neverless i see here that to downplay AMD some people go as far as negating the very laws that govern fet s behaviour and the way they are used in switching devices.

 

[Glo.]

No need to go in the details, and i skip nothing since the linear part is what matters as the device is in its linear region during the rising and falling hedges, and if it s not the case it means that your device is not adequate..

Neverless i see here that to downplay AMD some people go as far as negating the very laws that govern fet s behaviour and the way they are used in switching devices.

The problem is that whole discussion started from you believing that 95W APU will have 32 cores clocked at 1.44 GHz. Nobody here is downplaying AMD. Everybody is trying to tell you that there is no way in the world that it will be possible to achieve. For two reasons. First and the most important is that it is only your belief. Second, is that you forget to account things that do not scale with core clocks, but increase the power consumption of the CPU regardless.

I do not like stating that AMD will not be able to do something, or they will not come up with architecture that can compete with Intel. But your assumption about that APU is beyond ridiculous. It would be biggest jump in efficiency we have ever seen. Not even Intel is able to get this level of efficiency. All of the 22 core Broadwell-EP CPUs have 135W TDP at least. That is why it is safe to assume that that 32 core APU from AMD will have at least 150W TDP.

 

[lolfail9001]

No need to go in the details, and i skip nothing since the linear part is what matters as the device is in its linear region during the rising and falling hedges, and if it s not the case it means that your device is not adequate..

Neverless i see here that to downplay AMD some people go as far as negating the very laws that govern fet s behaviour and the way they are used in switching devices.

Look, my EE knowledge is lacking, as most likely does yours.
What i do know though, is that pseudo-random formulae on wikipedia are secondary to numbers. And numbers are known, frequency does not rise as square of voltage in any real life system discussed on these forums. Dynamic power does, however (and funnily that is school grade physics in hindsight). Frequency... not really. So acting all smug does not help you any here.

But yes, Glo. is right, it's mostly about your fairly ridiculous conclusion about 32C having 95W as upper bound

 

[Abwx]

The problem is that whole discussion started from you believing that 95W APU will have 32 cores clocked at 1.44 GHz. Nobody here is downplaying AMD. Everybody is trying to tell you that there is no way in the world that it will be possible to achieve.

That s a belief due to some people misleading others and succeding in doing so, hence why almost eeverybody keep believeing that it s not possible..

For two reasons. First and the most important is that it is only your belief.

And my belief is based on laws of physics that are invariable and are verifiable on existing CPUs..

Second, is that you forget to account things that do not scale with core clocks, but increase the power consumption of the CPU regardless.

You can check in real world and you ll see that what i m stating is the reality.

As an easy exemple a FX8350 at stock use 100W on Fritzbench, a FX8370E use 65W, that s measurements made by Hadware.fr, now do the math, the clock ratio is 40/33 = 1.21, squaring yield 1.46 and 65W x 1.46 = 95W, you can see that it s very accurate, and better than the apparent 5W error since the two CPUs have not exactly the same voltage/frequency curves, the curve of the 8350 in respect of the 8370E is very slightly shifted by a 2.5% voltage delta..

I do not like stating that AMD will not be able to do something, or they will not come up with architecture that can compete with Intel. But your assumption about that APU is beyond ridiculous. It would be biggest jump in efficiency we have ever seen. Not even Intel is able to get this level of efficiency. All of the 22 core Broadwell-EP CPUs have 135W TDP at least. That is why it is safe to assume that that 32 core APU from AMD will have at least 150W TDP.

It s not an APU, and btw, it wouldnt be a big jump since it should be at best 10% more efficient in FP than Intel s BDW, so how could it be a huge jump in respect of what is possible and aleady existing technically..?.

 

[Abwx]

Look, my EE knowledge is lacking, as most likely does yours.

You should had kept only the first half of your sentence, you would had made a right point..

What i do know though, is that pseudo-random formulae on wikipedia are secondary to numbers.

That s not a pseudo random formulae, what is random is your understanding of its meaning wich can be summarized by the current increasing as a square of voltage, you can check with any CPU, increasing voltage by a ratio x will increase frequency by a ratio x^2, that s while the CPU in its normal operating areas.

And numbers are known, frequency does not rise as square of voltage in any real life system discussed on these forums.

It s tiring at the end, take any CPU in its usefull range and do the maths, you are deseperatly negating the formulae above and what can be measured on current CPUs, you want me to show an exemple so that everyone can see that you are trying to mislead people here..?..

But yes, Glo. is right, it's mostly about your fairly ridiculous conclusion about 32C having 95W as upper bound

That s rididculous for whom ignore basic laws, or eventually has an agenda and is hence hell bent on downplaying the possibility that AMD could seriously rival Intel, actually that seems the concern of most "skeptical" people by here and certainly the reason of their presence in this thread...

 

[F-Rex]

The problem is that whole discussion started from you believing that 95W APU will have 32 cores clocked at 1.44 GHz. Nobody here is downplaying AMD. Everybody is trying to tell you that there is no way in the world that it will be possible to achieve. For two reasons. First and the most important is that it is only your belief. Second, is that you forget to account things that do not scale with core clocks, but increase the power consumption of the CPU regardless.

I do not like stating that AMD will not be able to do something, or they will not come up with architecture that can compete with Intel. But your assumption about that APU is beyond ridiculous. It would be biggest jump in efficiency we have ever seen. Not even Intel is able to get this level of efficiency. All of the 22 core Broadwell-EP CPUs have 135W TDP at least. That is why it is safe to assume that that 32 core APU from AMD will have at least 150W TDP.

AFAIK broadwell-ep is not clocked at 1.44GHz.
Some guys hère keep saying 14nmLPP is a low power process not suited for hPerformance CPU. But according to thèse guys, low power is also not achievable on this process. Despite s820 & high end exynos being fabbed on it.
At the end of the day, i don't see why 95w would not be achievable @1,44GHz.

 

[Glo.]

Ok, it may be possible. But will it be what we will see in he real world, in the end?

That is the point, that you, Abwx, ignore.

 

[lolfail9001]

It s tiring at the end, take any CPU in its usefull range and do the maths, you are deseperatly negating the formulae above and what can be measured on current CPUs, you want me to show an exemple so that everyone can see that you are trying to mislead people here..?..

"Useful" range is undefined. But sure, hardware.fr article you cite (by the way, it does not have numbers you claim it has, but that's for dessert): on 8370E we have 3.3Ghz on 1.032Vcore, 4Ghz on 1.188Vcore, yet if you were right it would be 4.3Ghz on 1.188Vcore or 4Ghz on ~1.136Vcore. Considering that it is area right inside it's operating frequencies, it's pretty useful

You should had kept only the first half of your sentence, you would had made a right point..

So far you've done nothing to demonstrate that.

As an easy exemple a FX8350 at stock use 100W on Fritzbench, a FX8370E use 65W, that s measurements made by Hadware.fr, now do the math, the clock ratio is 40/33 = 1.21, squaring yield 1.46 and 65W x 1.46 = 95W, you can see that it s very accurate, and better than the apparent 5W error since the two CPUs have not exactly the same voltage/frequency curves, the curve of the 8350 in respect of the 8370E is very slightly shifted by a 2.5% voltage delta..

http://www.hardware.fr/focus/99/amd-fx-8370e-fx-8-coeurs-95-watts-test.html
This article, correct? I don't see 100W for 8350 or 65W for 8370E anywhere in this article.
What i do see is 120W for 8350 and 72W for 8370E on unknown frequencies for latter . Thanks though, this article provided all evidence required to disprove your point about voltage/frequency.

 

[bjt2]

Good Afternoon.

This is my first post in this board, so i'll start saying Hello to everyone.

I have some consideration about a 32 core Zen CPU clock and TDP.

I start from the Apple A9 and A9X SoCs, with allegged TDP of 3W and 5W respectively.

They have 2 ARM core at 1.85GHz and 2.26GHz respectively.

According to Wikipedia, the Apple A9 ARM core has 4 INT pipelines, 2 memory pipelines and 3 FPU pipelines.

So it's comparable with Zen (more on later: I know that Zen has 4 FPU pipelines)

The pipeline stages are 16. According to a paper linked here (i think, but I follow many Zen threads) by Dresdenboy, the Zen int pipeline has 19 stages. So Zen should drain less than the A9 at the same frequency.
Let's assume that this compensates the 4 vs 3 FPU pipelines.

Let's assume that the 5W of the Apple A9X are used by the 2 ARM cores (there is also a GPU, the NB and SB).

32 such cores will drain 5*16=80W at 2.26 GHz.

So why a 32c Zen at 1.44GHz can not drain 95W?

Regards.

 

[jpiniero]

So why a 32c Zen at 1.44GHz can not drain 95W?

GloFo.

 

[Abwx]

Ok, it may be possible. But will it be what we will see in he real world, in the end?

That is the point, that you, Abwx, ignore.

I didnt say that such a lowly clocked 32C would be released (although why not..) but since this was discussed i wanted to point that people talking of 180W about such a theorical SKU are just spreading fud, because if such power would be required for this fequency and core count then 45W would be required for a 1.44GHz 8C Zen, and 180W would be necessary to clock it at 2.88GHz, on light of those numbers i hope that you realize the extent of the fud that is rolling by here..

Anyway since AMD stated that 8C at 3GHz fit in a 95W envelloppe we can make all extrapolations that we want and be sure to be right, assuming that we follow said basic physics laws of course.

We know now that at 95W they can make a 16C/2.15GHz or a 32C/1.5GHz, from here they have to increase the TDP, surely that they get up to 115W wich would allow 10% higher frequency..

 

[bjt2]

GloFo.

The apple A9 is made on the 14nm FF process of Samsung/GloFo (and 16nm TSMC but they are similar in consumtion as for Apple)

 

[jpiniero]

The apple A9 is made on the 14nm FF process of Samsung/GloFo (and 16nm TSMC but they are similar in consumtion as for Apple)

It's not the same, GloFo's process is a bastardization of the Samsung 14FF node.

 

[bjt2]

It's not the same, GloFo's process is a bastardization of the Samsung 14FF node.

The process used by Zen is the low power/high density. Why the Apple A9 would be made on another process?

 

[lolfail9001]

Good Afternoon.

This is my first post in this board, so i'll start saying Hello to everyone.

I have some consideration about a 32 core Zen CPU clock and TDP.

I start from the Apple A9 and A9X SoCs, with allegged TDP of 3W and 5W respectively.

They have 2 ARM core at 1.85GHz and 2.26GHz respectively.

According to Wikipedia, the Apple A9 ARM core has 4 INT pipelines, 2 memory pipelines and 3 FPU pipelines.

So it's comparable with Zen (more on later: I know that Zen has 4 FPU pipelines)

The pipeline stages are 16. According to a paper linked here (i think, but I follow many Zen threads) by Dresdenboy, the Zen int pipeline has 19 stages. So Zen should drain less than the A9 at the same frequency.
Let's assume that this compensates the 4 vs 3 FPU pipelines.

Let's assume that the 5W of the Apple A9X are used by the 2 ARM cores (there is also a GPU, the NB and SB).

32 such cores will drain 5*16=80W at 2.26 GHz.

So why a 32c Zen at 1.44GHz can not drain 95W?

Regards.

Well, i could start with note that Zen is x86 so it has added cost of instruction decoding compared to any ARM core.
But the main problem here is that we know that Naples has all the uncore material of 4 Summit Ridge dies, that is, ridiculous amount of IO. And that stuff requires power as well. And there is very little evidence to support it being entirely bound to cores frequency power-consumption wise.

I didnt say that such a lowly clocked 32C would be released (although why not..) but since this was discussed i wanted to point that people talking of 180W about such a theorical SKU are just spreading fud, because if such power would be required for this fequency and core count then 45W would be required for a 1.44GHz 8C Zen, and 180W would be necessary to clock it at 2.88GHz, on light of those numbers i hope that you realize the extent of the fud that is rolling by here..

Or the entire 1500-3000 range is all on low voltage (Low Power Plus, heh), with explosion in power consumption afterwards. Actually, never mind, i would not be surprised if quad core Summit Ridge actually has similar frequencies to 8 core. Then we can easily conclude that uncore is about 35W. Times 4, it's about 140. And in ironic twist of fate, both of us may just be right: Naples can't be below 150W( below 170W, in fact) TDP but 32 Zen cores @ 1.44 may actually consume as much as or less than 8 Zen cores @ 2.8. Not that we can extrapolate anything of use from this, but hey.

Damn, speculations are fun.

 

[bjt2]

Well, i could start with note that Zen is x86 so it has added cost of instruction decoding compared to any ARM core.

Zen has the uop cache, that reduces the consumption by the cache hit rate (I think between 50% and 80%) and AFAIK the A9 no, but I can be wrong... Anyway, I remember the A9 having 6 decoders and the ARM ISA, in the 64 bit incarnation, is not that simple...

But the main problem here is that we know that Naples has all the uncore material of 4 Summit Ridge dies, that is, ridiculous amount of IO. And that stuff requires power as well. And there is very little evidence to support it being entirely bound to cores frequency power-consumption wise.

Also the uncore can be downclocked, especially if the cores are low clocked. The integrated SB draw less than 6W on 28nm for bristol ridge and I think that someone will be fused off on the dices. Also the NB has not the L3 cache anymore.

Then we can easily conclude that uncore is about 35W. Times 4, it's about 140. And in ironic twist of fate, both of us may just be right: Naples can't be below 150W( below 170W, in fact) TDP but 32 Zen cores @ 1.44 may actually consume as much as or less than 8 Zen cores @ 2.8. Not that we can extrapolate anything of use from this, but hey.

Damn, speculations are fun.

35W for the NB+SB would be awful... No low power versions, no tablet versions...
Zen was projected from 4W to 95W... How come they obtain this if the NB+SB draw 35W?
Evidently the consumption can be scaled down and anyway I doubt that the maximum consumption is 35W... It would be a tragedy... And bristol ridge that is on 28nm? The NB and SB draw 70W?

 

[lolfail9001]

Zen has the uop cache, that reduces the consumption by the cache hit rate (I think between 50% and 80%) and AFAIK the A9 no, but I can be wrong... Anyway, I remember the A9 having 6 decoders and the ARM ISA, in the 64 bit incarnation, is not that simple...



Also the uncore can be downclocked, especially if the cores are low clocked. The integrated SB draw less than 6W and I think that someone will be fused off on the dices. Also the NB has not the L3 cache anymore.



35W for the NB+SB would be awful... No low power versions, no tablet versions...
Zen was projected from 4W to 95W... How come they obtain this if the NB+SB draw 35W?
Evidently the consumption can be scaled down and anyway I doubt that the maximum consumption is 35W... It would be a tragedy... And bristol ridge that is on 28nm? The NB and SB draw 70W?

I doubt it as well, but it was made entirely off of obviously faulty assumption that 65W and 95W Summit ridge 4c and 8c share frequencies entirely.

Also, obviously nothing stops one from downclocking or fusing parts of it entirely, if it is actually nearly as bad as bad math suggests.

Also, just saying, but Z170 has higher TDP than Z87.

 

[bjt2]

I doubt it as well, but it was made entirely off of obviously faulty assumption that 65W and 95W Summit ridge 4c and 8c share frequencies entirely.

Also, obviously nothing stops one from downclocking or fusing parts of it entirely, if it is actually nearly as bad as bad math suggests.

Also, just saying, but Z170 has higher TDP than Z87.

These are ES... The TDP aren't comparable... Also even in the old day of externals NB and SB, with long traces and 90nm or worse process they would not draw 35W combined...

And the Z170 & c are external chipset... The communication overhead is enormous... THis is the reason to have true SoC nowadays...

 

[deasd]

According to Wikipedia, the Apple A9 ARM core has 4 INT pipelines, 2 memory pipelines and 3 FPU pipelines.

So it's comparable with Zen (more on later: I know that Zen has 4 FPU pipelines)

The pipeline stages are 16. According to a paper linked here (i think, but I follow many Zen threads) by Dresdenboy, the Zen int pipeline has 19 stages. So Zen should drain less than the A9 at the same frequency.

It's not comparable, because x86 is different. x86 has too much complex logic to translate complex instruction set into simple instruction set thus consume a lot more than any other ISA. As you can see x86 core is quite big when compare to ARM.

Discussion about frequency of an architecture is not difficult, but it would be quite unrealistic when comes to a specific product. Zen ES @ 32core start from 1.4Ghz according to Geekbench might be a hint, but there's nothing about its TDP.

If we refer to ES 8core @ 2.8Ghz w/ 95w TDP, I would just guess the ES 32core @ 1.4Ghz has around 115-125w TDP.

 

[bjt2]

It's not comparable, because x86 is different. x86 has too much complex logic to translate complex instruction set into simple instruction set thus consume a lot more than any other ISA. As you can see x86 core is quite big when compare to ARM.

Discussion about frequency of an architecture is not difficult, but it would be quite unrealistic when comes to a specific product. Zen ES @ 32core start from 1.4Ghz according to Geekbench might be a hint, but there's nothing about its TDP.

If we refer to ES 8core @ 2.8Ghz w/ 95w TDP, I would just guess the ES 32core @ 1.4Ghz has around 115-125w TDP.

As I stated above, A9 has six decoders and no uop cache. This should more than compensate the x86 complexity. Moreover A9 pipeline lenght is 16 stages versus 19 of Zen. So Zen has a lower FO4 delay and thus at same frequency requires less Vcore and draw much less power...