AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[bjt2]

Erm, Tahiti at 925 MHz consumed 163W of power according to TPU numbers, and you forget that Tahiti, with 6 GB of VRAM is in FirePro D700 in Mac Pro. And that GPU has clocks of 5400 MHz on Memory, 850 MHz on core, and TDP of 129W.

On the other hand, 125W consumes RX 470 while having 50% higher core clock(1206 MHz). And most of the power consumed is on the memory side, rather than the GPU.

The GPU die for D700 consumes 70W of power while having 850 MHz core clock.
GPU die for RX 470 can consume around 85-90W, while having 1206 MHz core clock.

This is VERY off-topic.

We have so a +50% clock with about the same power...
But all of you keep saying that zen will have lower clocks than XV...
Fine...

 

[lolfail9001]

We have so a +50% clock with about the same power...
But all of you keep saying that zen will have lower clocks than XV...
Fine...

We have pretty much a direct statement from AMD that Zen will have lower clocks than XV in the fact that ES is only 3.2 single core boost and the fact that AMD had to downclock(!) 6900k for their demo. Will the rumored half a year until release be enough to upclock it to XV levels? We'll see. That recent benchlife rumor makes it look way too reminiscent of Polaris now (first a fairly favorable demo against competition, even if with sketchy rules) then half a year wait.

 

[KTE]

Linear scaling for the Vcore means cubic scaling for power, because P~V^2*f (P=V^2*I and I=kf)
Maybe this is what he meant.

If V is linear between 2 and 3 GHz, then at 2GHz the CPU draw 1.5^3=3.375 less than 3GHz... Less than 1/3. Supposing that an 8c Zen draw 95W at 3GHz we have:

A 32c at 2GHz should draw 95/3.375*4=112W...

At 180W we can have 32c at 2*(180/112)^(1/3)=2.34GHz...

Please see Transmeta's paper on processor and power variations: http://www.design-reuse.com/article...ent-leakage-control-process-compensation.html

Process/processor Vth and the SPICE Box is key to the scaling characteristics of the end product, and it's power.


P rarely equates to v^2*f below 45nm.

Yes, P equates to V^1.7 to V^3 for general roughing, depending on the process and parametric choices, and where in the curve that Vdd falls... *f

Unless you know the k*C values, in which case you have a more accurate profiling with k*C*v^n where n=the relevant voltage factor.

C differs much more than it used to at the smaller nodes while k is a process dependent constant.

For approximations with much data, in terms of IVB, for instance, P scales at ~V^1.75*f until you hit 4.5GHz -- the dead point of diminishing scaling.

Lastly, the Vdd values used in end shipping products is not determined by what we users find in OC/UC, but process wide averaged testing using thousands of samples that fit the median Gaussian distribution (bell curve). End user testing cannot account for this. This Vdd is again linked to the above unknowns/yields.

So we end up with two major factors yet unknown.

Eg. AMD had Agena 65nm running no lower than1.35V for 2.2GHz.

We users could get 1.15-1.20V.

Penryn was even more ridiculous.

However, Agena needed, end user, 1.5V to go >2.35GHz. It was pumped to the pipe in launch. This was a processor designed for 3GHz.

Due to the process/processor parametrics, scaling, from a DT users perspective, was not there.

This is something you cannot approximate until you know the process with some end product data.

Three major unknowns kill off these power and frequency scaling approximations. Until we have a starting datapoint.

The way it is looking with Zen, and this is just a guesstimate that could be completely wrong, it would be easier for AMD to do a Magny Cour than a Piledriver at this stage. Hence my tentative agreement with Abwx's end comment.

Sent from HTC 10
(Opinions are own)

 

[The Stilt]

You might be looking at a significantly tweaked Polaris in H1 2017 as GF 14LPP seems to be pretty horrible at the moment in terms of process variation and yields. GF has always been bad at launch but they make good improvements over the life of the process. The 32nm SOI process was a classic example. The Llano chip had yield issues and Bulldozer chip launched with horrible clocks in late 2011. But once Piledriver launched the process was in much better shape. Eventually the 32nm SOI process was good for 5 Ghz. So do not try to chose arbitrary points of comparison in process lifetime to fit your narrative.

Improved yields, smaller variation and lower leakage for 14nm LPP due maturation are possible and even likely, at least up to certain extent. With 32nm SHP the process had no direct effect to the maximum achievable clocks, only a indirect one. The poor initial process characteristics (extremely high leakage to be specific) made the CPU to run so hot that it could not reach it's maximum clocks. The issue could be addressed by using non-conventional cooling methods and the initial silicon was not much short of the frequencies which were achieved on much more mature silicon. In fact, 8.4GHz+ was done prior the launch in 2011 on LN2 cooling.

Unlike with 32nm SHP, the immaturity of the 14nm LPP has no ill-effects, outside the higher than expected power draw. The frequency on Polaris is not limited by the high temperatures or the VRM which would be over-run by the excess power draw. You can slap virtually any cooling on the Polaris GPUs, and they basically get nothing out of it. I don't expect 14nm LPP to gain any additional frequency capabilities due maturation, but I expect it to become much more consistent and efficient due to it. If the rumors about nVidia GP107 (6 SMM) are true, it tells us everthing we need to know about the 14nm LPP. The rumor has it that the smallest Pascal is made on Samsung 14nm LPP and has boost clock of just 1380MHz. Meanwhile the larger Pascal variants (GP104 20SMM & GP106 10SMM) have boost clocks of 1898 and 1911MHz.

Regardless, I wish that AMD has the decency to use 16nm FF+ on Raven and the successor of Zeppelin (Zen+ based).

 

[The Stilt]

We have pretty much a direct statement from AMD that Zen will have lower clocks than XV in the fact that ES is only 3.2 single core boost and the fact that AMD had to downclock(!) 6900k for their demo. Will the rumored half a year until release be enough to upclock it to XV levels? We'll see. That recent benchlife rumor makes it look way too reminiscent of Polaris now (first a fairly favorable demo against competition, even if with sketchy rules) then half a year wait.

You do realize that XV levels are now days up to 4.2GHz?

 

[Glo.]

We have so a +50% clock with about the same power...
But all of you keep saying that zen will have lower clocks than XV...
Fine...

I am not saying anything like this.

We have pretty much a direct statement from AMD that Zen will have lower clocks than XV in the fact that ES is only 3.2 single core boost and the fact that AMD had to downclock(!) 6900k for their demo. Will the rumored half a year until release be enough to upclock it to XV levels? We'll see. That recent benchlife rumor makes it look way too reminiscent of Polaris now (first a fairly favorable demo against competition, even if with sketchy rules) then half a year wait.

At 95W, yes it has 3 GHz core clocks. But the AMD Wraith Cooler is designed to work with 125W for a very good reason. Zen CPUs will come in 3 most likely desktop variants. 65W, 95W and 125W.

If you ask me how it fair in the end. Xeon E5 1660v4 has 8 cores, 3.4 GHz base clock, 4 GHz Turbo at 140W, and 1723$ price tag. Let AMD Zen Black Edition Have 8 cores at 3.5 GHz base clock, 4 GHz Turbo boost, at 125W TDP, and 999$ price tag, with Broadwell level IPC, and you have a killer in HEDT.

They do not have to have performance crown, to bring better offer to the market.

 

[lolfail9001]

I am not saying anything like this.

At 95W, yes it has 3 GHz core clocks. But the AMD Wraith Cooler is designed to work with 125W for a very good reason. Zen CPUs will come in 3 most likely desktop variants. 65W, 95W and 125W.

If you ask me how it fair in the end. Xeon E5 1660v4 has 8 cores, 3.4 GHz base clock, 4 GHz Turbo at 140W, and 1723$ price tag. Let AMD Zen Black Edition Have 8 cores at 3.5 GHz base clock, 4 GHz Turbo boost, at 125W TDP, and 999$ price tag, with Broadwell level IPC, and you have a killer in HEDT.

They do not have to have performance crown, to bring better offer to the market.

First: you are confusing 1660v4 and 1680v4. The Zen Black Edition of yours would be pretty much inferior to 1660v4, simply because we have dual channel 8 core against quad channel 8 core with similar performance. And 1660v5 is on the way.
The thing that suggests that even 220W TDP SKU would not clock that much better is the fact that 3.2 is listed as single core boost. Sure, AMD in general listed pretty low Turbo clocks but IIRC those were all-core turbo clocks in general.

 

[raghu78]

Regardless, I wish that AMD has the decency to use 16nm FF+ on Raven and the successor of Zeppelin (Zen+ based).

I think its likely we will see Vega at 16FF+ and Summit Ridge / Raven Ridge on Zen 14LPP in 2017 and their successors on GF 14HP (based on IBM 14nm SOI FINFET) in 2018

 

[bjt2]

We have pretty much a direct statement from AMD that Zen will have lower clocks than XV in the fact that ES is only 3.2 single core boost and the fact that AMD had to downclock(!) 6900k for their demo. Will the rumored half a year until release be enough to upclock it to XV levels? We'll see. That recent benchlife rumor makes it look way too reminiscent of Polaris now (first a fairly favorable demo against competition, even if with sketchy rules) then half a year wait.

BD ES was 2.8 GHz too. And we know the final clocks...

 

[The Stilt]

But the AMD Wraith Cooler is designed to work with 125W for a very good reason.

Making conclusions about Zeppelin's TDP, based on a AM3/+ factory heatsink is pretty far fetched to say at least. Wraith is designed to maintain sufficient °C/W up to 125W, nothing more. The same heatsink is shipped with 95W TDP (and much lower dissipating in reality, X4 880K) too. But yeah, generally I see no issues in using Wraith with Zeppelin too. Unless of course they have to implement some silly bracket for AM3+ compability in AM4 mounting hole pattern.

 

[The Stilt]

I think its likely we will see Vega at 16FF+ and Summit Ridge / Raven Ridge on Zen 14LPP and their successors on GF 14HP (based on IBM 14nm SOI FINFET)

17h 00 - 10h (i.e Zeppelin and Raven) are confirmed for 14nm LPP long a go. Wasn't the 14nm HP exclusively to IBM themselves (Power 9)?

 

[Phynaz]

The fact remains that Polaris shipped at higher clocks than 28nm products. I really dont understand why some of you believe clocks will decrease at 14nm FF. And really, i dont see why ZEN Fmax will top at 3GHz.

Because it's about more than how the chip is manufactured. But you know this.

 

[Arachnotronic]

Because it's about more than how the chip is manufactured. But you know this.

The dramatic improvement in perf/clock is likely to cost AMD some frequency. The higher IPC + new node will help on efficiency, though, so it's a reasonable trade off.

 

[bjt2]

Please see Transmeta's paper on processor and power variations: http://www.design-reuse.com/article...ent-leakage-control-process-compensation.html

Process/processor Vth and the SPICE Box is key to the scaling characteristics of the end product, and it's power.


P rarely equates to v^2*f below 45nm.

Yes, P equates to V^1.7 to V^3 for general roughing, depending on the process and parametric choices, and where in the curve that Vdd falls... *f

Unless you know the k*C values, in which case you have a more accurate profiling with k*C*v^n where n=the relevant voltage factor.

C differs much more than it used to at the smaller nodes while k is a process dependent constant.

For approximations with much data, in terms of IVB, for instance, P scales at ~V^1.75*f until you hit 4.5GHz -- the dead point of diminishing scaling.

Lastly, the Vdd values used in end shipping products is not determined by what we users find in OC/UC, but process wide averaged testing using thousands of samples that fit the median Gaussian distribution (bell curve). End user testing cannot account for this. This Vdd is again linked to the above unknowns/yields.

So we end up with two major factors yet unknown.

Eg. AMD had Agena 65nm running no lower than1.35V for 2.2GHz.

We users could get 1.15-1.20V.

Penryn was even more ridiculous.

However, Agena needed, end user, 1.5V to go >2.35GHz. It was pumped to the pipe in launch. This was a processor designed for 3GHz.

Due to the process/processor parametrics, scaling, from a DT users perspective, was not there.

This is something you cannot approximate until you know the process with some end product data.

Three major unknowns kill off these power and frequency scaling approximations. Until we have a starting datapoint.

The way it is looking with Zen, and this is just a guesstimate that could be completely wrong, it would be easier for AMD to do a Magny Cour than a Piledriver at this stage. Hence my tentative agreement with Abwx's end comment.

Sent from HTC 10
(Opinions are own)

AMD has impelmented, since XV and Polaris, AVFS, boot time calibration and other auto tuning features, with voltage gauges and mini replica of critical paths to tune the frequency to the actual Vcore and silicon status (age, temperature, etc), so we can, for fisrt order approximation, assume low margins on Vcore.

I have done rough approximations, with high margins, for exponents from 1 to 3.
These were only guesses to set a range of frequencies.
My more precise prediction was the one based on the Apple A9X SoC. You may agree or not agree, but I set a probable low limit for the frequencies...

I was starting from the 28nm BULK that is the most near process... Others were with much higher sizer or have SOI... I think that 45nm and 65nm are too old processes to compare with...

 

[Phynaz]

The dramatic improvement in perf/clock is likely to cost AMD some frequency. The higher IPC + new node will help on efficiency, though, so it's a reasonable trade off.

Yep

 

[Glo.]

First: you are confusing 1660v4 and 1680v4. The Zen Black Edition of yours would be pretty much inferior to 1660v4, simply because we have dual channel 8 core against quad channel 8 core with similar performance. And 1660v5 is on the way.
The thing that suggests that even 220W TDP SKU would not clock that much better is the fact that 3.2 is listed as single core boost. Sure, AMD in general listed pretty low Turbo clocks but IIRC those were all-core turbo clocks in general.

Yes, I have mistaken 1660v4 with 1680v4.
Are you sure 8 core, HEDT from AMD will not have quad channel memory?

Making conclusions about Zeppelin's TDP, based on a AM3/+ factory heatsink is pretty far fetched to say at least. Wraith is designed to maintain sufficient °C/W up to 125W, nothing more. The same heatsink is shipped with 95W TDP (and much lower dissipating in reality, X4 880K) too. But yeah, generally I see no issues in using Wraith with Zeppelin too. Unless of course they have to implement some silly bracket for AM3+ compability in AM4 mounting hole pattern.

Zeppelin is the 32 core Server APU. Not the 8 core HEDT CPU.
Wraith cooler wasn't designed without a reason. And the TDP of it is not without a reason, also.

 

[Arachnotronic]

Yes, I have mistaken 1660v4 with 1680v4.
Are you sure 8 core, HEDT from AMD will not have quad channel memory?

Zeppelin is the 32 core Server APU. Not the 8 core HEDT CPU.
Wraith cooler wasn't designed without a reason. And the TDP of it is not without a reason, also.

Zeppelin is the name of the 8 core die that serves as the basis for all of AMD's server products, including the 8C/16T desktop chip that's just a server die in a consumer grade package. It is a dual channel design.

Naples, the 32C/64T part, is an MCM with four Zeppelin dies, each with two memory channels for eight memory channels for the whole chip.

 

[bjt2]

Regardless, I wish that AMD has the decency to use 16nm FF+ on Raven and the successor of Zeppelin (Zen+ based).

Zen+ should be implemented on the same process as POWER9: 14nm FF HP, that should be SOI, if i remember well...

 

[Tcha]

We have so a +50% clock with about the same power...
But all of you keep saying that zen will have lower clocks than XV...
Fine...

Mark P said today that 14nm finfet was allowing 50% higher frequency at the same thermals as 28 nm planar.

 

[bjt2]

I am not saying anything like this.

You said: "The GPU die for D700 consumes 70W of power while having 850 MHz core clock.
GPU die for RX 470 can consume around 85-90W, while having 1206 MHz core clock."

The last was a typo, as it was 1266, but the first 70W you calculated from 165W, so 95W the RAM??? I think that the dice power was comparable, so we have same power, but +50% clock...

 

[bjt2]

The dramatic improvement in perf/clock is likely to cost AMD some frequency. The higher IPC + new node will help on efficiency, though, so it's a reasonable trade off.

BD has a 20 stage pipeline on a 28nm BULK process... Zen has a 19 stage pipeline on a 14nm FinFet process... Why on earth it should clock LESS than BD?

 

[bjt2]

Mark P said today that 14nm finfet was allowing 50% higher frequency at the same thermals as 28 nm planar.

But here they say than Zen does not go more than 3.2GHz... What does this Mark P know more than our forum members? Who is this Mark P?

 

[The Stilt]

Are you sure 8 core, HEDT from AMD will not have quad channel memory?

Zeppelin is the 32 core Server APU. Not the 8 core HEDT CPU.
Wraith cooler wasn't designed without a reason. And the TDP of it is not without a reason, also.

Are you really going to "correct" me, based on information you read from the internet?

Zeppelin (17h 00-0Fh) is the name of the design / die (same as Orochi was for 15h 00-0Fh).

Summit Ridge = AM4 PGA (SCM), consumer segment
Snowy Owl = SP4 BGA (MCM2), server segment
Naples = SP3 LGA (MCM4), server segment

All of these are based on the same Zeppelin die.
There are two 64-bit DDR4 controllers in each Zeppelin die, which means that SP3 parts will have eight channels in total and SP4 parts will have four.

AM4 infrastructure wasn't finalized even remotely by the time Wraith was released, so I'd say Wraith was designed about as much for Zeppelin as the pork chops in my fridge were (while they still were alive). Wraith only exists for marketing purposes, not because it was designed to be recycled with Zeppelin.

 

[krumme]

Improved yields, smaller variation and lower leakage for 14nm LPP due maturation are possible and even likely, at least up to certain extent. With 32nm SHP the process had no direct effect to the maximum achievable clocks, only a indirect one. The poor initial process characteristics (extremely high leakage to be specific) made the CPU to run so hot that it could not reach it's maximum clocks. The issue could be addressed by using non-conventional cooling methods and the initial silicon was not much short of the frequencies which were achieved on much more mature silicon. In fact, 8.4GHz+ was done prior the launch in 2011 on LN2 cooling.

Unlike with 32nm SHP, the immaturity of the 14nm LPP has no ill-effects, outside the higher than expected power draw. The frequency on Polaris is not limited by the high temperatures or the VRM which would be over-run by the excess power draw. You can slap virtually any cooling on the Polaris GPUs, and they basically get nothing out of it. I don't expect 14nm LPP to gain any additional frequency capabilities due maturation, but I expect it to become much more consistent and efficient due to it. If the rumors about nVidia GP107 (6 SMM) are true, it tells us everthing we need to know about the 14nm LPP. The rumor has it that the smallest Pascal is made on Samsung 14nm LPP and has boost clock of just 1380MHz. Meanwhile the larger Pascal variants (GP104 20SMM & GP106 10SMM) have boost clocks of 1898 and 1911MHz.

Regardless, I wish that AMD has the decency to use 16nm FF+ on Raven and the successor of Zeppelin (Zen+ based).

I guess most thought of zen+ as one of the motivators when hearing news about the new wafer agreement with mubadala.
Server cpu is high margin. It doesnt really matter much if you have to pay a fine to gf each time.
As for Raven i wouldnt bet on it. Why? Because they have experience with hbm and tsmc?
Apu is low margin and amd needs to allocate some wafers at gf. Polaris is a good place to start. Zen at GF is...ehh ...perhaps a serious challenge?
Naa keep those freq very low and lets get 4x moar cores for our hosting cost.

 

[Dresdenboy]

I'm enjoying to follow the discussion so far. Due to lack of time just some thoughts:

EDIT: Actually, AMD engineers were fools for not abandoning Bulldozer when it failed the first time on 45nm.

They might have expected to see more with the next process than it actually delivered. That and w/o BD they might have abandoned AMD, too. Would their construction core related revenue (incl. APUs) during the last years have completely gone, what would there be left?

BD has a 20 stage pipeline on a 28nm BULK process... Zen has a 19 stage pipeline on a 14nm FinFet process... Why on earth it should clock LESS than BD?

Main reason: different voltages. Compared at the same voltage, this might be interesting.