AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[Abwx]

Yeah, but you ignore the entire fact that Naples has all the uncore (that consumes relatively constant amount of power) of 4 ZP dies.
Account for that next time.

That s accounted, because power is proportional to throughput, if the CPU has lower freqency the uncore will switch less often as well, and in linear proportion...

And finally, you ignore the fact that power-frequency depends on voltage-frequency you have no clue of right now.

I used a best case scenario where frequency scale down as a root square of power, if the process is average at the displayed 3GHz then power will scale down even further with frequency, but i already posted this above, wich mean that you dont understand what is discussed, so much for branding others as cluless..

Actually you are looking at the things on the wrong end, it s not a process at low frequency whose scaling at higher frequencies is unknown, it s a process at 3GHz whose downscaling cant be better than a square law, i.e, if it s a cubic law power will scale down more than if t s a perfect process (with a square law), so the argument you brought is hence not only completely irrelevant but is even an auto contradiction in the same sentence, yet again talk of having no clues, lol..

 

[KTE]

There is only a single Zeppelin die. Server parts will use multiple of them (2 - 4).

Unlike previous AMD tradition... Are you 100% certain of this?

That'll be good for binning excellent dies together but will be a power drainer with the interconnects.

Edit: I can't see 18-core 115W release TDP being less than 2.0GHz base. I really can't.

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[The Stilt]

Unlike previous AMD tradition... Are you 100% certain of this?

That'll be good for binning excellent dies together but will be a power drainer with the interconnects.

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They did the same exact thing with Bulldozer. The only difference is that 15h used HTT and Zen uses GMI.
99.9% sure

 

[Arachnotronic]

They did the same exact thing with Bulldozer. The only difference is that 15h used HTT and Zen uses GMI.
99.9% sure

It's true, Piledriver Opterons were either 1x 8C Orochi or 2x Orochi in MCM.

 

[Abwx]

Edit: I can't see 18-core 115W release TDP being less than 2.0GHz base. I really can't.

You could, but this would require reading by here, among others :
https://en.wikipedia.org/wiki/MOSFET

At 2GHz the 3GHz/95W 8C/16T they displayed would be within 42W, so that s 84W for 16C and 95W for 18C...

And as said this is a worst case figure by assuming that their process is perfect, otherwise power would downscale by more than 2.25x from 3 to 2GHz, if at 3GHz they are within a 2.5 exponent globally then at 2GHz power would be downscaled down from 95W to 35W for said 8C.

Anyway that s funny that some people go as far as assuming that the process is more than perfect, beyond laws of physics, that s the only mean to make their downscalings with exagerated TDPs have an appearance of realism, assuming of course that the reader has no knowledge of said basic laws..

 

[lolfail9001]

I used a best case scenario where frequency scale down as a root square of power, if the process is average at the displayed 3GHz then power will scale down even further with frequency, but i already posted this above, wich mean that you dont understand what is discussed, so much for branding others as cluless..
Actually you are looking at the things on the wrong end, it s not a process at low frequency whose scaling at higher frequencies is unknown, it s a process at 3GHz whose downscaling cant be better than a square law, i.e, if it s a cubic law power will scale down more than if t s a perfect process (with a square law), so the argument you brought is hence not only completely irrelevant but is even an auto contradiction in the same sentence, yet again talk of having no clues, lol..

Best case scenario of yours has voltage approaching 0 as frequency approaches 0. Do i need to point out where it all falls apart? In fact, Polaris may not tell us about frequency potential but it sure can point out at that some point voltage goes flat, hits a certain tipping point and then turns into linear from freq. So, overall power goes from linear to cubic, no place for squares.

Finally, for all we know it may take an almost flat voltage to get from 1.5 some other point (say 2.7, just for example) and then straight linear voltage/freq dependency to 3 and up. Suddenly it turns into 4*(95-U)*(27/30)^3+4*U. What now? Ah, btw, cache naturally ends up as part of uncore in this equation.

 

[Abwx]

Best case scenario of yours has voltage approaching 0 as frequency approaches 0. .

That s total non sense, but i guess that it s in line with your previous theories..

Do i need to point out where it all falls apart? In fact, Polaris may not tell us about frequency potential but it sure can point out at that some point voltage goes flat, hits a certain tipping point and then turns into linear from freq. So, overall power goes from linear to cubic, no place for squares..

More non sense and with an irrelevant GPU comparison, but even then, if Polaris is of any indication it s to contradict your sayings, because it actually tell us about frequency potential as GCN clock higher with Polaris Finfets than with Bristol Ridge 28nm, that s all that matter to have a clue..

Finally, for all we know it may take an almost flat voltage to get from 1.5 some other point (say 2.7, just for example) and then straight linear voltage/freq dependency to 3 and up. Suddenly it turns into 4*(95-U)*(27/30)^3+4*U. What now? Ah, btw, cache naturally ends up as part of uncore in this equation.

Those are completely irrelevant "maths", either you know what is a fet and what are his fundamental characteristics or else you ll be stuck doing pseudo maths that have absolutely no meaning in reality, let alone any concrete existence.

 

[KTE]

You could, but this would require reading by here, among others :
https://en.wikipedia.org/wiki/MOSFET

At 2GHz the 3GHz/95W 8C/16T they displayed would be within 42W, so that s 84W for 16C and 95W for 18C...

And as said this is a worst case figure by assuming that their process is perfect, otherwise power would downscale by more than 2.25x from 3 to 2GHz, if at 3GHz they are within a 2.5 exponent globally then at 2GHz power would be downscaled down from 95W to 35W for said 8C.

Anyway that s funny that some people go as far as assuming that the process is more than perfect, beyond laws of physics, that s the only mean to make their downscalings with exagerated TDPs have an appearance of realism, assuming of course that the reader has no knowledge of said basic laws..

MOS has nothing to do with your inherent fallacy.

First, 3GHz 95W halo isn't even proven to be a launch SKU. 3GHz Phenom was also demo'd everywhere. We got 2.2GHz after a delayed launch.

Second, 3GHz 95W in 6 months isn't a 'perfect process' like you assume, it's not even good at 14nm to start with. Intel can put out an 8-core 3.6GHz CPU today as soon as pressured.

8-core DT market don't give a hoot about 10-15W, BTW. No one cares in the >$500 market.

The only reason to limit 8core SKUs to lower power would be if your chips don't clock high enough to be competitive in the higher market segments where power is ignored and it's all about raw performance.

So just to be clearer to you: I could definitely see that 2GHz... but it would mean a piss poor clocking@power chip.



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[lolfail9001]

That s total non sense, but i guess that it s in line with your previous theories..

Your scenario has power dropping down as square of frequency right? Well, go ahead and shoot frequency close to 0. What happens now? Voltage goes there as well! And yes, i know of static part in power use, but you are ignoring it as well.

More non sense and with an irrelevant GPU comparison, but even then, if Polaris is of any indication it s to contradict your sayings, because it actually tell us about frequency potential as GCN clock higher with Polaris Finfets than with Bristol Ridge 28nm, that s all that matter to have a clue..

Strictly speaking, you are comparing different arches here, so you are the one without a clue here.

Those are completely irrelevant "maths", either you know what is a fet and what are his fundamental characteristics or else you ll be stuck doing pseudo maths that have absolutely no meaning in reality, let alone any concrete existence.

Sure, go enlighten me, mr "95W 32 core"., show me your fets with square power-frequency curve and your totally not pseudo maths. Because right now they have as questionable of quality as mine.

 

[Abwx]

Your scenario has power dropping down as square of frequency right? Well, go ahead and shoot frequency close to 0. What happens now? Voltage goes there as well! And yes, i know of static part in power use, but you are ignoring it as well.

It s you who is ignoring the fact that i m talking of going to 1.5GHz from 3GHz, i specified it above and the fact that you re asking such a question tell me that you re not here for the technical discussion but just to spam the thread...

Strictly speaking, you are comparing different arches here, so you are the one without a clue here.

Sure, go enlighten me, mr "95W 32 core"., show me your fets with square power-frequency curve and your totally not pseudo maths. Because right now they have as questionable of quality as mine.

More thread crapping, i specified that square law is a best case when scaling frequency up figure but that it s the other way around when scaling frequency down, that is, a cubic law downscale power more rapidly as frequency is decreased, so one more time you are deliberately derailing the thread...

 

[Glo.]

32 cores at 1.44 GHz would be possible at very good process in 150W Thermal Envelope. I dont think the 14 or 16 nm processes are that good, tho.

 

[Abwx]

32 cores at 1.44 GHz would be possible at very good process in 150W Thermal Envelope. I dont think the 14 or 16 nm processes are that good, tho.

That s laws of physics, and here it s even more funny because we hear that GF process is not that good, but the same nay sayers dont know that if it s not good then it means that at 3GHz it has degraded efficency and that scaling frequency down will reduce power much more than if the process was very good, yet we have people that explain us that it s so bad that it downscale like a more than perfect process, lol...

As said if they manage 95W/3GHz/8C then a frequency downscaling with core upscaling cant be worse than 95W/2.1GHz/16C and 95W/1.5GHz/32C...

That s if they have a perfect process, if it s not perfect then the powers should be reduced accordingly, that s laws of physics, whatever the fantaisist maths s of eventual nays sayers..

 

[lolfail9001]

It s you who is ignoring the fact that i m talking of going to 1.5GHz from 3GHz, i specified it above and the fact that you re asking such a question tell me that you re not here for the technical discussion but just to spam the thread...

Someone is weak on rhetorical questions. You made an estimate based on assumptions you can't support with any evidence, that's it.

More thread crapping, i specified that square law is a best case when scaling frequency up figure but that it s the other way around when scaling frequency down, that is, a cubic law downscale power more rapidly as frequency is decreased, so one more time you are deliberately derailing the thread...

When scaling frequency down you will realistically hit the point where power/frequency scaling is borderline linear, rather than square or higher-power. Known facts about GloFo LPP support this statement. What happens to your estimates then?

And finally, if i wanted to disprove your statement on power/frequency, i could simply google a CPU-Z of 2309v4, a CPU-Z of good 6900k@4Ghz and destroy all your assumptions in 1 swell swoop of power consumption measurements. But you are capable of doing so yourself.

 

[Abwx]

Someone is weak on rhetorical questions. You made an estimate based on assumptions you can't support with any evidence, that's it.

No, it s you who dont have a basic maths training and dont understand the meaning of the starting point...

When scaling frequency down you will realistically hit the point where power/frequency scaling is borderline linear, rather than square or higher-power. Known facts about GloFo LPP support this statement. What happens to your estimates then?

If at 3GHz their process is still perfect then at half this frequency power will be 4x lower because a perfect process power scale as 2 degree polynomial with frequency.

Now we know that at 3GHz they are within 95W, but what about if they managed this result with an average process that scaled according to a 2.2 degree polynomial...??

It would mean that at half the frequency power would be scaled down by 2^(2.2) = 4.6x instead of the 2^2 = 4x of the perfect process;

That s why i find some nay sayers funny, in essence they explain us that it scale very badly with frequency increasing but that curiously, starting from high frequency it will downscale better (actually worse in matter of actual TDP reduction) than it did when frequency was increased;

At the end that s the total non sense that is spread here by you among others...

 

[lolfail9001]

If at 3GHz their process is still perfect then at half this frequency power will be halved because a perfect process power scale as 2 degree polynomial with frequency.

Now we know that at 3GHz they are within 95W, but what about if they managed this result with an average process that scaled according to a 2.2 degree polynomial...??

It would mean that at half the frequency power would be scaled down by 2^(2.2) = 4.6 instead of the 2^2 = 4 of the perfect process;

That s why i find some nay sayers funny, in essence they explain us that it scale very badly with frequency increasing but that curiously, starting from high frequency it will downscale better (actually worse in matter of actual TDP reduction) than it did when frequency was increased;

At the end that s the total non sense that is spread here by you among others...

Once again, show me that quadratic scaling you talk about in a "perfect" process, whatever that would mean. In fact, the closest thing i have seen to perfection process wise is going from 610Mhz on 818mV to 930Mhz on 843mV. You can estimate for yourself, how far away from quadratic that is (hint: it's pretty linear).

So, in the end you are using the faulty assumption of "going above comfort zone leads to ugly scaling [well documented fact naysayers use] so same exact scaling happens when you go right into comfort zone and below [citation needed]". And yes, you can preface it as much as you can, but don't try to sell it as some physics.

P. S. 25W 7500U.

 

[Abwx]

Once again, show me that quadratic scaling you talk about in a "perfect" process, whatever that would mean. In fact, the closest thing i have seen to perfection process wise is going from 610Mhz on 818mV to 930Mhz on 843mV. You can estimate for yourself, how far away from quadratic that is (hint: it's pretty linear).
.

Btw, i m not stupid, dont try to fool me with parts of a curve at minimal frequencies, that, is where the gate threshold voltage is still significant in respect of VDD wich require increasing the voltage apparently, but not actually, quasi linearly, what about if we substract the Vth..?..

So willfull bad exemple, what about from 1.5GHz to 3GHz, the frequency range we were talking about...?.

You can check, frequency increasing as a square of voltage, that being said you should do some homework but anyway stop threadcrapping the thread with deliberatly flawed exemples..

And yes, you can preface it as much as you can, but don't try to sell it as some physics.

I let people who have the knowledge to decide who between you and me is posting sentences filled with pseudo science...

 

[jpiniero]

You can easily explain why there isn't as much scaling at lower clock speeds because A.) The GMI interconnect power and B.) GloFo being GloFo.

 

[lolfail9001]

Btw, i m not stupid, dont try to fool me with parts of a curve at minimal frequencies, that, is where the gate threshold voltage is still significant in respect of VDD wich require increasing the voltage apparently, but not actually, quasi linearly, what about if we substract the Vth..?..

So willfull bad exemple, what about from 1.5GHz to 3GHz, the frequency range we were talking about...?.

But that's the thing: 610Mhz is like half the stock clock. Basically i literally took your own 3->1.5 transition and applied it to Polaris' stock clocks. In fact, i should have surpassed 4x scaling with it, right? Right? Woops, i did not.

You can check, frequency increasing as a square of voltage, that being said you should do some homework but anyway stop threadcrapping the thread with deliberatly flawed exemples..

Well, here's the thing: you are agreeing with me now and are trying to frame it as objection. That's classy, i know, but point stands: where is power~freq^2 in here?
EDIT: Wait, i didn't misread "power" as frequency, did i? Yes, i did, welp.

I let people who have the knowledge to decide who between you and me is posting sentences filled with pseudo science...

The one thing i know which does not constitute science is building hypothesis on 0 factual information.

 

[Abwx]

But that's the thing: 610Mhz is like half the stock clock. Basically i literally took your own 3->1.5 transition and applied it to Polaris' stock clocks. In fact, i should have surpassed 4x scaling with it, right? Right? Woops, i did not.

Well, here's the thing: you are agreeing with me now and are trying to frame it as objection. That's classy, i know, but point stands: where is power~freq^2 in here?

The one thing i know which does not constitute science is building hypothesis on 0 factual information.

All your post, starting from the first sentence and its deliberatly flawed exemple comparing a GPU (from one brand..) to a CPU (fom another brand...), is thread crapping, rinse and repeat ad nauseam.

I guess that for the sanity of the thread it s better that you get on my ignore list..

. I dont think the 14 or 16 nm processes are that good, though.

Paradoxally, and as explained in my previous posts, it would be very good news...

 

[krumme]

Not seeing a vast difference, especially with The Stilt's < 297mm² figure.

Sandy bridge 4c was 216mm2 as i can tell. And that was with a gpu included...so yes the difference was huge even before performance difference was factored in.

 

[krumme]

The Stilts fmax vs voltage curves for polaris seems to indicate there absolutely is a lower limit where power vs freq is aprox liniar. Especially vs prior process.

That and the 150/180 w tdp is the most solid data we have. Amd imo it makes good sense all together.

180w for a 32c part is imo lean enough. 95w makes no sense. Why do that?

 

[The Stilt]

AFAIK there won't be any 32C parts with < 150W TDP. SP3 requires four dies to be used, so binning harvested dies to the extent required by MCM makes exactly zero sense, at least if we are talking the very bottom bin of harvested dies (4x4 cores in total / per package). SP3 (Naples) is the highest-end of Zeppelin based server CPUs. SP4 (Snowy Owl) will offer lower core count and lower power options. SP4 is BGA and supports two dies in MCM config.

 

[jpiniero]

AFAIK there won't be any 32C parts with < 150W TDP. SP3 requires four dies to be used

Hmm, I hadn't thought of that. It would certainly make things harder, 4x200 mm2 dies at CPU yield is not going to be cheap. They might still want to do 4x4C simply because of being able to put it into two sockets.

Do all of the dies have to have the same number of cores?

 

[KTE]

There's no such 'v^2 law'. You guys are arguing over nothing.

It's an old observation that rarely holds true after 65nm. You can find anywhere from v^1.7-v^3 accounting for chip scaling, and even then, it's in particular voltage ranges on a shmoo, after which, the chips stop scaling. This is a major problem since 45nm.

Then, where a chip+process is designed for 2-3GHz, it can scale very well with little voltage increase between that range, but right after, the voltage input has to be astronomical for the slightest of frequency gain. We are finding that the scaling does not continue.

Also, this is only accounting for dynamic power, not leakage. Which is even more complex after 45nm.

Hence why projected scaling without good data points is nearly always wrong. Especially where power is concerned.

Also, I would wager hitting max power on Zen would be much more difficult with its beefed up resources (than previous uarchs). So I'd be looking for a major disparity between max power and TDP, and between typical power and max power.

I think it's possible AMD will use this to their advantage when it comes to TDP figures. Certainly for Server SKUs.

Sent from HTC 10
(Opinions are own)

 

[krumme]

800mV seems to be the sweet spot for polaris
https://forums.anandtech.com/index.php?posts/38421916
The interesting is imo its a extremely narrow window. Below 800mV fmax is 900MHz all the way and over 800mV efficiency falls of a cliff. Its facinating.

That indicates imo the freq for zen will also have a comparable or in a historically context very narrow sweetspot for voltage meaning very narrow window for freq if it will stay efficient.
Amd said they went for dense power optimized process.
Imo all point to low freq with a very narrow window.
To me that spells to hell with desktop we went for cloud/wm/laptops/future consoles.