Question AMD Rembrandt/Zen 3+ APU Speculation and Discussion

[izaic3]

Alright, so we've had some leaks so far. I don't know if any of it's been confirmed yet, as it's pretty early, but here is what I've surmised so far (massive grain of salt of course):

• Zen 3 "enhanced"
• DDR5 and LPDDR5 support
• PCIE4
• 6nm
• CVML
• Navi 2/RDNA/RDNA 2
• 12 CU
• Socket FP7/AM5
• Possible USB4
• 2021(unlikely) -2022 (more likely) release date

If if turns out to have RDNA 2 and 12 CU, I could see iGPU performance potentially almost doubling over Cezanne.

If I've made any mistakes or gotten anything wrong, please let me know. I'd also love to hear more knowledgeable people weigh in on their expectations.

 

[DisEnchantment]

4 Zen3 cores and 256 Navi2 shaders are needed for IoT. What the hell is this IoT device?

This is equivalent to 3400G. Faster CPU and slower GPU.

This kind of IoT

https://www.amd.com/en/products/embedded-automotive-solutions

You can see above they are not ASIL/ISO 26262 compliant. N12e would support ASIL requirements needed for Automotive.
My guess TSMC has no ASIL compliant process on the leading edge ( <10nm )
As far as I know, all the latest QC, Exynos Auto and Tegra platforms for Auto are fabbed on some form of Samsung 8LPP/10LPP.

I think they are up against very tough incumbents, lets see.

 

[Mopetar]

Yes and no. As mentioned it's probably really meant for IoT but it could get into some laptops eventually.

I really don't see a 4C 4CU APU fitting into most IoT devices. The older Athlon products that this would undoubtedly replace are 35W - 65W parts (granted there are mobile versions of these chips that listed as being 12W - 25W) on a similar node and in several respects a lot less powerful than this product. A lot of those products are also going to have a small form factor that makes a full-fledged x86 CPU less desirable since an ARM SoC can include some of the additional functionality that those devices need in a much smaller form factor that requires less power and cooling.

These almost certainly end up in low-end corporate desktops or even the inexpensive consumer options that companies like Dell and HP have on offer. Until prices became crazy due to general shortages (and further exacerbated by insane GPU prices making even extremely low-end APUs all that much more valuable due to having onboard video) AMD had the MSRP for their Athlon chips as low as $49, but with most of the models being set aside for OEMs.

Right now that same Athlon 3000G that originally retailed for $49 when it launched in late 2019 is being listed on Amazon for as much as $150 and that's only a dual core CPU with much older graphics technology. Even if AMD doesn't expect prices that good to last, the state of the market definitely leaves plenty of room for a product like this to occupy.

 

[jpiniero]

I really don't see a 4C 4CU APU fitting into most IoT devices. The older Athlon products that this would undoubtedly replace are 35W - 65W parts (granted there are mobile versions of these chips that listed as being 12W - 25W) on a similar node and in several respects a lot less powerful than this product. A lot of those products are also going to have a small form factor that makes a full-fledged x86 CPU less desirable since an ARM SoC can include some of the additional functionality that those devices need in a much smaller form factor that requires less power and cooling.

You'd be surprised. Intel made $900M in revenue last quarter from their IoT business.

 

[Mopetar]

You'd be surprised. Intel made $900M in revenue last quarter from their IoT business.

I'd really have to see what's being classified under that. If you go to their website they lump IoT and Embedded processors together, so it's not hard to imagine that a lot of what they're counting is older equipment that used Atom processors.

For what it's worth AMD has similar lines (or stuff being sold to the embedded market), but a lot of that isn't what I'd classify as IoT or what most people think about when someone talks about IoT devices. Of course IoT has turned into even more of a buzzword than cloud-computing ever was so really it can mean just about anything they want it to.

 

[jpiniero]

I'd really have to see what's being classified under that. If you go to their website they lump IoT and Embedded processors together, so it's not hard to imagine that a lot of what they're counting is older equipment that used Atom processors.

That's fair about embedded devices possibly being included with the segment since you wouldn't want it included with CCG revenue. I guess it's fairer to say that AMD's intention is industrial devices as a whole with the need for an updated GPU.

 

[Abwx]

That's actually an argument for the back port imo. Zen has sufficient performance for most use cases even at lower frequencies, and AMD showed by using mobile oriented libraries for its CPUs that that doesn't necessarily mean forced lower frequencies anyway. And higher energy efficiency/longer battery life is a selling point even in low budget computers so using a specialized older node for such an apparently long living product would make perfect sense.

What i questionned wasnt the use of a bigger node than 7nm but about TSMC s 12nm instead of GF s 12LP+...

The big question is, areal density aside what is the power efficiency difference between 12LP+ and N7P?

A link was posted about GF s 12LPP+, 40% lower power than their own 12LPP wich was an improvement based on their 14LP.

From the numbers it should be at rougly 50% lower power than the latter and quite close from TSMC s first 7nm used for Zen 2 perf/watt wise but not in matter of area since it s only 25% less than their 14LPP, at about midrange from TSMC s 7nm and said 14LPP.

GlobalFoundries Unveils 12LP+ Technology: Massive Performance & Power Improvements

www.anandtech.com

 

[uzzi38]

What i questionned wasnt the use of a bigger node than 7nm but about TSMC s 12nm instead of GF s 12LP+...



A link was posted about GF s 12LPP+, 40% lower power than their own 12LPP wich was an improvement based on their 14LP.

From the numbers it should be at rougly 50% lower power than the latter and quite close from TSMC s first 7nm used for Zen 2 perf/watt wise but not in matter of area since it s only 25% less than their 14LPP, at about midrange from TSMC s 7nm and said 14LPP.

GlobalFoundries Unveils 12LP+ Technology: Massive Performance & Power Improvements

www.anandtech.com

It doesn't need to be a high clocking product at all, the goal would be to produce Monet as cheaply as possible. Glofo's process shouldn't only be cheaper, it should also be higher density than TSMC's N12.

Just using Zen 3 cores is still a 30% IPC uplift over the Zen that Dali uses, and it's even double the cores on top. The performance uplift should be huge enough that marketing Monet should be quite easy even without the much higher clocks N12 could provide.

 

[Mopetar]

So what you're basically saying is that AMD's strategy is to "make Monet money, make Monet money"?

 

[Shivansps]

Edge device that needs GPU compute.

I do think they will make SKUs for laptops but I can't see them spending the effort on this for something that was intended mainly to compete with Atoms and Pentium Gold laptops, etc. If they thought Picasso would have competitiveness issues due to Vega lacking features it seems to me that it would be better to just get out. This is going to be a lot of work.

Well, they HAVE to replace Reven2/Dali and wharever the 5W variant is called eventually, that 14nm SoC is getting old. The question here is if it worth the effort to backport both the CPU and the GPU for it. If they are not going to do it on 12nm it will have to be on 7nm, 6nm or wharever it is.

Picasso was great in desktops but no so much on anything else, to keep using Picasso for years to come with the outdated Vega, old CPU cores power efficiency issues, and DDR4 memory controller i think it is a no-go, at the very least they would need to go back and fix the power issues, Renoir completely destroys Picasso in that front and change the memory controller.

 

[blckgrffn]

Well, they HAVE to replace Reven2/Dali and wharever the 5W variant is called eventually, that 14nm SoC is getting old. The question here is if it worth the effort to backport both the CPU and the GPU for it. If they are not going to do it on 12nm it will have to be on 7nm, 6nm or wharever it is.

Picasso was great in desktops but no so much on anything else, to keep using Picasso for years to come with the outdated Vega, old CPU cores power efficiency issues, and DDR4 memory controller i think it is a no-go, at the very least they would need to go back and fix the power issues, Renoir completely destroys Picasso in that front and change the memory controller.

I believe memory compatibility (not to mention speeds) could be greatly enhanced with a refresh like this.

If you think that that they are still shipping GF 14nm 4C/8T APU's then moving to their latest node and the latest CPU and GPU architectures available makes more and more sense to me, given this is likely a product with a 5-7 year life cycle and GF is way less likely to move away from this process like TSMC might want to do. I mean, is GF *ever* going to deploy technology newer than this? That's probably a separate question.

Is 7nm or 6nm a long term support node for TSMC? I can't keep them all straight, I felt like some where almost disposable and some were meant to stay...

 

[NostaSeronx]

TSMC is less likely to move away from 16/12 since they have their own fab complex. While 7/6 and 5/4 also have their own fab complexes.

GlobalFoundries if they want more revenue from Malta, they need to sacrifice 14LPP/12LP/12LP+ space to 45RF/45RFe/45CLO/45SPCLO. Malta only went profitable when they transferred RFSOI(PDSOI for RF) from Fishkill to Malta.

GlobalFoundries major goal is to get rid of bleeding nodes, that lose money. Sadly operating the FinFET nodes were always a loss for GloFo. Only money-makers like Fab1/Fab7 allowed Fab8 to operate as badly as it did.

The only reason 12LP/12LP+ is still running at GloFo is all the IBM hardliners that stayed to bomb Malta to oblivion.

N12e is the more likely node given a backport. Since, cross-gen IP shares the same generation between 16/12 and 7/6 at TSMC. GlobalFoundries only does that between 65nm-22nm.

The backport idea is also very flimsily since Xbox Series X, Xbox Series S, Playstation 5(OB)/5+(OBP), Renoir/Lucienne, Cezanne/Barcelo, VanGogh, Rembrandt. Why stop now, throw Monet in that group of nodes.

My guess TSMC has no ASIL compliant process on the leading edge ( <10nm )
As far as I know, all the latest QC, Exynos Auto and Tegra platforms for Auto are fabbed on some form of Samsung 8LPP/10LPP.

Model-less support:

Synopsys Delivers Automotive-Grade IP in TSMC 7-nm Process for ADAS Designs

Highlights: Broad portfolio of controller and PHY IP in the 7-nm process includes LPDDR4X, MIPI CSI-2 and D-PHY, PCI Express 4.0, and security IP IP solutions implement advanced automotive-grade...

news.synopsys.com

Model support:

TSMC Delivers World-first 7nm Automotive Design Enablement Platform|Taiwan Semiconductor Manufacturing Company Limited

Hsinchu, Taiwan, R.O.C., May 28, 2020 – TSMC (TWSE: 2330, NYSE: TSM) today announced the availability of the world’s first 7nm Automotive Design Enablement Platform (ADEP),

pr.tsmc.com

 

[Abwx]

GlobalFoundries if they want more revenue from Malta, they need to sacrifice 14LPP/12LP/12LP+ space to 45RF/45RFe/45CLO/45SPCLO. Malta only went profitable when they transferred RFSOI(PDSOI for RF) from Fishkill to Malta.

You are just inventing whatever pass in your mind, and likely to voluntarly derail the thread since a few seconds research say otherwise than your wild speculations...

They transfered nothing since their Dresden plant has always produced SOI product, first by AMD starting at 130nm and then for AMD once Atic took control at 45nm, and is to this day producing SOI based products according to GF s own words.

This certification extends the ability to cost effectively manufacture secure, connected products to Globalfoundries’ 22FDX technology.

GlobalFoundries Dresden Certified to Manufacture Secure Products | GlobalFoundries

Common Criteria Certificate opens the door for new solutions, markets and customers, completing GF’s global network of Secure and Trusted […]

globalfoundries.com

 

[NostaSeronx]

They transfered nothing since their Dresden plant has always produced SOI product, first by AMD starting at 130nm and then for AMD once Atic took control at 45nm, and is to this day producing SOI based products according to GF s own words.

SOI FinFET 14HP was transferred from East Fishkill to Malta. // "What is notable here is 14HP has been moved out of East Fishkill into the Malta fab and East Fishkill is now focused on 300mm RF SOI and Silicon Photonics" => https://semiwiki.com/semiconductor-...-globalfoundries-is-hitting-on-all-cylinders/
45RF/45CLO was transferred from East Fishkill to Malta. => "GF’s East Fishkill-based 45RFSOI and silicon photonics technologies will be moved to Malta." // https://globalfoundries.com/blog/silicon-photonics-marriage-optical-and-digital-gfs-rf-process


SOI Nodes are available at all three locations; Dresden, Malta, Singapore currently.

However, 45nm PDSOI & FDSOI is a major thing at Malta:
(( “We are working on several things with GF to take the work that we’ve done in pilot production on the 45nm RF SOI, combine it with some of the technologies and processes that GF has from the IBM R&D acquisition, and mix those together to build a highly reliable and manufacturable process to build our solution in 45CLO,” Wade said.

GF’s Yu said the company’s 45CLO monolithic technology will be manufactured at Fab 8 in Malta, New York and plans on qualification of its production process in the second half of 2021. ))
45CLO/45RF = 45nm PDSOI
45SPCLO/45RFE = 45nm FDSOI

Community & Services | GLOBALFOUNDRIES

GF Partner Community & Services GF Partner Community Manufacturing Services

globalfoundries.com

45SPCLO => APR 14 4C00 // 45nm FDSOI first mpw
45RFE => OCT 6 4E00 // 45nm FDSOI second implementation first mpw
Both of which are fabbed at Malta.

All of which will be the key focus of fabrication at Malta going forward.

There is also the 90nm FDSOI w/ Skywater which Malta has to fab for Skywater in HVM capacity: https://www.skywatertechnology.com/...domestic-supply-assurance-for-u-s-government/
RH90 is a fully depleted silicon-on-insulator (FDSOI) complementary metal-oxide-semiconductor (CMOS) process specifically developed to produce electronics which can withstand harsh radiation environments.
Furthermore, this S90RH platform uses the already-proven 90 nm fully depleted silicon-on insulator, or FDSOI, frontend process licensed from MIT-Lincoln Laboratory, where the FDSOI architecture provides improved radiation tolerance, higher transistor speed, and lower power operation. This contract also includes an option for the DoD to fund enhancements and extensions to this technology.

Going further, the first fab to bring forth 12FDX, is also Malta. With a comprehensive migration plan that is much larger than the current FDXcelerator Partner Program & RFwave Partner Program. Which was suppose to support migrations from 14HP, 14LPP, 14LPP+, 12LP, 12LP+ to 12FDX. However, we have only been given Dresden's adoption timeline, not Malta's 12FDX adoption timeline.

14LPP = Late 2015, Exref: https://www.anandtech.com/show/9764...e-first-14nm-finfet-sample-production-success
12LP = Late 2017, Exref: https://www.anandtech.com/show/11854/globalfoundries-adds-12lp-process-tech-amd-first-customer
12LP+ = Late 2019 Exref: https://www.anandtech.com/show/1490...nology-massive-performance-power-improvements
To follow the trend: A 12FDX announcement needs to occur within the half we are in.
"This next generation has been approved by one of our customers and will be rolled out to other customers over the coming year." - SOITEC under FDSOI(Exisiting: 28/22/18 FD substrates, Advanced/Next-Gen: 12 FD substrates) - September 2, 2020

14LPP: 1x perf, 1x power }
12LP: 1x perf, 0.9x power } Same Masks required
12LP+: 1.2x perf, 0.5x power}
12FDX-2017: 1.3x perf, 0.47x power >> Less masks required

This however develops how unlikely AMD would continue to fab at Malta. It also doesn't work in the sense that the amended 7th agreement cancels the 14nm and 12nm exclusivity commitment. So, there isn't a need or requirement for AMD to pump out GlobalFoundries fabbed products.

Especially with:
• development of test APIs/algorithms for 16FFC/12FFC products working with IP designers to achieve maximum coverage within overall estimated test cost in production across SORT/FT/SLT
• Asia Technology Showcase - SAMUROM BIST Failure, debug methodology and resolution for 12FFC/16FFC+
• Recognized for driving the 12FFC technical feasibility assessment with the 12nm test vehicle with a high quality analysis and providing a data based recommendation to the CEC to make a well-informed decision on the feasibility of the 12nm project despite the delays in the fab cycle time for the test vehicle wafers and the delays in sorting due to capacity priorities in the OSAT

There is a lot of TSMC 16FFC+/12FFC+ notes, however N12e is a superset of both. It makes sense N12e is the node and not 12LP+. If we are talking about backports.

4-core Zen3 w/ 8 MB L3 and 4 CU RDNA2 would most likely share its node with Rembrandt and be the Pollock(FT5 socket-esque/class companion) of Van Gogh.

Raven2/Dali/Pollock = 150 mm2 = backport Zen3/RDNA2 12LP+/N12e => >225 mm2
Rembrandt = 208 mm2 = smaller die N6 => >100 mm2

 

[uzzi38]

The big question is, areal density aside what is the power efficiency difference between 12LP+ and N7P?

Difference in area is huge. Like 12LP+ is only like 25-30% better than 12LP, whereas N7 nearly doubled density iirc.

Difference in power efficiency much less so though. More like 20% or so probably. Glofo claim 12LP+ is either 20% perf or 40% power vs 12LP, TSMC claim N7 is 30% perf or 55% power vs N16

 

[soresu]

Difference in area is huge. Like 12LP+ is only like 25-30% better than 12LP, whereas N7 nearly doubled density iirc.

The lower core/CU count should help with that at least.

Though RDNA2 is pretty chonky vs Vega, so it's likely still gonna be bigger than Renoir, possibly even Cezanne.

I do wonder why Monet wasn't on the earlier roadmap though, whether it was named something else or if it's just the node capacity crush that prompted a new SoC on old node.

 

[uzzi38]

The lower core/CU count should help with that at least.

Though RDNA2 is pretty chonky vs Vega, so it's likely still gonna be bigger than Renoir, possibly even Cezanne.

I do wonder why Monet wasn't on the earlier roadmap though, whether it was named something else or if it's just the node capacity crush that prompted a new SoC on old node.

It could be a 2023 product as opposed to 2022 like we first thought. Tbh not a huge amount is known about Monet past the specs RGT talked about.

 

[DrMrLordX]

So what you're basically saying is that AMD's strategy is to "make Monet money, make Monet money"?

Monet money, Monet problems.

 

[DisEnchantment]

TSMC is less likely to move away from 16/12 since they have their own fab complex. While 7/6 and 5/4 also have their own fab complexes.

GlobalFoundries if they want more revenue from Malta, they need to sacrifice 14LPP/12LP/12LP+ space to 45RF/45RFe/45CLO/45SPCLO. Malta only went profitable when they transferred RFSOI(PDSOI for RF) from Fishkill to Malta.

GlobalFoundries major goal is to get rid of bleeding nodes, that lose money. Sadly operating the FinFET nodes were always a loss for GloFo. Only money-makers like Fab1/Fab7 allowed Fab8 to operate as badly as it did.

The only reason 12LP/12LP+ is still running at GloFo is all the IBM hardliners that stayed to bomb Malta to oblivion.

N12e is the more likely node given a backport. Since, cross-gen IP shares the same generation between 16/12 and 7/6 at TSMC. GlobalFoundries only does that between 65nm-22nm.

The backport idea is also very flimsily since Xbox Series X, Xbox Series S, Playstation 5(OB)/5+(OBP), Renoir/Lucienne, Cezanne/Barcelo, VanGogh, Rembrandt. Why stop now, throw Monet in that group of nodes.
Model-less support:

Synopsys Delivers Automotive-Grade IP in TSMC 7-nm Process for ADAS Designs

Highlights: Broad portfolio of controller and PHY IP in the 7-nm process includes LPDDR4X, MIPI CSI-2 and D-PHY, PCI Express 4.0, and security IP IP solutions implement advanced automotive-grade...

news.synopsys.com

Model support:

TSMC Delivers World-first 7nm Automotive Design Enablement Platform|Taiwan Semiconductor Manufacturing Company Limited

Hsinchu, Taiwan, R.O.C., May 28, 2020 – TSMC (TWSE: 2330, NYSE: TSM) today announced the availability of the world’s first 7nm Automotive Design Enablement Platform (ADEP),

pr.tsmc.com

Automotive Grade != ISO26262 Certified, in other words, AEC Certified yes, ASIL certified no

Automotive | GlobalFoundries

Partner with GF for your automotive needs with future-ready automotive platforms and infrastructure    The transition to Software Defined Vehicle (SDV) […]

globalfoundries.com

GF 12FDX is supposed to be, but currently in production they have 22FDX
N12e is ASIL certified, Samsung 8LPP is ASIL certified. The process itself does not necessarily have to be, but the product made out of that process has to meet the certification. One of the reasons why Orin will be fabbed on 8LPU/A

 

[izaic3]

First mentions of AMD RDNA1 "Cyan Skillfish" iGPU for future Ryzen APUs appear in Linux code

We were expecting to see RDNA iGPUs added to the Ryzen 5000 APUs, but AMD was not able to sync the production schedule for that to happen. Then we saw the leaked future gens with RDNA2 iGPUs, and we thought AMD is probably ditching the RDNA iGPUs altogether, but some recent Linux code uncovered...

www.notebookcheck.net

Do you guys think they would split the Rembrandt mobile series like that?

 

[jpiniero]

Do you guys think they would split the Rembrandt mobile series like that?

A Cezanne rebrand is pretty much a given.

Edit: RDNA1? I suppose that could be Raphael as mentioned in the article.

 

[Kepler_L2]

Cyan Skillfish is the PS5 APU.

 

[uzzi38]

Cyan Skillfish is the PS5 APU.

I don't know of anything but this that it could be as well.

 

[NTMBK]

First mentions of AMD RDNA1 "Cyan Skillfish" iGPU for future Ryzen APUs appear in Linux code

We were expecting to see RDNA iGPUs added to the Ryzen 5000 APUs, but AMD was not able to sync the production schedule for that to happen. Then we saw the leaked future gens with RDNA2 iGPUs, and we thought AMD is probably ditching the RDNA iGPUs altogether, but some recent Linux code uncovered...

www.notebookcheck.net

Do you guys think they would split the Rembrandt mobile series like that?

Doesn't make sense to me- RDNA2 was much more power efficient than RDNA1. Only thing I can think of is if they ported the design to another fab, like Samsung- the extra time for the port could explain the older GPU, and a second fab would give them a lot more capacity.

 

[soresu]

Cyan Skillfish is the PS5 APU.

That designation is a driver designation, and AMD don't write the PS4 and PS5 drivers.

If they did I would have expected this at least back when the PS5 tech details were released earlier last year.

 

[soresu]

Seems like 'Cyan Skillfish' is a semi custom APU for a specific client, like that Subor thing a while back.