Question AMD Phoenix/Zen 4 APU Speculation and Discussion

[uzzi38]

I can finally make this thread.

https://twitter.com/x/status/1519669375283957760

Phoenix is indeed RDNA3. My advice to everyone: treat the old APU rumours as being out of date.

 

[uzzi38]

Just the opposite. They needed the cost savings from the smaller die to make Phoenix viable.

Edit: I had assumed that they are/would have used the 7540U for both versions but possibly Legal insisted they separate the two.

No, they realised PHX2 was better for the laptops it would eventually have ended up in so they decided so they tacked the 5 on the end because it is better than the 7540U for anyone buying a thin and light laptop.

Also, PHX2 isn't very competitive vs just buying whatever the current name for Rembrandt refresh is (which will still be available next year too). The only thing it does it makes the absolute low end for the FP7/FP7r2 platform a little cheaper.

 

[jpiniero]

Also, PHX2 isn't very competitive vs just buying whatever the current name for Rembrandt refresh is (which will still be available next year too).

The only thing Rembrandt is better in is IGP gaming. Everything else Little Phoenix should be better.

 

[TESKATLIPOKA]

View attachment 88236
Ye, Zen 4C cores only appear to benefit at extremely, extremely low power ranges, and the power benefit doesn't even seem to be that extreme either unless you go all the way to <13 watts.

It's not that bad.
At 17.5-22.5W they are very similar.
7840HS manages only 15,640 points at 45W.
With a config like what you would get with Strix Point -> 4 standard and 8 dense cores, you get ~16,200-18,400 points at 35-45W.
You gain extra 18% of performance at the same 45W.

If with Zen5c they can make the difference between standard and dense core even bigger, then we can expect a pretty nice bump in MT performance.

 

[Abwx]

20% better perf at 10W mean that at 6.5W PHX2 will perform as well as PHX@10W, in power constraint usage, that is on battery, this should help increase battery life by 30% or so at same usage, that s not negligible with Cromebooks and other such dedicated devices.

 

[SpudLobby]

The gaps would be much larger too if they compared a 6c Zen 4C vs the 7540U instead of the 2+4 configuration which still has the overhead of the Perf/W curves of those two big cores. You'd be looking at a 50% larger gap than the current one at some points on the curve, albeit it'd perform worse at other points on the curve since it lacks the 2 big cores and their curves as you scale up. But a worthwhile trade for the target market (hits ST peak though obviously).

Good confirmation though that they leave stuff on the table here for low power instances (sub-15W). I'd rather have 8 Zen 4c cores and have the die space devoted to more L3 than the standard 8 Zen 4. Alas, AMD won't do that.

 

[jpiniero]

The only thing it does it makes the absolute low end for the FP7/FP7r2 platform a little cheaper.

If AMD rebrands Rembrandt, it's because OEMs simply want to reuse current designs. But it doesn't seem like it will be that much... I looked at Lenovo and Rembrandt currently is only a couple of models. It's still mostly Cezanne but there are plenty of Phoenix models now that Little Phoenix is ready.

 

[SteinFG]

If AMD rebrands Rembrandt, it's because OEMs simply want to reuse current designs. But it doesn't seem like it will be that much... I looked at Lenovo and Rembrandt currently is only a couple of models. It's still mostly Cezanne but there are plenty of Phoenix models now that Little Phoenix is ready.

They reused Cezanne in 2023, they'll reuse Rembrandt in 2024, makes sense to me. 8030U Rembrandt-refresh-refresh coming soon

 

[LightningZ71]

I wonder how far they considered taking this approach (phx2). Did they internally test a version with 2+6(16)? Did they consider the possibility of making a flagship H series with a 4 core z4 cluster and an 8 core Z4c cluster with a 2CU iGPU? That could have been an MT monster.

 

[Mopetar]

So do we consider this AMD's first hybrid chip or not? I'm still confused about Ian's stance not considering Little Phoenix and claiming AMD hybrid chips are still way out.

I wouldn't considering there's no difference between the cores from an ISA perspective. They're not as different as Intel's P and E cores and probably much closer to the usual differences that AMD has had in their Zen cores across different products and nodes.

 

[SteinFG]

I wonder how far they considered taking this approach (phx2). Did they internally test a version with 2+6(16)? Did they consider the possibility of making a flagship H series with a 4 core z4 cluster and an 8 core Z4c cluster with a 2CU iGPU? That could have been an MT monster.

It's easier to make the cheapest die a market will bear and a good part that can be used anywhere, regardless if it's connected to the gpu or not. So the answer to your question is almost certainly no.

 

[igor_kavinski]

Is there an annotated die shot of the 7545U available?

 

[SteinFG]

Is there an annotated die shot of the 7545U available?

Found on twitter

 

[igor_kavinski]

View attachment 88335
Found on twitter

Lovely!

So a shared cache between all the cores automatically gives them a higher cache hit rate rather than trying to transfer data over the ring bus like the stupid separate Intel P-core/E-core cluster mess. Is my understanding correct?

 

[TESKATLIPOKA]

Lovely!

So a shared cache between all the cores automatically gives them a higher cache hit rate rather than trying to transfer data over the ring bus like the stupid separate Intel P-core/E-core cluster mess. Is my understanding correct?

Why are you surprised?
Did you forget that Zen1(+) had 4+4(2*CCX) cores per chip, Zen2 had 4+4(2*CCX) per CCD and had two of them.
Zen3 increased core count per CCX to 8 instead of 4.

 

[tamz_msc]

Lovely!

So a shared cache between all the cores automatically gives them a higher cache hit rate rather than trying to transfer data over the ring bus like the stupid separate Intel P-core/E-core cluster mess. Is my understanding correct?

?
Zen 3 onwards uses a bidirectional ring-bus too.

 

[igor_kavinski]

Why are you surprised?

I'm pleasantly surprised that they did the logical thing instead of doing the dumb thing of creating separate clusters of Zen 4 and Zen 4c cores, automatically raising the communication latency between the dissimilar core clusters.

 

[igor_kavinski]

?
Zen 3 onwards uses a bidirectional ring-bus too.

What I'm referring to is that there aren't multiple CCDs so intercore communication latency should be much less between the Zen 4 fat cores and Zen4c tiny cores. Imagine if they had done the Intel bone-headed way of having one CCD for fat cores and one for tiny cores.

 

[TESKATLIPOKA]

I'm pleasantly surprised that they did the logical thing instead of doing the dumb thing of creating separate clusters of Zen 4 and Zen 4c cores, automatically raising the communication latency between the dissimilar core clusters.

I kinda don't understand why you even thought that they will do the dumb option?

 

[igor_kavinski]

I kinda don't understand why you even thought that they will do the dumb option?

Because knowing only about the Intel way, I didn't know before what the clever way of going about it would be

 

[TESKATLIPOKA]

Because knowing only about the Intel way, I didn't know before what the clever way of going about it would be

AMD is also using ring bus and shared L3 like Intel. So the Intel way is the correct way. The wrong way is(was) the AMD way of using separate clusters.

 

[igor_kavinski]

L3 in Raptor is also shared between P and E-cores.

It's shared between P-cores and "cluster" of E-cores. All four e-cores of a cluster are not directly connected to the L3. There has to be an additional latency or some agent that has to ensure that the received data from the L3 lands on the correct one of the four E-cores. There is more overhead in the Intel way. At least, that's what it seems like to me.

 

[TESKATLIPOKA]

It's shared between P-cores and "cluster" of E-cores. All four e-cores of a cluster are not directly connected to the L3. There has to be an additional latency or some agent that has to ensure that the received data from the L3 lands on the correct one of the four E-cores. There is more overhead in the Intel way.

There is, as is when AMD is using separate CCDs + IOD on top of that.
So what's the big deal about It?

 

[igor_kavinski]

So what's the big deal about It?

I think the 7545U could be a very snappy CPU in real world use. Much better than any comparable Intel hybrid mobile CPU.

 

[TESKATLIPOKA]

I think the 7545U could be a very snappy CPU in real world use. Much better than any comparable Intel hybrid mobile CPU.

That's based on what? Or in what APP?
We are still talking about 2+4 vs 2+8.
CB R23 looks like It would be pretty similar even at comparable TDP.
I would normally except a difference in gaming, but those CPUs are mainly using only IGPs.
If the price is similar, then I would choose AMD because I don't like Intel's Big-little approach.

 

[igor_kavinski]

That's based on what? Or in what APP?

Just a feeling. I'm talking more about responsiveness than absolute performance. The 7545U should feel much snappier. In case Chips and Cheese does a proper article on it, we will surely get some juicier benchmarks.