Discussion AMD cools the pace to Moore's Law Death

[adroc_thurston]

it would seem like improving memory access is should become the new low hanging fruit in the future.

The only way to do that is moar SRAM, which directly translates to moar $$$ since SRAM scaling is Very Dead.

 

[maddie]

Although this is from the before times

Nice description.

 

[RTX]

I am not as low on Zen 6 clock speed as many here are, Zen 3 to Zen 4 was a huge boost to clock speed.
While I expect lower improvement from Zen 5 to Zen 6, I think close to 10% is reasonable. So we could have a 11950X (if that's the name) with 1 core max clock speed of 6.1-6.2GHz. That's not bad at all if it also comes with a 10% IPC improvement.
N3P is much better than N3B, a problematic node, and Intel is clocking at 5.7GHz with the latter.

Might be harder for AMD if they are going to use the 2-1 fin option to save on die area.

 

[FlameTail]

Might be harder for AMD if they are going to use the 2-1 fin option to save on die area.

That would explain the rumours about how Medusa will have 12-core Zen6 CCDs, which are still ~70 mm². That means Zen6 will be a smaller core than Zen5.

 

[fkoehler]

The only way to do that is moar SRAM, which directly translates to moar $$$ since SRAM scaling is Very Dead.

From a proc-centic POV thats correct, and I should have explained a bit more where I was aiming.

I think we are already well into the memory wall on the PC side now such that its going to become more and more an impediment even as we grind out smaller and smaller litho/uarch gains in the future.
Everytime there is a cache miss the core has to go off-die to main memory, which causes n wait-states.
At 5ghz its n wait states
At 6ghz, its n + 20% wait states
Maybe it can do a context switch in the interim and do useful work, maybe not.

So our new 6ghz system is going to be faster than our old 5ghz potato, but we are not going to see significantly greater processing power as we might have in the past because cache-misses and off-die memory access is not improving at anywhere near the rate we've seen with proc architecture.
So even though our proc is 16% faster at 6ghz, every off-die memory access (non-cache) is burning more non-productive cycles in wait states at 6ghz vs 5ghz.
Now extrapolate from 5-6-7-8ghz, and there is only so much other work that can be done while waiting for memory return, and it would appear that the faster you go, the greater and greater off-die memory accesses are going to limit the actual work the proc can complete.

In fact its probably much worse because OS and people have doubled-tripled the number of processes and apps open at any one time such that I imagine a current cache-trace utility would show caches fragmented like crazy nowadays. Which then leads to more cache-misses and off-die requests slowing yet more.

So from a proc-centric POV, the faster we go without addressing memory speed, the lower and lower improvements we will be able to actually realize.
Semi-Analysis did an interesting video on the memory wall though he focused on economics and scaling vs efficiency and effects upon system throughput.

Making SRAM smaller/3d isn't going to really help, it'll be a crutch that will allow greater amounts of cache to hopefully prevent more cache-misses is all.
Knocking a zero off DDR latency would probably be like adding a Ghz or more to Core speed I would guess.

 

[reaperrr3]

That would explain the rumours about how Medusa will have 12-core Zen6 CCDs, which are still ~70 mm². That means Zen6 will be a smaller core than Zen5.

For what it's worth, the rumor says ~75mm², so about ~10% bigger than a Zen5 CCD.
The logic transistor scaling of N3P vs. N4P might be good enough to do that even if there are 2-2 and 3-2 transistors in the mix, from a Zen5 CCD you only need to get ~28% smaller to get to ~50mm², +50% cores/L3 and we land at the rumored ~75mm².

And I wouldn't expect any major transistor-costing changes in Zen6, rather many smaller optimizations, hardware errata fixes and picking of other low-hanging fruits with good PPA ROI, along with leveraging N3P for higher turbo-clocks (at least when not all cores are fully utilized).
There were also rumors that the Zen6 consumer cores might now all get the Strix treatment of slimming the FPUs back to 256bit, though I don't know how feasible that is (it would require more CCD variants, after all).

The only way to do that is moar SRAM, which directly translates to moar $$$ since SRAM scaling is Very Dead.

I think that's one reason AMD is starting to go with bigger CCDs instead of moar CCDs.
Bigger CCDs = when not all cores are fully utilized, more L3 available for each core that actually does some work.

Taking the rumored 12core Medusa CCD for example, if the CCD has 48MB L3 and they still do V-Cache the Zen5 way by then, that'd be a whopping 144MB L3 for one CCD.
Even if Zen6 core IPC and clockspeed only increase modestly, Zen6X3D may very well bring a notably bigger gaming performance uplift than even the 9800X3D did, simply courtesy of 50% more L3/V-Cache for that 1 CCD.
The better MT scaling in games with more than 8 threads would only be the cherry on top.

For Zen7 or later, Skymont also has me wondering whether AMD may eventually start to share blocks of L2 between clusters of 2-4 cores as well, since that's another measure that would potentially allow to reduce RAM accesses for bigger threads without increasing total SRAM investment per core.

 

[GunsMadeAmericaFree]

Based on plans Intel will eclipse AMD in 2026. It's that simple.

Is that when Intel processors are expected to get better graphical abilities?

 

[gdansk]

Is that when Intel processors are expected to get better graphical abilities?

They already have it. Lunar Lake is as good as RDNA3.5 in most cases at lower power.
Late 2025/early 2026 is when Darkmont will eclipse Zen 5 IPC in a core half the size while Zen 6 won't be available until late 2026.

So based on roadmaps it will not be a good time for AMD. The roadmap doesn't make sense unless they're counting on Intel not existing.

 

[DavidC1]

So based on roadmaps it will not be a good time for AMD. The roadmap doesn't make sense unless they're counting on Intel not existing.

Them switching CEOs like women need new tampons don't help in this regard.

The x86 vendors are in for a tumultuous time.



Ridiculous and offensive analogy. Don't do it again.


esquared
Anandtech Forum Director

 

[Thunder 57]

Them switching CEOs like women need new tampons don't help in this regard.

The x86 vendors are in for a tumultuous time.

Really?

 

[fkoehler]

They already have it. Lunar Lake is as good as RDNA3.5 in most cases at lower power.
Late 2025/early 2026 is when Darkmont will eclipse Zen 5 IPC in a core half the size while Zen 6 won't be available until late 2026.

So based on roadmaps it will not be a good time for AMD. The roadmap doesn't make sense unless they're counting on Intel not existing.

Its funny how 5-6 hours can make a plausible statement actually completely implausible.

 

[gdansk]

Its funny how 5-6 hours can make a plausible statement actually completely implausible.

Nothing has changed. It is still the roadmap. This was posted after the news in any case.