Discussion AMD Cezanne/Zen 3 APU Speculation and Discussion

[TESKATLIPOKA]

If Rembrant is really 208mm2, then the known specs don't match. As Seronx mentioned, the SoC in Xbox series S is only 197mm2(8 Zen2 cores, 24CU RDNA2, 128bit GDDR6) and Renoir is only ~150mm2.
There could be more cores, which is very unlikely considering Zen3 has 8 cores per CCX and the size is small for 16 cores(2x CCX) or a lot more L3 cache. I don't think Zen3 core is so much bigger than Zen2 to explain the difference in size.

 

[lightmanek]

We need to keep in mind that Cezanne should also support PCIe 4.0 and possibly new USB standards. That can eat up few transistors as well ...

 

[Kedas]

If this rumor is true it looks like AMD really likes to mix-up 5000 series numbers with Zen2 cores again (facepalm)
I'm sure there were 4000 series numbers left to use...

AMD Ryzen 5000 Cezanne "Zen 3" & Lucienne "Zen 2" APUs Detailed

A series of reports regarding AMD's Ryzen 5000 APU lineup which features the Zen 3 based Cezanne & Zen 2 based Lucienne APUs have emerged.

wccftech.com

 

[Thibsie]

Well, if those zen2 cores are used in embedded automotive related CPUs, I don't think we need to care a damn.

 

[soresu]

We need to keep in mind that Cezanne should also support PCIe 4.0 and possibly new USB standards. That can eat up few transistors as well ...

Somebody give that man a cigar!

 

[Hans de Vries]

From Twitter picked op by VideoCardz:

https://twitter.com/i/web/status/1317827352437686272

AMD Ryzen 5000U "Cezanne/Lucienne" mobile series specifications leaked - VideoCardz.com

The full specifications of the AMD Ryzen 5000U series have been revealed. AMD Ryzen 5000U – a mix of Cezanne and Lucienne Just a few hours after publishing the story about Ryzen 5 5600U specifications leaked by ExectutableFix, the leaker posted the full specifications of the whole series. The...

videocardz.com

Cézanne and Lucienne specs:

 

[jpiniero]

Cézanne and Lucienne specs:

That's not going to be confusing at all. Cezanne is going to be the way better product. But I bet OEMs will buy Lucienne since it will likely be cheaper.

 

[Kedas]

Sure it's not confusing if the number start with an 5 and the next digit is an even number then it's Zen3 otherwise it's Zen2.

 

[Shivansps]

Definitely sounds more like 12 CU than the 24 CU that Nosta insists to be the case.

That sounds correct to me, 24CU RDNA2 is designed for 128bit GDDR6, so 12CU for 128bit DDR5 sounds about right. Altrought it may be a little more, maybe 14CU if it really is 208mm2.

I think they are aiming for RX570 perf.

 

[mikk]

So there are three Zen 2 SKUs and three Cezanne SKUs if this is true. This is super confusing and the 0815 user has no chance to differentiate between Zen 2 and Zen 3 devices when they all use the 5000U branding. And why do they need to mix between Zen 2 and Zen 3? Not enough capacity, fool the mainstream buyer or why?

 

[Hans de Vries]

Well, for a number of benchmarks you get a nice staircase.
Single threaded ones not so much.

 

[uzzi38]

Wonder if Cezanne is actually on N7+? Unlike Vermeer, it actually has improved base clocks over Zen 2 counterparts.

Could explain why Lucienne also exists. N7+ capacity requires time with the EUV machines, which will be shared with Apple.

 

[NostaSeronx]

Wonder if Cezanne is actually on N7+? Unlike Vermeer, it actually has improved base clocks over Zen 2 counterparts.

Could explain why Lucienne also exists. N7+ capacity requires time with the EUV machines, which will be shared with Apple.

N7+ is at Fab 15B while N5 is at Fab 18A.
N7+ is shares its floor space with N10, N7, N7+, N6.

N5 will not share fab capacity with any node except cost-effective RTO N4 and for N3/N2 up to 0.9v DKs before they switch over to their own fabs.

Apple doesn't use Fab 15 EUV machines(N7+/N6), instead uses Fab 18 EUV machines(N5). Which they only are sharing with an unspecified HPC customer.

C. C. Wei - Q1 2020
"But all I can say is now in N5, we have customer from -- smartphone; customer from HPC-related area"

The only two products to be on N7+ is Ascend 910 and Kirin 990 5G. Everyone else has moved to 2nd wave 7nm family node: N6 and 1st wave 5nm family node: N5.

 

[exquisitechar]

Wonder if Cezanne is actually on N7+? Unlike Vermeer, it actually has improved base clocks over Zen 2 counterparts.

Could explain why Lucienne also exists. N7+ capacity requires time with the EUV machines, which will be shared with Apple.

Interesting. I can see this being true. Why would Lucienne even exist as it does otherwise?

 

[LightningZ71]

Maybe Lucienne and Cezanne are on the same base process, but use different track libraries. Cezanne uses denser libraries to fit it's increased transistor count into the same die space, but Lucienne uses a relaxed track library set with minor circuit and firmare tweaks. Also, with N7 being more mature, they are seeing better yield fractions, so they can have higher CU counts per performance level.

I think Ice Lake performing as well as it did has affected their binning tiers for the CUs. Tiger Lake was too recently uncovered to go into that calculus in my opinion.

 

[jpiniero]

Interesting. I can see this being true. Why would Lucienne even exist as it does otherwise?

uzzi's reasoning makes sense to me, but the answer would be because Lucienne is smaller and thus AMD can get more chips out of it.

 

[exquisitechar]

uzzi's reasoning makes sense to me, but the answer would be because Lucienne is smaller and thus AMD can get more chips out of it.

Ah, true. Cezanne even has twice the L3 cache based on these leaks. Still, big mistake if AMD is doing this.

 

[jpiniero]

Ah, true. Cezanne even has twice the L3 cache based on these leaks. Still, big mistake if AMD is doing this.

OEMs don't seem to mind, if the Comet Lake/Ice Lake mashup is any indication.

 

[LightningZ71]

There is still a notable generational improvement at each SKU. The odd numbered SKUs gain: added boost clock, one more CU, and HT. The even numbered SKUs gain more L3 and the Zen3 core improvements. Going up from an even to the next odd, you gain one CU and two more cores, so at least an MP/MT improvement and an iGPU performance. The only place where it will be a bit situational is in single threaded benchmarks or things that are case sensitive between 4MB and 16 MB.

 

[Gideon]

Cezanne even has twice the L3 cache based on these leaks

Interesting, haven't noticed that, where was this mentioned?

EDIT: Never mind, opened the twitter post (preview truncates the L3 part).
16MB unified L3 from 4MB per CCX should improve ST perfomance a lot (on top of other Zen 3 gains). It also IMO hints at 7NP or 7N+ as otherwise such a cache increase could negatively affect battery life (especially as it also as higher base-clocks).

 

[Olikan]

EDIT: Never mind, opened the twitter post (preview truncates the L3 part).
16MB unified L3 from 4MB per CCX should improve ST perfomance a lot (on top of other Zen 3 gains). It also IMO hints at 7NP or 7N+ as otherwise such a cache increase could negatively affect battery life (especially as it also as higher base-clocks).

An interesting review would measure the Igp performance by the bandwidth savings of the cpu cache...

 

[LightningZ71]

I doubt that the enlarged cache I'd directly responsible for much of a change in iGPU performance. In essence, from what I've read and seen, the iGPU is responsible for 90+% of the memory reads on the controller while gaming. Texture churn is huge, which is why modern cards have such massive memory throughput. I'm firmly in the camp that it makes a big change for the cpu side of things, but not as much for the iGPU.