So, straight off..
For 22FDX, 1.5x frequency gain does not require body biasing or increased voltage scaling for the e-suffix Stoney Ridge designs.
A9-9420e -> 2.7 GHz @ ~1.0v VID to Future design => 4.05 GHz @ ~1.0v VID to ~0.9v VID
A6-9220e -> 2.4 GHz @ ~1.0v VID to Future design => 3.6 GHz @ ~1.0v VID to ~0.9v VID
E2-9000e -> 2.0 GHz @ ~0.9 VID to Future design => 3.0 GHz @ ~0.9v VID to ~0.8v VID
In this case, ABB can be used to go even further for increased leakage(10W to 25W TDP) or to clamp down on power(sub-6W TDP).
With the CPU core however, AMD/GF would most likely target two post-Excavator style of designs:
- First is Migration, Optimization, Minimal Redesign => Ex: Piledriver -> Steamroller -> Excavator
- Second is a full Redesign => Ex: Bobcat -> Jaguar -> Zen
Either way we get a new core with a new name on a new process. Of the process which has three major nodes: 22FDX, 12FDX, 7FDX. 7FDX is in advanced pathfinding and isn't officially licensed, trademarked, restricted by GlobalFoundries yet.
With the first, the design remains dual-core and gets the above frequencies.
With the second, the design goes quad-core and gets the median of old and new frequencies:
FD2A => 3.375 GHz boost for quad.
FD2B => 3 GHz boost for quad.
FD2C => 2.5 GHz boost for quad.
With dual-core boosts probably peaking out as the above via ABB.
Either 22FDX design will definitely drop certain Stoney Ridge IP for Raven Ridge IP;
Infinity Fabric, Display Controller Next, Video Codec Next, the Sensor Hub, etc.
On the two major interconnects...DDR PHY and PCIE PHY. We should be looking at PCIe 5.0 and DDR5.
DDR5 mainly for the wide salvage zone: 3200 MHz to 6400 MHz is 3.2 GHz wide. Where as 2400 MHz to 3200 MHz is 0.8 GHz wide. So, DDR5 will quickly become cheaper than DDR3 and DDR4, simply because of frequency salvaging.
PCIe 5.0 support is mostly for switches and not for direct connections. For example: 4x PCIe 5.0 to 4x 2-lane PCIe 4.0 to 4x 4-lane PCIe 3.0 to 4x 8-lane PCIe 2.0 to 4x 16-lane PCIe 1.0, etc.
The SoC would be a wide-utility application processor. Thus, the possibilities are only limited by the designers who want to use it.
On the side: 22FDX is aggressively pointed at dual-core. 12FDX is aggressively pointed at quad-core.
Also:
https://i.imgur.com/v1cwaGO.png
v0.2 PDK 12FDX in October 2018. Compared to 22FDX v0.2 in April 2016 and v1.0 in Q1 2017.
Given that info, then 12FDX will be ready in Q3 2019 for ramp.
// 22FDX => 14FDSOI 90CPP relaxed to 104CPP for Dense/Perf libs and 116CPP for Low-power libs
// 12FDX => 10FDSOI 64CPP relaxed to 78CPP? for Dense/Perf libs and 84CPP for Low-power libs
// 7FDX => 7FDSOI 46CPP/48CPP relaxed to 56CPP? for Dense/Perf libs and 64CPP? for Low-power libs
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