AMD Bristol/Stoney Ridge Thread

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amd6502

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I do not expect to see v1 big.Little or v2(DynamIQ) big.Little in any of the FDSOI nodes. Zen will stay on FinFETs/NextGen(Nanosheets), and designs that use CMT will stay on planar(FDSOI).

Zen races for desktop to HPC. High TDP/High Frequency/Big IPC focus
// Maintain TDP or increase TDP to get higher IPC to Frequency gains.
This core races for fanless to laptops. Low TDP/High Frequency/Big EPI focus
// Extends from Steamroller 35W -> Excavator 15W -> This core 7.5W
Wow, very informative. I kind of worry if they don't join the big.little crowd it could count against them for not having that feature. Also, amd pioneered the heterogenous computing idea and then seemed to have dropped it some years ago while arm plows ahead https://community.arm.com/processors/b/blog/posts/where-does-big-little-fit-in-the-world-of-dynamiq

I have little doubt that XV on an advanced 22FDX would be very perf/watt competitive at sub 10w---even without a next gen modification. I think they could easily do sub 10w for quadcore with L2 halved from BR's 2MB.

For the other performance end (DT+HPC) they could still mix planar with finfet cores for certain MCM products using their 8c/16t 7nm zen2 chiplet (if they ported a controller chip to planar). In fact, a small 22nm controller module and small iGPU for the consumer DT and mobile APU seems to make good sense, although with 16 threads I don't know if would make too much sense to mix in 4 XV or 8 puma cores (if they binned all the reject 4 core+below chiplets for consumer, then with 8 zen threads it almost would make sense to add those 4 to 8 little threads; but maybe not, and they just add an aSMT mode).
 

NostaSeronx

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NTMBK

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WHY ON 28 NM?

Why not trying a new uARCH with Stoney with 22 or 14 nm???
If they made a 14nm part they would use Zen. This was just cranked out for minimal investment so that AMD can make a quick buck.
 

NostaSeronx

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New microarchitecture would not be Stoney.

22FDX/12FDX is likely to be the next cluster-based multithreading nodes.

My most current calc for the new core is:
- Front-end from Zen (L1i is 64 KB)
- Back-end from Zen (L1d is 32 KB and LSU from Zen)
- Cache-unit from Zen (512 KB L2 cache)

What has changed is the modification of the cores and FPU. Which are two cores/two FPUs. My speculation of those are:
2x L0i @ 8 KB
2x Single Rename Map(Int & FP)
2x Unified Scheduler Int
2x Unified Scheduler FP
2x Networked Int PRF (Bypass architecture from Zen), No EX/AGLU clusters, EX0/EX1/AGLU0/AGLU1 are their own units.
2x Clustered FP PRF (Bypass architecture from Zen/Jaguar), maximum capabilities is 2x 128-bit FMAC(high CPI for low EPI)
2x L0d @ 4 KB, Inside the core and is interconnected to the SLAQ(Store-Load Allocation Queue)/StLF(Store-to-Load Forwarder)/LCU(Load Convert Unit)

If anything it hints more towards it being 12FDX. Reduced port complexity from 14FF to 12FDX. The timetable for 12FDX for top tier companies is full year revenue in 2020. With 12FDX tapeouts happening before Q4 2019.
 
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Abwx

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NTMBK

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Abwx

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But are there actually any silicon changes, or is this just improved firmware/drivers?
The driver can enable the functionality only if it is there materialy, video codec is hardware implemented, meaning that there are specific computations that are done by the UVD and related to the video format requirement, FI a new video algorithm can require more capability for a given serie of math ops, at this point dunno if a firmware update could be enough, more likely a tiny computation unit within the UVD was silicon updated.
 

NostaSeronx

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The CPU cores have seen some tuning for low-power operation, and the IGP's video block has been updated for modern formats, but otherwise they're unchanged.
The A6-9220c/A4-9120c are the same as the A9-9420e/A6-9220e. There is no tuning for low-power operation, as that was done in the e-suffix SKUs. The IGP block of Stoney already supported H.264/H.265 decode and it doesn't support VP9. The only hardware that supports fixed function VP9 is Raven/Picasso.

The more funny bit, is that they forgot they added 10-bit support to Stoney! HDR AVC/HEVC is the decode capability of Stoney.

The IP however supports this on decode UVD/VCN:
H.264/VP8 <-- VP8 is disabled for some reason.
H.265/VP9 <-- UVD6 has it disabled and VCN has VP9 crippled.
 
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Abwx

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The IGP block of Stoney already supported H.264/H.265 decode and it doesn't support VP9. The only hardware that supports fixed function VP9 is Raven/Picasso.


The more funny bit, is that they forgot they added 10-bit support to Stoney! HDR AVC/HEVC is the decode capability of Stoney.

The IP however supports this on decode UVD/VCN:
H.264/VP8 <-- VP8 is disabled for some reason.
H.265/VP9 <-- UVD6 has it disabled and VCN has VP9 crippled.
You should read the articles before making wild claims...



https://www.anandtech.com/show/13771/amd-ces-2019-ryzen-mobile-3000-series-launched
 

Shivansps

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NostaSeronx

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amd6502

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The A6 looks nice given the 6w tdp but the A4 is really pushing the limits and would be better used as as 10w part with less anemic frequencies.

I like the rebranding as A9 really was number inflated badly from the start.
 

amd6502

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Maybe inherited from BR.

Would it be possible to configure SR and BR to run as dGPU rather than APUs? They seem quite capable. I wouldn't have guessed they could drive 3 displays.

Each of these processors supports the following display modes:

- DVI, 1920x1200 at 60 Hz
- DisplayPort 1.2a, 4096x2160 at 60 Hz (FreeSync supported)
- HDMI 2.0, 4096x2160 at 60 Hz
- eDP, 2560x1600 at 60 Hz

Technically the processor will support three displays, with any mix of the above. Analog video via VGA can be supported by a DP-to-VGA converter chip on the motherboard or via an external dongle.

For codec support, Bristol Ridge can do the following (natively unless specified):

- MPEG2 Main Profile at High Level (IDCT/VLD)
- MPEG4 Part 2 Advanced Simple Profile at Level 5
- MJPEG 1080p at 60 FPS
- VC1 Simple and Main Profile at High Level (VLD), Advanced Profile at Level 3 (VLD)
- H.264 Constrained Baseline/Main/High/Stereo High Profile at Level 5.2
- HEVC 8-bit Main Profile Decode Only at Level 5.2
- VP9 decode is a hybrid solution via the driver, using CPU and GPU
https://www.anandtech.com/show/11669/amd-releases-bristol-ridge-to-retail-am4-gets-apus

In any case, Stoney will have to do for most or much of 2019 for the very lowest end.

On a different note, it looks like Ryzen 3 mobile has a year's worth of Raven Ridge die salvage, mixing (non-native) dual core 14nm into the otherwise 12nm mobile APU product mix.


No signs of BR-L nor RR-L yet. I do think 22FDX would be perfect for BR-L and, if these are high volume, a good thing for the GF WSA too.
 

Abwx

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On a different note, it looks like Ryzen 3 mobile has a year's worth of Raven Ridge die salvage, mixing (non-native) dual core 14nm into the otherwise 12nm mobile APU product mix.
Notably, AMD indicates that the two dual-core APUs are fabbed on GlobalFoundries' 14nm process rather than the 12nm process of their cousins. We asked AMD about this, and the company confirmed that these chips have all the same refinements and improvements—whatever those may be—despite being fabricated on the older process. That is to say, they're new silicon, not harvested older chips.

https://techreport.com/review/34364/amd-announces-its-second-generation-ryzen-mobile-processors
 

amd6502

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Same refinements is pretty vague. Could mean the gpu and cpu support the same instructions. (The GPU portion should have the same refinements as it's the same Vega cores. Zen1 from RR and Zen+ are similar, both are revisions of Zen 1.0 . If this is Picasso-L there would be Zen+ if it's RR-L then it would be Zen1.)

If it is a new die then I'd expect details at CES. We'll eventually also see details on the dual core such as the stepping. It would be nice if a laptop reviewer can take the heatsink off to see what's under the 3200u or Athlon 300u.

Personally I'd much rather see another XV APU with 4 threads than a 2c/4t native die. With the large volume of quadcores in mainstream APUs it seems they can make a decent number of 2c/4t from salvage, and supplement the rest with XV APUs, assuming they come out with another generation after Stoney.
 
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krumme

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Interesting discussion guys. If those 2c Athlon 14nm are a new smaller die it's surely next years Chromebook cpus. My vote is still on salvaged chips though :)
4c Zen is 210mm2 and it's way to expensive. They need to go down to the stoney ridge 125mm2 range.
 

ET

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Same refinements is pretty vague.
Probably refers to power saving refinements, which was the purpose of Picasso. Would be nice if there's also other stuff, but I'd guess the majority of changes have to do with that.

Even if that's the only thing, it's still pretty important. These 2c/4t chips could make their way into low cost thin and lights and good battery life is important there.
 

NostaSeronx

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On the 22FDX side:
DDR5 is supported and supports these speed bins for now: 3200 Mbps, 3600 Mbps and 4000 Mbps
PCIe 5.0 is draft supported.
HDMI 2.1 is supported.
- With the current PHY and Controller as far as three months ago?

Logic libraries that AMD could use:
9T => 600 mV Vddnom // Fast TTM
8T => 650 mV Vddnom // Average PPAC
7T => ??? mV Vddnom // Best PPAC

The downloads for 22FDX/12FDX for Mobility(Laptops, Tablets, Smartphones, other devices with RF) involve top tier:
AMD, Qualcomm, Unisoc(Spreadtrum), HiSilicon, MediaTek, Rockchip

Anything TSMC 28nm or GlobalFoundries 28nm is liable to have a 22FDX upgrade by the end of 2019.
 

dark zero

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So, Bulldozer is not dead?
No please, no!
 

amd6502

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On the 22FDX side [....]

Anything TSMC 28nm or GlobalFoundries 28nm is liable to have a 22FDX upgrade by the end of 2019.
Geez 22fdx isn't ready yet and not till end 2019; it seems like it should've been ready 2017/2018 according to some of the info floating around. https://www.semiwiki.com/forum/content/6475-iedm-2016-globalfoundries-22fdx-update.html

In 2015 22FDX was still in development, this year [end 2016] 22FDX is getting ready to ramp.
I don't get what AMD's waiting for; it's ready (?), it's very low project cost, and it's similar to the old familiar 28nm soi.
 

NostaSeronx

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I don't get what AMD's waiting for; it's ready (?), it's very low project cost, and it's similar to the old familiar 28nm soi.
I think it is the ole 28SHP scenario. AMD didn't go 28LP/28HP, they didn't go 28SLP/28HPP, they went 28SHP.

WAYTOGO FAST is the parallel pursuit of innovative developments within the FDSOI ecosystem.
=> Front 2: Development of enhanced performance FDSOI technology (14FD+) at ST’s pilot line.
=> Performance boosters developed for the 14FDSOI and the 14FD+ have started to be reengineered to be applied to the 28FDSOI Derivatives : the gate stack change : from HfSiON to HfO2, the dual workfunction gate metals, the SiGe channel for the PMOS, the Low k spacers integration.

Then:
=> Front2 with GlobalFoundries:
In this project the SOI substrate technology blocks for 22FDX technology and 22FD+ were developed. Substrate Pilot line was qualified by GlobalFoundries and the targets for quality & quantity were reached.

For extra context:
28FD+ and 22FDX are derived from 14FD
With 22FDX+/22FD+ being derived from 14FD+.
However, 22FDX already had boosters from 14FD&14FD+. So, 22FD+ must have more stuff, possibly from 10FD. As the 10FD node has been split into three nodes; 10FD, 7FD Gen1, 7FD Gen2.

22FDX+ would be using 10FD boosters
12FDX would be using 7FD Gen 1 boosters.
Gate-last(RMG or Gate-first FMG) and sSOI/SGOI isn't set till 7FD Gen 2.
Geez 22fdx isn't ready yet and not till end 2019; it seems like it should've been ready 2017/2018 according to some of the info floating around.
Most of 22FDX demand is from China. As well as all mobility SoCs are planned for Chengdu, not Dresden. Automotive, Industrial, and Government tasks are slotted for Dresden. Singapore is targeting the High-Voltage 22FDX and the modified HR-UTBB 22RF node. Malta/Fishkill is aiming for 3D stacked SRAM/DRAM aka 22FDX for Networking/Datacenters/Aerospace.

With the death of 7LP the foundry is a complete mess. GloFo is throwing everything at 22FDX/12FDX. Mainly, because the FinFET nodes didn't allow them to get the net profit to satisfy the owners. No matter the capacity of FinFET, it will not net a profit. However, there is hope for 22FDX/12FDX to net profit. Which is why the huge push in the above segment, all 300mm are being tooled to do 22FDX.
 
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