• Guest, The rules for the P & N subforum have been updated to prohibit "ad hominem" or personal attacks against other posters. See the full details in the post "Politics and News Rules & Guidelines."

AMD Bristol/Stoney Ridge Thread

Page 59 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

NostaSeronx

Diamond Member
Sep 18, 2011
3,231
759
136
Note the mention of graphics in there. This is designing cores that are embedded into the GPU, not a standalone CPU product.
I think that implies beyond just developing RISC-V CPU work, it might move towards other RISC-V implementations of GPU/NPU/PSP/ACP/etc.

The mention of graphics includes stuff like RV64X[X extension of V extension]/Simty. The mention of compute includes a RVV co-processor in the vein of Centaur's NPU, etc.
Note the distinction between CPUs and Processors:
  • Work with a team of architects for developing new innovative embedded RISC-V CPUs.
  • Understand and improve existing and emerging graphics/compute paradigms and new APIs employing RISC-V Processors.
Now take note of this Think Silicon's related quote: "The usage of a common ISA between the main system CPUs and GPUs will allow new programming paradigms by dynamically balancing computation load between these processing elements."

Today: CPU+Graphics+Compute => Physically Unified(on the same die) yet Logically Separated(Differentiated programming model, unique compilers, multiple instruction sets)
Tomorrow: "+"+" => "(") and Logically Unified(Unified programming model, shared compiler, single instruction set)
 
Last edited:

NTMBK

Diamond Member
Nov 14, 2011
9,226
2,561
136
I think that implies beyond just developing RISC-V CPU work, it might move towards other RISC-V implementations of GPU/NPU/PSP/ACP/etc.

The mention of graphics includes stuff like RV64X[X extension of V extension]/Simty. The mention of compute includes a RVV co-processor in the vein of Centaur's NPU, etc.
Note the distinction between CPUs and Processors:
  • Work with a team of architects for developing new innovative embedded RISC-V CPUs.
  • Understand and improve existing and emerging graphics/compute paradigms and new APIs employing RISC-V Processors.
Now take note of this Think Silicon's related quote: "The usage of a common ISA between the main system CPUs and GPUs will allow new programming paradigms by dynamically balancing computation load between these processing elements."

Today: CPU+Graphics+Compute => Physically Unified(on the same die) yet Logically Separated(Differentiated programming model, unique compilers, multiple instruction sets)
Tomorrow: "+"+" => "(") and Logically Unified(Unified programming model, shared compiler, single instruction set)
Nah, this is the same as Nvidia replacing their FALCON embedded core with a custom RISC-V one. Tiny cores that handle data flow, power management etc within the GPU are moving over to RISC-V so that they can benefit from the software ecosystem and don't need to write their own compilers etc.
 
  • Like
Reactions: amd6502

NostaSeronx

Diamond Member
Sep 18, 2011
3,231
759
136
Nah, this is the same as Nvidia replacing their FALCON embedded core with a custom RISC-V one. Tiny cores that handle data flow, power management etc within the GPU are moving over to RISC-V so that they can benefit from the software ecosystem and don't need to write their own compilers etc.
However, that relates to security/systems not graphics/compute.

Falcon and NV-RISCV processor => systems and security
Systems => Debug ucode, temperature, etc
Security => Tegra Security Processor, secure driver context switching, etc.

None of which touch upon existing and emerging graphics/compute paradigms => HLSL/GLSL/SPIR-V or new APIs beyond => DirectX/OpenGL/Vulkan.

Unless, AMD plans to remove hardware features from their graphics ISA/HW. There is no reason to have RISC-V microcontrollers where Nvida places them.

Nvidia:
What will be done:
  • Support development of (bare metal) firmware run on embedded microcontrollers within Nvidia GPUs.
  • Collaborate with the hardware and software teams to architect new features and guide future development.
  • Optimize software to improve system robustness, performance and security.
  • Participate in testing new and existing firmware.
  • Perform system bring-up, debug, and validation.
  • Ensure compliance to functional safety standards (ISO 26262 and ASPICE). This includes defining requirements, architecture and design with end-to-end traceability, performing safety analyses - FMEA/DFA/FTA and ensuring code compliance to MISRA and Cert-C standards.
What we will need to see:
  • Familiarity with computer system architecture, microprocessors, and microcontroller fundamentals (caches, buses, DMA, etc).
If such a project existed, I would suspect similar language to above. Rather than firmware development, it would be hardware development.

For Example: Systems Design Engineer for AMD:
Key Responsibilities
  • Develop and execute feature verification, enablement, and test plans for SOC power and performance management features
  • Develop firmware functions and features for embedded microcontrollers in CPU/GPU
  • Debug, troubleshoot system-level issues related to power and performance features
  • Prototype innovative ideas and designs
  • Support test automation infrastructure and develop test scripts
  • Proactively drive continuous improvement in all areas of activity
Looking at other occurrences of AMD CPU Design Engineers, they do in fact work on CPU cores.

=> RISC-V CPU in the vein of a microprocessor not a microcontroller, which targets central processor functions. (Ex List: K5/K6/K7/K8-10h/K9^1/Bobcat/Bulldozer/Jaguar/Zen^1/etc)
=> RISC-V Processor in the vein of a microprocessor not a microcontroller, which targets graphical/computational functions. (Ex List: GCN/RDNA/CDNA)
 
Last edited:

NTMBK

Diamond Member
Nov 14, 2011
9,226
2,561
136
However, that relates to security/systems not graphics/compute.

Falcon and NV-RISCV processor => systems and security
Systems => Debug ucode, temperature, etc
Security => Tegra Security Processor, secure driver context switching, etc.

None of which touch upon existing and emerging graphics/compute paradigms => HLSL/GLSL/SPIR-V or new APIs beyond => DirectX/OpenGL/Vulkan.

Unless, AMD plans to remove hardware features from their graphics ISA/HW. There is no reason to have RISC-V microcontrollers where Nvida places them.

Nvidia:
What will be done:
  • Support development of (bare metal) firmware run on embedded microcontrollers within Nvidia GPUs.
  • Collaborate with the hardware and software teams to architect new features and guide future development.
  • Optimize software to improve system robustness, performance and security.
  • Participate in testing new and existing firmware.
  • Perform system bring-up, debug, and validation.
  • Ensure compliance to functional safety standards (ISO 26262 and ASPICE). This includes defining requirements, architecture and design with end-to-end traceability, performing safety analyses - FMEA/DFA/FTA and ensuring code compliance to MISRA and Cert-C standards.
What we will need to see:
  • Familiarity with computer system architecture, microprocessors, and microcontroller fundamentals (caches, buses, DMA, etc).
If such a project existed, I would suspect similar language to above. Rather than firmware development, it would be hardware development.

For Example: Systems Design Engineer for AMD:
Key Responsibilities
  • Develop and execute feature verification, enablement, and test plans for SOC power and performance management features
  • Develop firmware functions and features for embedded microcontrollers in CPU/GPU
  • Debug, troubleshoot system-level issues related to power and performance features
  • Prototype innovative ideas and designs
  • Support test automation infrastructure and develop test scripts
  • Proactively drive continuous improvement in all areas of activity
Looking at other occurrences of AMD CPU Design Engineers, they do in fact work on CPU cores.

=> RISC-V CPU in the vein of a microprocessor not a microcontroller, which targets central processor functions. (Ex List: K5/K6/K7/K8-10h/K9^1/Bobcat/Bulldozer/Jaguar/Zen^1/etc)
=> RISC-V Processor in the vein of a microprocessor not a microcontroller, which targets graphical/computational functions. (Ex List: GCN/RDNA/CDNA)
I'm sure that they will work on a RISC-V CPU core! I'm also sure that it will never be accessible to end users.
 

NostaSeronx

Diamond Member
Sep 18, 2011
3,231
759
136
I'm sure that they will work on a RISC-V CPU core! I'm also sure that it will never be accessible to end users.
Again, RISC-V CPU and processors are not RISC-V Microcontrollers. So, the given hiring statement is for a RISC-V project of a CPU. Which is in the vein of the CPU cores in such products as Athlon, Sempron, Duron, FX, Ryzen, Geode, etc.

If AMD was going for RISC-V microcontroller, they would state it. It also wouldn't be a CPU Design Engineer position either.

So, it is definitely a RISC-V CPU core, which will be accessible to those who buy it. With absolute access to a more open BDKG/PPR/etc than x86/ARM cores from AMD.

Premium => Proprietary (orientated towards premium closed-source firmware/microcode // NDA requirement)
Value => Libre (orientated towards free open-source firmware/microcode // No NDA requirement)

The mention of graphics/compute mostly comes from RISC-V capability of having hybrid CPU-GPU architectures. So, basically AMD RISC-V Core A is a traditional CPU, while AMD RISC-V Core B is a Scalar Processor of a larger Vector-focused RISC-V Graphics unit.

1. GlobalFoundries.
2. 22FDX/12FDX => AMD has already done 14LPP/12LP/etc. Malta is running down FinFETs for more mature processes like 90nm FDSOI, 45nm CLO/LPCLO (PDSOI/FDSOI), etc.
3. Needs to compete with or surpass upcoming solutions.

Allwinner/Pine => Really weak CPU, no GPU?
BeagleV => 2x/4x U74 (SiFive-licensed) + Imgtec B-series (4x32) <== Probably TSMC
PicoRio => 4x Low-end custom? RISC-V + Imgtec 7XE GE7800 (2x16) <== TSMC
HiFive Unmatched => 4x U74 + No GPU IP <== TSMC
T-head ICE soc => 2x C910 + 1x C910w/V-extentsion + 1x GPU core(unknown) <== TSMC

Thus, the lowest end RISC-V embedded processor at minimum to maximum must be within these.
Ontario/Zacate[Bobcat-class], Kabini/Steppe Eagle/Crowned Eagle[Jaguar/Puma-class], Brown Falcon/Prairie Falcon[Excavator-class]

Since, the competition of RISC-V in consumer/embedded SBC market is pretty weak.

2x RISC-V ULP CPU cores/ 4x RISC-V ULP CPU cores / 2x RISC-V HP-ULP cores
1x RISC-V GPU cluster / 2x RISC-V GPU cluster / 3x RISC-V GPU cluster

Embedded markets are shared with semi-custom. So, if on GloFo that means several added options RHBD-capability, RF-capability, 3rd party RISC-V IP, etc. More customers to GloFo through AMD's Value IP, rather than using AMD's Premium IP which has been mostly exclusive to TSMC anyway.

RISC-V + FDSOI and the lower costs and faster time to market. Should allow for several versions of such processors;
Drafts => Initial version; Boot, OS, Software development//Identify issues.
Candidates => Mid-timeline version: Addition of third-party IP//Second identification of issues.
Release => Frozen version: Compliant for end-user usage with frozen features.//Issues identified previously shouldn't be in here, etc.
OoO style => Draft v1 -> Candidate v1 -> Draft v2 -> Release v1 -> Candidate v2 -> Draft v3 -> Release v2 -> etc.
Which should allow for a similar launch style of yearly improved IP.
Ex: => https://www.sifive.com/blog/sifive-core-ip-20g1
and Beagle-V Later Version which switched out the Cadence Tensilica VP6 which is in the Early Version for a IMG BXE-4-32 MC4 GPU
^-- These later boards are expected to swap to a new SoC, trading out the VIC-7100 for the VIC-7110. This will be a quad-core SoC, with the aforementioned dedicated video hardware.


I went searching it seems to be a copy-paste with exact meaning:
AMD GPU Architect:
A self-motivated compute architect who is passionate about growing the efficiency of the GPUs. An effective teammate who focuses on collaboration, team building, mentoring, and further team success.
  • Work with a team of architects for developing innovative solutions in the field of graphics and compute.
  • Identify complex technical problems, summarize multiple simpler solutions, and help the team to make advances in PPA.
  • Understand the concepts of Performance/FLOP and Performance/Byte. Use these metrics as a vehicle to identify bottlenecks and solves them to increase the overall GPU efficiency.
  • Explore architectural innovation in fixed function, compute, and memory hierarchy.
  • Communicates ideas with other architects and managers on multiple sites.
Only needs =>
  • Knowledge of modern GPU architectures with an overall· 7+ years of experience in architecting GPUs.
Master or PhD degree with emphasis in Electrical engineering, Computer architecture, or Computer science preferred

AMD CPU Design Engineer 2:
A self-motivated CPU enthusiast. An effective team player who focuses on collaboration, team building, mentoring, and furthering team success.
  • Work with a team of architects for developing new innovative embedded RISC-V CPUs.
  • Identify complex technical problems, break them down, summarize multiple possible solutions, and help the team make advances in Performance, Power, and silicon Area (PPA).
  • Understand and improve existing and emerging graphics/compute paradigms and new APIs employing RISC-V Processors.
  • Work with subsystem architects to understand bottlenecks and other problems where an embedded processor will improve the performance.
Only needs => Master's degree preferred in EE and CE or Bachelor's degrees with 1 year of proven experience.

While sharing the GPU Architect position it appears to share more with a PMTS Silicon Design Engineer:
PMTS Silicon Design Engineer:
A self-motivated graphics enthusiast. An effective team player who focuses on collaboration, team building, mentoring, and furthering team success.
  • Work with a team of architects for developing new innovative algorithms in the field of graphics and compute for low power GPUs
  • Identify complex technical problems, break them down, summarize multiple possible solutions, and help the team make advances in Performance, Power, and silicon Area (PPA).
  • Understand and improve existing and emerging graphics/compute paradigms and new APIs
  • Work with subsystem architects to understand bottlenecks in low power graphics cores/SoCs
How to know it isn't a microcontroller positon;
Power Management Firmware Engineer:
AMD's power management design team is seeking an experienced Firmware Design Engineer to chip in to System Management, Power Management and Security firmware for AMD's APU, Server and dGPU products. This position offers a very good growth path in a highly visible role.
  • Assume ownership in development and/or verification of firmware crafted for an embedded microcontroller.
  • Work with HW design and verification engineers to verify firmware features
  • Contribute to architecture of hardware, firmware and power management features

I'll go through these one by one.
  • Work with a team of architects for developing new innovative embedded RISC-V CPUs.
  • Identify complex technical problems, break them down, summarize multiple possible solutions, and help the team make advances in Performance, Power, and silicon Area (PPA).
  • Understand and improve existing and emerging graphics/compute paradigms and new APIs employing RISC-V Processors.
  • Work with subsystem architects to understand bottlenecks and other problems where an embedded processor will improve the performance.
1. Work under(CPU DE2 is a very low position) a team of architects who are designing/developing a new RISC-V CPU.
2. Basically choose PPA options for a given process that the RISC-V CPU will be on.
Let say 22FDX:
Track Libs: 12T(UHP), 8T(ULP), 7.5T(ULL), 6.75T(AG1)
Types: SDB, DDB, CNRX, etc
ABB: FBB-orientated block, RBB-orientated block, or complex FBB/RBB double block.
etc.
3. Understand/Improve existing/emerging programming models/APIs in regards of employing RISC-V processors for graphics/compute.
4. Makes little sense, but it basically is stating if x86/ARM/GCN/RDNA/CDNA bottleneck and cause other problems identify if RISC-V processors will solve and improve performance.
 
Last edited:
  • Like
Reactions: Skoynay and amd6502

ASK THE COMMUNITY