AMD “Next Horizon Event" Thread

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CatMerc

Golden Member
Jul 16, 2016
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Had an amusing thought. If the I/O die really has a bunch of L4 cache, and they scale it between EPYC/Threadripper/AM4, that would mean Threadripper should have more L4 than AM4.
That would allow some games on Threadripper to outperform their AM4 counterparts core for core, clock for clock.

Would be first time in quite a while where the top end gaming CPU was also HEDT :p
 

moinmoin

Senior member
Jun 1, 2017
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Had an amusing thought. If the I/O die really has a bunch of L4 cache, and they scale it between EPYC/Threadripper/AM4, that would mean Threadripper should have more L4 than AM4.
That would allow some games on Threadripper to outperform their AM4 counterparts core for core, clock for clock.

Would be first time in quite a while where the top end gaming CPU was also HEDT :p
Threadripper 2 is already clocking higher than 2700X so TR3 having more L4$ than R 3xxx would be a given (if there's L4$ to begin with). Whether that makes it more suitable for (some) games we'll have to see.
 

beginner99

Diamond Member
Jun 2, 2009
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A small GPU to just drive the display for office work would open up more markets to them- massive piles of OEM office PCs, that all ship with Intel integrated graphics. Even a 3CU thing would do the job.
I do see the benefit but the chiplet must be designed including mask costs and the IO die capable of using it. I'm not sure AMD would make that many more sales to be worth it. And if Rome takes off, then they will be able to sell every single Zen2 chiplet the produce anyway.
 
Apr 27, 2000
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If distance does not matter the 2990WX says hi.
Distance alone matters little, but multiple hops between dice can impose other penalties. Compare the 2990WX to the 2950X and then consider what would happen if there were a few more millimeters between the dice of the 2950X and the memory banks.

The 2990WX suffers from forcing the two dice that have no direct access to system RAM to share a memory controller with a die that is presumably not completely idle itself.
 

Tuna-Fish

Senior member
Mar 4, 2011
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At 450mm2, the IO die is too much for anything other than Epyc, even on 14 nm.
The cost of putting a harvested chip that has a flaw that makes it not work for an EPYC onto a TR chip is 0, regardless of it's die size. TR is a small market compared to EPYCs. With 8 memory channels, 128 PCIe, and 8 IF links there should be enough broken EPYC IO dies that still have enough DRAM channels, PCI-E and IF to work just great as a TR.
 

NTMBK

Diamond Member
Nov 14, 2011
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I do see the benefit but the chiplet must be designed including mask costs and the IO die capable of using it. I'm not sure AMD would make that many more sales to be worth it. And if Rome takes off, then they will be able to sell every single Zen2 chiplet the produce anyway.
A dual channel northbridge with small GPU should be much smaller than the eight-channel northbridge for Epyc, and high enough volume to justify. Not like 14nm is that expensive.
 

jpiniero

Diamond Member
Oct 1, 2010
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Unlike 7 nm, 14 nm yields are good. I'm assuming that low end Epyc would be able to consume almost all of the defective IO dies.
 

Topweasel

Diamond Member
Oct 19, 2000
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Unlike 7 nm, 14 nm yields are good. I'm assuming that low end Epyc would be able to consume almost all of the defective IO dies.
Doubtful. AMD has been really keen on needlessly segmenting markets. AMD probably isn't going to sell EPYC's without full PCIe lanes or without full Memory lanes.
 

Tuna-Fish

Senior member
Mar 4, 2011
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Unlike 7 nm, 14 nm yields are good. I'm assuming that low end Epyc would be able to consume almost all of the defective IO dies.
Low end EPYC cannot consume many of the defective IO dies. For the very simple reason that lower-end EPYC reduces core counts, and possibly cache, but not PCI-E lanes or memory channels. Every single EPYC1 out there has support for 8 channels of DRAM and 128 PCI-E lanes, and AMD is not likely to change this for EPYC2.

And why would they when they have a perfectly good product already on the roadmap that can take them? That is, Threadripper.
 

jpiniero

Diamond Member
Oct 1, 2010
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Every single EPYC1 out there has support for 8 channels of DRAM and 128 PCI-E lanes, and AMD is not likely to change this for EPYC2.
That's what I'm saying; I think they will. Unlike the desktop I think there's room in servers for AMD to really stick it to Intel without compromising sales at the higher end. And the defective IO dies would be a part of that.
 

Topweasel

Diamond Member
Oct 19, 2000
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There is a perfect already made market for these dies. Why would you assume AMD needs another?
 

CatMerc

Golden Member
Jul 16, 2016
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Depends on Threadripper volumes.

If for example they sell a lot of TRs, the cost savings by having more dies per wafer could tip over the balance Vs taking defective dies. That's why Intel tends to make a lot of small consumer dies (8c/6c/4c/2c are all different), because at their volumes it makes sense.
 

moinmoin

Senior member
Jun 1, 2017
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I'm toying with the possibility that Ryzen chips will contain two chiplets allowing AMD to bin every single core on them for maximum possible frequency. Also there no longer be CCX structures that could have unbalanced structure if not equally gated (name previously proposed for the chiplets was CCD) with IOC managing the balancing regardless of the physical layout and actual number of cores on every chiplet.
 

Topweasel

Diamond Member
Oct 19, 2000
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Depends on Threadripper volumes.

If for example they sell a lot of TRs, the cost savings by having more dies per wafer could tip over the balance Vs taking defective dies. That's why Intel tends to make a lot of small consumer dies (8c/6c/4c/2c are all different), because at their volumes it makes sense.
Volume has to match or exceed the cost of designing a new chip, testing, converting and dedicating production lines to it. Intel basically always has a garuntee that any die they make will sell between 5-10 million a year. It makes the money saved on silicon worth the R&D costs.

AMD on the other hand had to make one chip that scaled from $100-$4500. I doubt there will be more than 2 IO chips and I doubt TR gets one of it's own and I doubt that AMD will offer buss and memory limited versions of EPYC, it's one of the big selling points is gobs of both at any price level. TR also won't get it's own because it doesn't sell nearly enough to "tip the favor". It doesn't for Intel, why would you imagine it would for AMD?
 

CatMerc

Golden Member
Jul 16, 2016
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Volume has to match or exceed the cost of designing a new chip, testing, converting and dedicating production lines to it. Intel basically always has a garuntee that any die they make will sell between 5-10 million a year. It makes the money saved on silicon worth the R&D costs.

AMD on the other hand had to make one chip that scaled from $100-$4500. I doubt there will be more than 2 IO chips and I doubt TR gets one of it's own and I doubt that AMD will offer buss and memory limited versions of EPYC, it's one of the big selling points is gobs of both at any price level. TR also won't get it's own because it doesn't sell nearly enough to "tip the favor". It doesn't for Intel, why would you imagine it would for AMD?
Didn't say it will, I said why such a decision would be taken if it was, using Intel as an example.
 

Topweasel

Diamond Member
Oct 19, 2000
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Didn't say it will, I said why such a decision would be taken if it was, using Intel as an example.
I understand that but again the volume Intel ships in allows them that freedom. AMD is still years a way and may never get there because they will be beholden to others to fab their chips.
 

Shivansps

Platinum Member
Sep 11, 2013
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Imagine placing 1 CPU die and 7 GPU dies and sell it as something like a Xeon Phi.
 

moinmoin

Senior member
Jun 1, 2017
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I understand that but again the volume Intel ships in allows them that freedom. AMD is still years a way and may never get there because they will be beholden to others to fab their chips.
I personally find stating "AMD is beholden to others for fabbing while Intel isn't" quite funny in the context of Intel for years being stuck to 14nm for not managing to get their 10nm process up and running. Obviously both approaches have advantages and disadvantages.
 

Topweasel

Diamond Member
Oct 19, 2000
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I personally find stating "AMD is beholden to others for fabbing while Intel isn't" quite funny in the context of Intel for years being stuck to 14nm for not managing to get their 10nm process up and running. Obviously both approaches have advantages and disadvantages.
This isn't to give either a hard time. Just Intel when they are producing CPU's they have near limitless output (Of course you can make a Die so large, with so bad of yields, for a CPU you need 2 of them for and bring that manufacturing to it's knees).

AMD as noted would need a tipping point. A sales amount of TR that would provide AMD profit for developing and having manufactured a dedicated IO die for TR. That means that not only would AMD have to sell a but load of TR's to hit that point, it would be on top of Ryzen, Ryzen APU (in 2020), and EPYC cpu's, and Even Radeon's. TSMC will have a lot of capacity. But AMD won't be their only customer (like they practically are for GloFo). They are already going to be working against Apple and eventually Nvidia. So while it would be the greatest problem for AMD to have I doubt TSMC can supply enough dies to AMD to cover not only TR being large enough to get it's own IO chip but the supply for all the other dies needed for the rest of their lineup.
 

Veradun

Senior member
Jul 29, 2016
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I doubt TSMC can supply enough dies to AMD to cover not only TR being large enough to get it's own IO chip but the supply for all the other dies needed for the rest of their lineup.
Interesting point. Will they finally differentiate SKUs before assembly?

I mean, they can use just 4 chiplet and a salvaged motherchip for TR, but also for low end EPYC they can use full motherchip with less chiplet for the sake of segmentation.

The big question is will they this or just assemble everything as full packages like they do now?

Since they will have the contention on capacity you just mentioned I think this would greatly help even if it will cost some more on packaging/sorting/inventory.
 

moinmoin

Senior member
Jun 1, 2017
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This isn't to give either a hard time. Just Intel when they are producing CPU's they have near limitless output.
Their 14nm output doesn't seem that limitless. And all that possible 14nm output won't help them getting any competitive 10nm/7nm output for which they still need to build up the capability, both at all and then on an equally large scale. Once AMD's 7nm chips reach the market Intel for the first time ever will be confronted with the pure-play foundries as direct competitors that the insane mobile market grew. And unlike with Intel for the pure-play foundries further node development doesn't depend on the success of a (comparably) small scale x86 industry.
 
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teejee

Senior member
Jul 4, 2013
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Interesting point. Will they finally differentiate SKUs before assembly?

I mean, they can use just 4 chiplet and a salvaged motherchip for TR, but also for low end EPYC they can use full motherchip with less chiplet for the sake of segmentation.

The big question is will they this or just assemble everything as full packages like they do now?

Since they will have the contention on capacity you just mentioned I think this would greatly help even if it will cost some more on packaging/sorting/inventory.
Maybe I misunderstand your question but I'm pretty sure AMD/TSMC does wafer testing, is it this you're asking about?
https://en.m.wikipedia.org/wiki/Wafer_testing
 

moinmoin

Senior member
Jun 1, 2017
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Veradun

Senior member
Jul 29, 2016
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Maybe I misunderstand your question but I'm pretty sure AMD/TSMC does wafer testing, is it this you're asking about?
https://en.m.wikipedia.org/wiki/Wafer_testing
What I mean is they have 4xZeppelin Threadrippers out there even now and even when they completely disable two Zeppelins. So the question is if they are going to differentiate assembly, this time, or continue to always package the same stuff even when disabling full dies (it is a given TR3 won't be 64c/128t, right?)
 


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