-
We’re currently investigating an issue related to the forum theme and styling that is impacting page layout and visual formatting. The problem has been identified, and we are actively working on a resolution. There is no impact to user data or functionality, this is strictly a front-end display issue. We’ll post an update once the fix has been deployed. Thanks for your patience while we get this sorted.
Info 64MB V-Cache on 5XXX Zen3 Average +15% in Games
Page 44 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.
Could be thicker. I was just going by number given by TSMC demonstration of 600 um for 12 layers. It is probably not necessary to go all the way down to 50 um if all AMD is going to be offering this time around is a single layer.
I've no doubt he's correct, but you should definitely not read too much into it. AMD can bump clocks on current chips below the 5900x by at least 10% without a stepping. I doubt they will do that, instead they will realign everything and release new models when the time comes.
Is it the top die that is really thin or the bottom die, or both, I guess? To make TSVs, they etch deep holes into the cpu wafer and fill them with metal. Then the wafer is flipped over and they polish it down sufficiently to expose the TSVs that were etched from the other side. If it is micro-bump based, I think they apply the micro-solder balls to the whole wafer using photolithography techniques. “Mechanically shaving” probably does’t describe it that well; it is a polishing process. A quick google search says 10 to 200 um for the TSV depth; I don’t know what TSMC uses. If the cpu wafer is 700 um thick, then they need to polish off around 500 um of the base cpu die to meet the same height requirement as the non-stacked die. In that case, the cache die may actually be thicker for a single stack. They would need to be a lot thinner for a 4 stack device with the same height.
It is the top die that is very thin. Which is the height that the bottom die would need to be reduced by, in order to maintain the same height.
For SoIC, hybrid bond, there would not be any micro-bumps. As far as we know, AMD is not planning on using micro-bumps for stacking, mainly because SoIC hybrid bond is a generation ahead of it.
As far as TSV depth, I am not sure from which side they are counting. If it is 10-200 um from the top die, it means that TSMC would be shooting for 10um end so that more than enough of the TSV is exposed by polishing off the 50 um from the top.
But TSMC / AMD don't necessarily have to shoot for the thinnest die, since on Zen 3, we may not necessarily see more than 1 level.
It seems that going from 0 to 1 layer is hard, going from 1 to 2 is hard, but then going from 2 to more layers would just re-use the same technique that was used in going from 1 to 2.
Edit: I was wrong. In this AMD video, they show that it is the core die that is shaved to the thinnest height, they said 20 um:
Last edited:
Yes, that is how it has to be. The depth of the TSV etching is likely a big component in yield of TSVs. The 200 micron figure is likely extreme. It sounds like 10 to 20 micron thickness for the base die might be more common, but the cache die are supposed to be something like 50 micron. A wafer is like a sheet of paper at that thickness.
The single layer is very easy since the top cache die doesn’t actually need any TSVs. It would basically be a flip-chip. They make the cache die with the contacts to connect to the cpu die TSV on the top. Then they flip it over for mounting on top of the cpu die. The cpu die has the TSVs, so it is more complicated.
For more than one stack high, they have to make the cache chips with TSVs also. They may already need to polish the single stack cache die down a bit to reach height requirements, but no TSVs are needed in the cache die. For stacking more than 1 cache layer, the cache die needs to have TSVs and those in middle of the stack will need to be polished down to expose the TSVs. The top die could technically be thicker, but thinner than the current top die if they want to maintain the same height without fillers. I guess they might have 3 thicknesses of top cache die: 1 for single stack, one for 2 stacks, and one for 4 stacks. It likely isn’t difficult to make different thicknesses. The wafers would be the same otherwise, just different amounts of polishing. I don’t know if a thicker die on top is needed for mechanical stability or other reasons. Thinner is better for thermals, but it might be very delicate or have other trade offs.
So, if I have this correct, going from 0 to 1 requires a simple cache die but a lot more complexity on the cpu die side since it has to go through a deep etching and deposition process to make the TSVs. The cache die is simple with no TSV processing required. To go more than 1, a lot more work is required on the cache die in both design and processing. They have to design the die to have TSVs for pass through to up to 4 layers above (edit: 3 layers above the cache die, but the cpu die may need more work also for the added pass through TSVs to all 4 layers). That isn’t just signals; they need to get power delivery through TSVs also. That likely required a lot of power and ground TSVs coming from the base die into the stack. I wouldn’t be surprised that there would be another stepping of the cpu die to get more than one high stack working. This has been done before in HBM stacks, but I believe those were done using micro-solder ball connections which are much larger. DRAM also takes very little power compared to SRAM, so getting that through tiny TSV connections is likely new territory.
edit: after re-reading this, I still don’t know if we are on the same page. TSVs are made by etching deep holes into the wafer and filling with metal. They then do standard processing; device layers and multiple metal layers. Once that is complete, they flip the wafer over and polish it down from the original bottom to expose the TSVs that were created from the original top. The depth of the TSV would be how deep the holes were etched from the original top of wafer. The wafer then has to be thinned from the original bottom to expose the metal TSVs. Any die that is stacked (including the base die), unless it is at the top of the stack, must be very thin, limited by the TSV hole etch depth (seems to be <200 microns, and possibly 20 to 50 microns for AMD v-cache parts).
Last edited:
Markfw
Moderator Emeritus, Elite Member
Why do you keep talking about Zen 3d/v-cache non-launch. It has not been scheduled, its not a non-launch.
AtenRa
Lifer
A few remarks,
3 Intel sockets vs one AM4
5800X at number one spot after prices were fallen the last weeks
5600G/5700G high percentage of sales due to GPU prices ??
12700K best high end CPU, sales could be higher if cheaper Motherboards were available (B660, H610 etc)
DrMrLordX
Lifer
It's not even clear if AMD will bring Zen3D/Vermeer-X to market. At all. They teased some theoretical performance gains from the massive L3 cache die, but they never actually said they would sell it. The only thing we know for sure is that Milan-X does exist and has for some time now.
Best as in best-selling? 5900X sold more units. But yeah I think 12600k and 12700k could sell better with a better selection of motherboards. Right now, nearly every LGA1700 board has a VRM built for a 12900k. Not great for the budget shopper.
Some dude said days before that they started testing V-cache cpus, and guessed to be released in early Feb
leoneazzurro
Golden Member
And this will continue to be. Even with B6XX motherboards, because they have to satisfy the requirements of the most hungry CPU supported. Yes, in the future motherboard makers could cut something in the VRM department by sticking to the nominal specs and thus not favoring oveclocking. On the other side, the nominal specs must take in account the 12900K, so the minimum bare limit cannot be set too low.
uzzi38
Platinum Member
That's the same person as Greymon on Twitter btw.Some dude said days before that they started testing V-cache cpus, and guessed to be released in early Feb
translated:
DrMrLordX
Lifer
That'd be awesome if true. It's not like Fugger from XS has a QS overclocked and running at home, though. Kinda miss the guerilla marketing leaks from the old days.
leoneazzurro
Golden Member
Yes, PC vendors could do as they want, even supporting only the 12400 or using mobile versions of ADL.
I thought we were talking about the DIY market, though? As Mindfactory is not an OEM.
RnR_au
Diamond Member
AMD themselves told us in October that there will be a Ryzen product with V-Cache for AM4 in early 2022.
At the 8:34 mark.
AtenRa
Lifer
AMD have said they are going to bring Ryzen 6000 in Q1 2022. I find it highly impossibly to bring something else instead of the 3D Cache.
Best CPU in relation to price/performance both in Games and MT workloads. Cheaper vs 5900X, faster in games and within 5% in MT workloads.
DrMrLordX
Lifer
PC vendors source boards from some of the same players that serve the DiY market. If they want to bring B660 boards to market without 12900k on the supported list, the opportunity will be there for them to do so.
Okay, thank you for the correction. That's one of the few places where I've seen anything official or semi-official from AMD on what is coming in Q1 2022. Of course it's an interview, and they could contradict that later but . . . at least someone in an official capacity said, yeah, we're selling Zen3D in 2022.
leoneazzurro
Golden Member
Yes, it is possible but highly unlikely in the DIY market, as historically there is very little market for this kind of solutions because of the reduction of upgrade possibilities (which is one of the big reasons a DIY market exist).
Hans Gruber
Platinum Member
Alder Lake basically made Zen 3D a need rather than a nice to consider option for AMD. I have read many articles saying end of January or early Feb 2022 will be when Zen 3D arrives. I think Zen4 will not be delayed at all because of Alder Lake.
Intel has managed to turn their CPU's from binge drinkers to moderate alcoholics when it comes to power consumption.
Intel has managed to turn their CPU's from binge drinkers to moderate alcoholics when it comes to power consumption.
TRENDING THREADS
-
Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)- Started by DisEnchantment
- Replies: 25K
-
Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads
- Started by Tigerick
- Replies: 25K
-
Discussion Intel current and future Lakes & Rapids thread- Started by TheF34RChannel
- Replies: 24K
-
-
