Info 64MB V-Cache on 5XXX Zen3 Average +15% in Games

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Kedas

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Dec 6, 2018
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Well we know now how they will bridge the long wait to Zen4 on AM5 Q4 2022.
Production start for V-cache is end this year so too early for Zen4 so this is certainly coming to AM4.
+15% Lisa said is "like an entire architectural generation"
 
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jamescox

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That's not true. There is going to be a Milan-X. When it will be released and if it will just be a few customers remains to be seen.
We have already seen some screen shots of X3D settings in a Milan BIOS, it is highly likely that we will get Milan-X. I suspect that the desktop chips will get single cache layer only. It might be that there are Milan-X parts based on single cache layer CCD also. The 4 layer devices are likely to be extremely limited, very high-end, and very, very expensive. Perhaps a high core count version for HPC and a low core count for single thread optimized software. I think Milan might be around for a while after initial Zen 4 launch. It is unclear whether Zen 4 will be a Ryzen or Epyc part first. With an essentially new architecture, they may want to sell some of them as high-end Ryzen parts while the Epyc parts go through extended validation. It takes a while for the platform development. Zen 4 will have all new sockets, so platform validation will take a while.
 

jamescox

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But that is exactly how it works. As AMD is testing, sending chips out for validation and so on, they are specifically tracked as test equipment and can't be used, they need to track and count by batches and only as they submit for finalization for production would they start producing chips that could be used in for sale. So yeah before X day, those 3d cache chips can't and won't be used.


This is where you are right, it's the Threadripper philosophy. They only needed so much stock, much less than people tend to think that they could keep stock with using 95th percentile dies. As long as AMD is still selling the 3d cacheless 5k Ryzen, it doesn't matter what the success rate is.

Also because 3d cache requires it to mate to the cache on the CPU, AMD has to create the cache chips for the specific compute dies. AMD won't offer this on Milan because it means revalidating a whole bunch of chips with Genoa coming so soon. Genoa would be the first implementation (potentially) for server.

The math on this is easy. 3D'd Zen 3 is what we though Zen 3+ was. At time of production Ryzen Zen 3 desktop chips will be the only products that will be using the tech. It's a perfect hold over till Zen 4 hits desktop and allows them to ship Genoa first. To top it off, its potentially why we haven't seen Zen 3 Threadripper yet. Potentially as Genoa launches I see AMD taking that Milan production and using it for 3d cached Zen 3 for Threadripper.

As noted, we have already seen a screen shot of Milan-X X3D bios settings for up to 4 cache layers. I don’t know when Genoa will release, but it will take a lot of time for a completely new platform. It was a while just to get Milan optimized systems and those were based on the same socket as Rome. Genoa might be available early to some customers, but I think Milan and Milan-X will be the top sellers for quite a while, even after Genoa is available. We might only get high end 4 cache layer devices with Milan-X. I think all desktop parts will be a single layer of cache die.

Also, Zen 3 seems to have had the TSVs for stacking from the start. I thought they made a new stepping and claimed it was just for manufacturability. This might have been final changes to enabled die stacking. The initial implementation may not have been functional even though the TSVs were present. Now, every Zen 3 CCD likely has the TSVs to allow 4 layers of stacked cache. I don’t know if they can bun them before attempting the stacking. They would want to maintain the same Z height, so I assume that the 4 layer cache stacks have to be thinned more than the single layer. The 4 layer stack will likely be a lot more risky to make, so it will not be cheap.

There is also still a possibility that there is a Zen 3+ with some minor tweaks. The switch to an 8-core CCX seems like it is complex enough that there is likely some minor tweaks that could be done to increase performance. I wouldn’t rule out a new stepping when Zen 3D actually ships.
 

Joe NYC

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We have already seen some screen shots of X3D settings in a Milan BIOS, it is highly likely that we will get Milan-X. I suspect that the desktop chips will get single cache layer only. It might be that there are Milan-X parts based on single cache layer CCD also. The 4 layer devices are likely to be extremely limited, very high-end, and very, very expensive. Perhaps a high core count version for HPC and a low core count for single thread optimized software.

There is one server part with 8 cores, 1 core per chiplet and 256 MB of L3 between all 8 chiplets.

In theory, 4 layers of L3 could result in 1 chiplet having the same 8 cares and 256 MB of memory.

The problem would, of course, be that the single chiplet can only get a relative bandwiddth out of the IOD die and 8 memory channels, while 8 chiplets can max out the memory bandwidth.

I think Milan might be around for a while after initial Zen 4 launch.

Yup, probably 2+ years selling in parallel. Plenty of time in the market place to make it worthwhile to optimize it with the V-cache

It is unclear whether Zen 4 will be a Ryzen or Epyc part first. With an essentially new architecture, they may want to sell some of them as high-end Ryzen parts while the Epyc parts go through extended validation. It takes a while for the platform development. Zen 4 will have all new sockets, so platform validation will take a while.

Conventional wisdom is that AMD will follow the pattern and release Ryzen first. But there was something in the interview today, on Yahoo Finance, with Lisa Su, When she talked about upgrading products to 5nm process technology, she said "particularly in the data center". It may not necessarily be pertaining to timing, perhaps just emphasis, but just throwing it out there.

AMD CEO: 'Demand for computing is exploding' (yahoo.com)

Before both desktop and server version of Zen 4, we should get an official launch of CDNA2 and perhaps Trento (a Milan derivative) as well.

The only tidbit we have about Trento is that there will be some changes to I/O die and that it will enable coherent memory access between CPU and GPU.

I wonder if there are going to be any additional surprises in that IO die...
 

A///

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Feb 24, 2017
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Well pretty much yeah. Except it was the 1.13GHz model that was recalled, not the 1GHz. Small detail, not trying to nitpick just wanted to clarify in case someone tried to go search for info on it.

AMD did beat Intel to 1GHz by a matter of a week or two maybe, but the Pentium 3 model was a paper launch whereas you could get the Athlon 1 GHz.

Kyle Bennett, there's a name I haven't heard in awhile. He was right up there with Anand. Anandtech was involved in the recalled P3 as well. With so many reputable sources confirming the problem Intel had no choice but to go into damage control mode.

Fair enough. I usually roll my eyes at small detail nitpicking but this particular example warrants it because they're two very separate events. Anand wasn't the only one who pushed for it. They opened the flood gates from what I remember. When more notable sites began reporting it everything became a giant mess for Intel. The funny thing is Intel never learned their lessons. Then or during the period they made side deals with OEMs. Intel's gotten reamed hard this week by people in the biz and even major crediting houses that are ambivalent about their new naming scheme which, to be frank, seems to be used as a vehicle to hide their ongoing and possibly further messes involving products. Forgive me, but I've never become immune to the several decades of Intel BS that Intel has become a master at peddling.
 

A///

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Feb 24, 2017
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There may have been a non-trivial amount of effort on Zen 3d with V-cache. We know that there is a new stepping of Zen 3. We don't know what it entails. It could be from trivial, to gain of some frequency all the way to moving Zen3 (and Zen 3d to 6nm)

Given the likely tightness of 5nm capacity in 2022, I thin Zen 3 will be around for some time in desktop. We may see a full line-up of Zen 3d desktop products.
You know, I had not thought of it like that. To keep Zen 3 and console APUs on 7nm while moving Zen 3+/V-Cache to 6nm would not only alleviate any potential chokes that a new chip would cause on an already tight 7nm line, but it may allow for console APUs to increase once AMD decides to cut down on Zen 3 fabrication. Not entirely sure who uses 6nm now or who would use it, but I would not be shocked if AMD has a running order with TSMC to automatically buy any 5nm wafer space after a certain point once Apple backs off. I only say this because I am 100% certain AMD will try and get as much wafer count as they can to box out NVidia. While I don't believe TSMC plays favorites, they're likely less inclined to help a company out that routinely backstabs them.

Well, I am worried. Alder lake will almost certainly edge regular Zen 3. AMD will need Zen 3D to keep desktop crown.

Going forward to Meteor Lake, Intel is the only company that has on its public roadmap a standalone GPU chiplet / tile. Ever since ATI acquisition, AMD has talked about integration a lot, has done a just rudimentary effort to have integrated graphics of low end quality integrated on some CPUs. But never a game changing solution, that would replace, at least on the mobile side, the external GPU.

And Intel is doing it with Meteor Lake.

We'll see about Alderlake. It would have to outperform Zen 3 while using the same energy expenditure as Zen 3 for it to be a win. I won't touch the varied clocks issue depending on which subset of cores is being engaged. If it outperforms Zen 3 while using 50-150 more watts, that isn't a huge success in my book. Intel running hotter, power hungry and at higher clocks while failing is not a new phenomena in the Intel-AMD game. Meteorlake sounds cool but until it's a physical product that can be bought, it's a lot of claims being made by a company who hasn't had a good track record on delivering in a long time.

Wasn't Zen 4 or Zen 5 coming with a GPU chiplet or on die (IOD) development?
 
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A///

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I mean sure, that'd be okay too I guess, but they really should be aiming for Jan-Apr 2022 (Q2 latest). Unless they just don't care anymore. As good as Zen3d might be, I don't think it obviates the need for them to launch their new platform with a desktop halo product to go with it along the generally-accepted cadence of 15-18 months.
I don't look at Zen 3+/V-Cache as a Zen+ (2000 series) situation. I view it as an XT type of situation. If it were that, we wouldn't be seeing Zen 4 until well into 2023. AM5 boards are going to be manufactured in Q1 and arrive in Q2 '22. It seems incredibly stupid to begin production so early if the product is coming in December. You usually want to get products a month out before the holiday season begins. AMD's Zen 3 launch in early November did not do them any favors. It's hard to comment on the V-Cache products because they're only affecting top SKUs per AMD's words. It's hardly an XT going by my own example. No idea if Threadripper will come with V-Cache or not, but I'd say it's a given. Zen 3 based Threadripper was already going to be a monster and that was known before the V-Cache announcement.

From what I've heard, TSMC really wants everyone on N7 to transition away to N6 due to reasons of cost. It would be eccentric moving forward for AMD to take any N7 wafers from TSMC. I'm guessing they're going to try to move N7+ and N7P customers - such as they are - to N5 and derivatives. But that's just a guess, and I don't think AMD even uses those nodes anyway (which still confuses me, but whatever!).

The way I understand TSMC's process, not having set a foot in any of their fabs, is that all these nodes run independent of others in a node family. That's what I've been told by people who are more closely involved with TSMC. It doesn't make much sense to me either but TSMC would likely prefer products moved to N6 if they'd truly benefit from it. Console refresh APUs/Pro Models would benefit but that's not for another few years because consoles are sold at cost but you don't want to take on more cost eating than necessary if you're Sony or Microsoft.
We will see. I will concede that there is a possibility that failed Genoa CCDs may comprise early Raphael, and that any aggressive push to saturate ODM channels with Genoa will just make it easier for them to launch Raphael earlier than Q4 2022 (which is a commonly rumoured launch quarter).

Seeing as the chiplets are the same from top to bottom, you are very likely 100% correct with that assertion. It does make sense because those failed chiplets would still be inadequate considering they're early run product and as yields improve and production is refined the CPUs generally become better.
I have no clue.
It's fine. There's some hot take rumors coming out and it's not really spoken about.
It's actually 15-18 month now (bleh). Zen1->Zen+ was 13 months, ->Zen2 was 15 months, and ->Zen3 was 18 months. At least on the consumer side. Things were a little different on the server side but that is to be expected, since that is their primary focus at the moment. In any case, Nov 2020 saw the Vermeer launch, so Raphael would be Jan-Apr 2022 assuming AMD is pegging their cadence to Raphael and not Zen3D/Warhol/whateveritis.

Zen 2 had considerable work done, though. Actually it's funny you bring this up. I do believe Zen 3 got delayed due to COVID. On the other hand, VC released a chart a short while back with Zen 5 in 2023. That would point towards a time regression if true, especially if Raphael is launching in 2H 2022. If it's earlier like my guess or in summer 2022, it would point towards a 15-18 month run if it releases in late 2023. But if it launches in late 2022 like Zen 3 did, then Zen 5 launching in 2023 would point at a much shorter dev cycle in line with Zen to Zen+.
If AMD is saying "eh let's just let Zen3d take Raphael's spot and delay Raphael" then all bets are off.
Except it'll only affect Ryzen 9 products the way AMD framed it. Actually, I wouldn't be surprised if the 5950X is the only one that gets the treatment outside the Threadripper lineup. I think it's safe to say 3D cache will be commonly available on Zen 4 and beyond. If AMD could routinely bring in performance bumps like Zen 2 to Zen 3, and then 3D cache to it, they could possibly see performance gains each generation that would keep Intel's engineers sweating. A lot of the former Intel engineers I've spoken to and become friends didn't enjoy life at Intel two decades ago when AMD was steamrolling them at every turn. I can't blame them. Crunch time kills your soul regardless of where you work. The now gone Intel intranet blog post and comments that were leaked showed the morale at the company, and that was before Zen 2 came out. That was a few weeks before Zen 2 launched, in mid June 2019. A lot has changed since then.
 
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jpiniero

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I don't look at Zen 3+/V-Cache as a Zen+ (2000 series) situation. I view it as an XT type of situation. If it were that, we wouldn't be seeing Zen 4 until well into 2023. AM5 boards are going to be manufactured in Q1 and arrive in Q2 '22. It seems incredibly stupid to begin production so early if the product is coming in December.

You forget about Rembrandt. AM5 is going to launch with it.
 

DrMrLordX

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On the other hand, VC released a chart a short while back with Zen 5 in 2023. That would point towards a time regression if true, especially if Raphael is launching in 2H 2022.

That would be very interesting indeed if it happens that way.

I think it's safe to say 3D cache will be commonly available on Zen 4 and beyond.

Isn't it true that TSMC won't have the packaging tech available for N5 to utilize v-cache (Zen4) until late 2022? Like . . . Q4?
 
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Joe NYC

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You know, I had not thought of it like that. To keep Zen 3 and console APUs on 7nm while moving Zen 3+/V-Cache to 6nm would not only alleviate any potential chokes that a new chip would cause on an already tight 7nm line, but it may allow for console APUs to increase once AMD decides to cut down on Zen 3 fabrication. Not entirely sure who uses 6nm now or who would use it, but I would not be shocked if AMD has a running order with TSMC to automatically buy any 5nm wafer space after a certain point once Apple backs off. I only say this because I am 100% certain AMD will try and get as much wafer count as they can to box out NVidia. While I don't believe TSMC plays favorites, they're likely less inclined to help a company out that routinely backstabs them.

N7 and N6 share the same facilities. But TSMC said that due to more extensive use of EUV and fewer steps of N6, the N6 wafers can process at higher rate. Which could mean more capacity from small potential die area savings and also from higher rate of processing.

Since there is a single die that serves all server chips and desktop chips, it seems to me that it could be cost a cost effective move for AMD to move to N6. Even if only for the Zen 3D dies - would be a benefit.

The console move may come later.

With N5 capacity, I don't think AMD has anything ready for production right now, and also, I don't think TSMC will have any unused capacity in H2 2021. The mobile players will buy all the N5 capacity TSMC brings on line. But in H1 2022, AMD should be starting production of Zen 4 and should be grabbing all the N5 capacity AMD can get its hands on.

Wasn't Zen 4 or Zen 5 coming with a GPU chiplet or on die (IOD) development?

There is a slide from March 2020 that showed Zen 4 IO die with GPU on it. My guess is that it will be only very basic iGPU, but it's not based on anything, it's just a guess.

There has never been any standalone GPU chiplet, and the various leaked or reconstructed road maps are not clear about block diagrams of the products.

Intel is clearly showing (in a high level 3d block diagram) a separate GPU chiplet / tile for Meteor Lake, most likely using EMIB to connect to adjacent IO die. It looks quite big, so it may be in the category killer range -killing most of the mobile dGPU category.
 
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Joe NYC

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Isn't it true that TSMC won't have the packaging tech available for N5 to utilize v-cache (Zen4) until late 2022? Like . . . Q4?

True. IIRC, it just showed H2 on the roadmap.

I think there may be a version of Zen 4 that has only the base die, no stacking, so that could have an earlier availability than V-Cache version.
 

Joe NYC

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Except it'll only affect Ryzen 9 products the way AMD framed it. Actually, I wouldn't be surprised if the 5950X is the only one that gets the treatment outside the Threadripper lineup. I think it's safe to say 3D cache will be commonly available on Zen 4 and beyond.

My, completely wild guess would be that there would be 6950x and 6800x, both 2x8 and 1x8 core versions, and no 6 core version (as was demonstrated by Lisa Su).

Because, Zen 3D stacking is based on known good die, so why waste stacking on die that has only 6 good cores, if there are plentiful die with 8 good cores?
 

jpiniero

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My, completely wild guess would be that there would be 6950x and 6800x, both 2x8 and 1x8 core versions, and no 6 core version (as was demonstrated by Lisa Su).

Because, Zen 3D stacking is based on known good die, so why waste stacking on die that has only 6 good cores, if there are plentiful die with 8 good cores?

Just from a sales perspective I think they will only do 12 and 16 core.
 

biostud

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They will probably launch 12 an 16 cores with vcache around Intel releases 12xxx. These chips sell in relatively low volume, but it will be important marketing wise to have fastest desktop CPU, as that will make enthusiasts keep using AMD and keep their brand value high, which will make less tech savvy customers interested in buying the mid and low range Cpu's.
 

Joe NYC

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Just from a sales perspective I think they will only do 12 and 16 core.

I think I am going to disagree here.

AMD specifically emphasized gaming performance. AMD is now fully on board in keeping that crown. The best gaming performance could be obtained from single chiplet 8 core CPU with high L3 cache.

2 reasons:
- higher power to cores in 8 core vs. 16 core config, can lead to higher sustained turbo clocks
- 1 chiplet eliminates coherency traffic and some memory latency hit

The fact that 5950 has a higher boost clock just means someone was not thinking things through fully.

The easiest way for AMD to keep gaming performance crown is to release highest clock 8 core CPU with 1-4 layers of V-Cache.
 

Topweasel

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That's not true. There is going to be a Milan-X. When it will be released and if it will just be a few customers remains to be seen.
Is Milan-X really Milan-X Or is it Threadripper 5k? Because while I am sure AMD was developing a Milan using 3d cache and maybe Milan-X is a Semi custom like the Steamdeck CPU (I want to say Warhol). But any shot we have seen for a Milan-X is also applicable to a Threadripper product.
 

jpiniero

Lifer
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Is Milan-X really Milan-X Or is it Threadripper 5k? Because while I am sure AMD was developing a Milan using 3d cache and maybe Milan-X is a Semi custom like the Steamdeck CPU (I want to say Warhol). But any shot we have seen for a Milan-X is also applicable to a Threadripper product.

It's Epyc. Not entirely clear it will be publicly available either.

They could do a Threadripper w/vcache. But there's been no indication that they are going to do so. The Zen 3 Threadripper is going to be released soonish.
 

Joe NYC

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It's Epyc. Not entirely clear it will be publicly available either.

They could do a Threadripper w/vcache. But there's been no indication that they are going to do so. The Zen 3 Threadripper is going to be released soonish.

There is also a Threadripper Pro, which is not yet being released. That one may have V-Cache.
 

Gideon

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They could do a Threadripper w/vcache. But there's been no indication that they are going to do so. The Zen 3 Threadripper is going to be released soonish.
While it will probably come almost a year after Zen3 Threadripper I really hope they do. V-cache would be very relevant in many real world workloads, for instance code compilation (CI servers, etc).

Judging by current cache scaling it would cut Linux kernel compilation times over 2x. Obviously it won't benefit most task as much, but theb again some BW bound tasks that fit into 1-2GB might even get close to an order of magnitude speedup.

It would cost them very little to develop and they would have buyers even when the max-cache and cores version costs 10K
 

Topweasel

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There is also a Threadripper Pro, which is not yet being released. That one may have V-Cache.
Yeah my point. It makes sense for a couple of reasons. No Zen 3 Threadripper yet. Work already being done on that configuration plus we know shipping Ryzen Zen3d products. It would make sense if AMD was holding off on Zen 3 till Zen 3d so that Threadripper 5k was on the best version of Zen 3. Since the design is shared between HEDT and the servers specially with TRpro being a mirror of the server product, rumors and snapshots don't have to be wrong for it still to be a desktop part. I know someone earlier said Milan will be sold long enough that integrating the cache would be worth it. I disagree. We saw this with Zen+ all the work they put into it (as much or little as you imagine) it was better for a TR/Epyc part than a desktop one. TR got it, EPYC did not because the validation and seed work going into it wouldn't be worth it versus continuing to sell Vanilla Naples. Milan already has tons of cache, some apps can use more cache, but it doesn't really matter because they are already miles ahead of Intel there. Anyone willing to buy Milan3d would be just as willing to buy Milan. Better to just wait out Genoa.
 
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N7 and N6 share the same facilities. But TSMC said that due to more extensive use of EUV and fewer steps of N6, the N6 wafers can process at higher rate. Which could mean more capacity from small potential die area savings and also from higher rate of processing.

Since there is a single die that serves all server chips and desktop chips, it seems to me that it could be cost a cost effective move for AMD to move to N6. Even if only for the Zen 3D dies - would be a benefit.
AMD can't use N6 if they want to do stacking because the TSMC tech is N7 on N7 or N5 on N5