Info 64MB V-Cache on 5XXX Zen3 Average +15% in Games

[Kedas]

Well we know now how they will bridge the long wait to Zen4 on AM5 Q4 2022.
Production start for V-cache is end this year so too early for Zen4 so this is certainly coming to AM4.
+15% Lisa said is "like an entire architectural generation"

 

[Kedas]

They were very clear that N7 -> N6 was a 15% or so performance/power improvement with nothing more than the needed tweaks for the library change

Who is they? The 15%/18% is density improvement (hence more dies per wafer) not performance.

7nm Technology - Taiwan Semiconductor Manufacturing Company Limited

TSMC's 7nm Fin Field-Effect Transistor (FinFET) (N7) process technology sets the industry pace for 7nm process technology development by delivering 256Mb SRAM with double-digit yields in June 2016. In 2019, in N7 process node's second year of volume production, customers taped out more than 110...

www.tsmc.com

 

[Gideon]

Who is they? The 15%/18% is density improvement (hence more dies per wafer) not performance.

7nm Technology - Taiwan Semiconductor Manufacturing Company Limited

TSMC's 7nm Fin Field-Effect Transistor (FinFET) (N7) process technology sets the industry pace for 7nm process technology development by delivering 256Mb SRAM with double-digit yields in June 2016. In 2019, in N7 process node's second year of volume production, customers taped out more than 110...

www.tsmc.com

TSMC Q4: 7nm Dominates Revenue, Preps 5nm Ramp, 6nm By EOY

7-nanometer contributes the lion's share of wafer revenue to TSMC's fourth-quarter driven by growth from smartphones and HPC. The foundry is also preparing the 5-nanometer node for early this year and the 6-nanometer by the end of the year.

fuse.wikichip.org

N6 is said to provide around 15-20% higher density with improved power consumption compared to N7,

1. Less power consumption can instead be used for more all-core clocks at same power.
2. Instead of using the density they can leave it the same, spacing out transistors more as they did going from GF 14nm to 12nm

 

[DrMrLordX]

1. Less power consumption can instead be used for more all-core clocks at same power.

Really depends where on the v/f curve the old design sat. If it was already stretched to its limits on the old node, porting it to a new node which only has superior power consumption @ isoclocks as its characterstic doesn't necessarily mean you can get that many more clocks @ isopower. Usually the foundry will come out and tell you in its marketing materials that you can get +n% performance @ isopower when such a thing is possible.

 

[Kedas]

Let me quote that sentence from that link completely

In fact, TSMC considers N6 to be part of the “N7 family”. N6 is said to provide around 15-20% higher density with improved power consumption compared to N7, albeit no iso-power or speed comparisons where provided.

So we don't know, (and certainly not 15% performance) but we can assume that since TSMC didn't provide any performance improvements they will likely be small or not existing.

 

[Gideon]

Let me quote that sentence from that link completely

So we don't know, (and certainly not 15% performance) but we can assume that since TSMC didn't provide any performance improvements they will likely be small or not existing.

I can absolutely believe there will be no performance gain at the top end, say above 4.6 - 4.7 GHz single-core.

I still refuse to believe that this process will net zero performance gains for all core loads in say, a 5950X successor. That chip is running at ~3.775 GHz using 142W when all 16 cores are active. Any power-draw gains in that frequency range should directly result in clock speed gains, even if it's a lowly 50 - 100 MHz. (even 3950X runs at 3.9 Ghz in similar workloads)

Now AMD could also do this:

On the right is the representation of the 12LP design – each of the features have been reduced in size, putting more dark silicon between themselves (the white boxes show the original size of the feature). In this context, the number of transistors is the same, and the die size is the same. But if anything in the design was thermally limited by the close proximity of two features, there is now more distance between them such that they should interfere with each other less.

While it will not save any power, it will allow higher clocks if some parts of the chip limit performance due to high thermals becuse of proximity.

 

[maddie]

T

I can absolutely believe there will be no performance gain at the top end, say above 4.6 - 4.7 GHz single-core.

I still refuse to believe that this process will net zero performance gains for all core loads in say, a 5950X successor. That chip is running at ~3.775 GHz using 142W when all 16 cores are active. Any power-draw gains in that frequency range should directly result in clock speed gains, even if it's a lowly 50 - 100 MHz. (even 3950X runs at 3.9 Ghz in similar workloads)

Now AMD could also do this:

While it will not save any power, it will allow higher clocks if some parts of the chip limit performance due to high thermals becuse of proximity.

They probably won't, as getting as many chips out the fabs is the goal here. Staying the same size counters that.

 

[LightningZ71]

I did generalize a bit much, but, energy efficiency directly related to thermal dissipation. The main point if buying the 5900/50 is all core performance as the 5800x is able to boost to similar speeds in single threaded scenarios. The mykti-core performance of these chips is held back primarily by thermals and a bit by power delivery. If you can knock down the power draw at a given frequency (on a given instruction throughout), then you reduce the amount of heat it's dissipating at that frequency and load. If there is less heat and power draw, then there is now headroom for higher frequency during all core loads (that is still going to be substantially below single core boost maximums).

So, I expect that Zen3d will be able to best AL (@ equivalent prices) in gaming due to the massive cache. I expect it to be able to best AL in all core scenarios that aren't almost completely limited by main memory bandwidth or entirely dependent on AVX-512. it's going to depend on how aggressively Intel prices their chips. But, it's going to be hard to beat 12 cores+ with 192mb of L3 cache.

 

[Kedas]

There is actually a way that you get a performance boost on 6nm even though the process doesn't provide it directly.

Due to the simplified process due to EUV steps the yields/quality could be better than on 7nm, meaning more better quality dies or with other words the binning curve moves a very little to the higher freq. hence an performance improvement.

But this is only true when they actually have better yield otherwise it will only be density improvements.
Maybe that's why TSMC choose not to mention it since it's dependent on yield difference between 7nm and 6nm and that keeps changing in time. and may also be very design specific.

(TSMC already claimed better yield on 5nm than 7nm, assumed due to EUV)

edit: although they do show N7 and N6 on the same line in their graphs, so not very likely for now https://www.anandtech.com/show/16732/tsmc-manufacturing-update

 

[Topweasel]

The server market moves so slowly though, Rome is still their majority selling platform. Im not sure they would cannibalize sales at all by announcing faster skus. And after all there is no such thing as a free lunch, the extra cache will help many workloads but it will require more power if not exceptional binning, or lowered clocks. Also don't forget it will absolutely add cost over regular milan. Not all customers are going to have that need and I assume most will keep buying skus from the mainstream enterprise lineup.

Its not faster SKU's, well it is if you need it, but its more cache. My point was in comparison to competitors. There is no one purchasing a Milan3d CPU that because of where Milan sits (256MB of cache), wouldn't purchase the Milan, even 2 years from now compared to anything Intel has available now or in the near future. That means they are just making margin on the difference between the two chips, minus the cache cost and R&D. Anything Milan3d is still going to be well into the life cycle of Milan either way. Then they will have to have all new sku's validated including trashing or giving away a bunch of silicon they would have sold anyways.

That isn't to say there is no value. I just think the validation process on top of the late market entry, the canabalization. I dont think it would make sense to go through that process with Genoa coming out so shortly and seemingly launching server first.

If anything I see Milan-X as an experiment in waste analyst before a true server launch and again possibly being part a future Threadripper Zen 3 launch.

 

[jamescox]

Its not faster SKU's, well it is if you need it, but its more cache. My point was in comparison to competitors. There is no one purchasing a Milan3d CPU that because of where Milan sits (256MB of cache), wouldn't purchase the Milan, even 2 years from now compared to anything Intel has available now or in the near future. That means they are just making margin on the difference between the two chips, minus the cache cost and R&D. Anything Milan3d is still going to be well into the life cycle of Milan either way. Then they will have to have all new sku's validated including trashing or giving away a bunch of silicon they would have sold anyways.

That isn't to say there is no value. I just think the validation process on top of the late market entry, the canabalization. I dont think it would make sense to go through that process with Genoa coming out so shortly and seemingly launching server first.

If anything I see Milan-X as an experiment in waste analyst before a true server launch and again possibly being part a future Threadripper Zen 3 launch.

The lead times for servers is often very long. A lot of companies will still be buying Rome even with Milan having been out for a while. Big companies don’t just go out and buy the latest and greatest. There is often evaluation machines, software porting, and validation cycles that take quite a while.

Also, a lot of people don’t want the bleeding edge due to compatibility issues. They want a mature platform. Genoa is going to be a new socket with new memory and everything else. A lot of buyers wouldn’t even consider it until it had been on the market for a while and all of the compatibility issues worked out. Genoa will take a while to gain market share. Milan-x should be a drop in replacement for current Milan chips with no platform switch. Genoa coming soon is not going to be that big of an issue for corporate buyers who might have specified their build months ago and might be buying the same machine for a few years.

 

[Joe NYC]

There is actually a way that you get a performance boost on 6nm even though the process doesn't provide it directly.

Due to the simplified process due to EUV steps the yields/quality could be better than on 7nm, meaning more better quality dies or with other words the binning curve moves a very little to the higher freq. hence an performance improvement.

That is what I was thinking as well. N6 is a higher precision process due to EUV, and it should improve average binning.

The worst binning parts should improve.

 

[Joe NYC]

That isn't to say there is no value. I just think the validation process on top of the late market entry, the canabalization. I dont think it would make sense to go through that process with Genoa coming out so shortly and seemingly launching server first.

If anything I see Milan-X as an experiment in waste analyst before a true server launch and again possibly being part a future Threadripper Zen 3 launch.

If you consider the upcoming pile-up of companies trying to get TSMC N5 capacity in 2022, extending Milan on the process node where capacity is being freed up makes all the sense in the world.

Having a highly competitive N7 (N6) product in 2022 will set AMD apart. So making investments today in validation will bring significant returns on the investment in 2022, independent of success and timing and volumes of Genoa.

 

[wahdangun]

Wait a dang second. I remember this. That was the Pentium 3 incident, wasn't it?



Isn't that what he's referring to? Toms Hardware did get punished, but I remember Kyle Bennett ended up saving the day by offering his own chip to be tested and confirm. I think after that, everything snowballed and Intel couldn't keep denying it.

man i miss Hard[H]OCP

 

[Joe NYC]

That's correct. I just wanted to point out, how unfeasible it is, expecting AMD to be producing those chips right now.

I simply pointed out a single fact that AMD's CEO publicly stated in an official presentation, I had and/or still don't have ANYTHING ELSE that I've supposedly had hidden behind my words. Can you please explain to me what you're talking about and where exactly have I sounded like any sort of this bizarre dream scene of yours?

Or is this just the week where people got infected with some lunacy-inducing disease where they come up with the wildest and most irrelevant accusations they can think of?

Oh I see, so you were just mistaking this forum for some twisted cynical scrabble game platform that I don't know of. Sorry man, I don't swing that way, but you go ahead and have a blast with the others nonetheless!

No it would not, because I'm not pretending to have supernatural powers and know what certain companies are planning behind the scenes. I repeated what was told publicly, pointing out its contradiction to expecting something to happen several months before it's due. When you practically tell me that 'by the end of the year could mean 1st of August as well', I can't help but think that you're being 100% cynical just to mask the silly nature of your first answer to me, which didn't make any sense in the first place.

If AMD released consumer CPUs with V-Cache tomorrow, your comment would still be either cynical or silly, depending on your intentions when you've posted it.

Your posts must include your own written commentary in the CPU forum.

AT Moderator ElFenix

 

[Magic Carpet]

man i miss Hard[H]OCP

Kyle joined Intel as Director of the Enthusiast Engagement in 2019. There has been a bit of him in every Intel product release since 😁

 

[legcramp]

Kyle joined Intel as Director of the Enthusiast Engagement in 2019. There has been a bit of him in every Intel product release since 😁

Thought he left almost immediately due to family matters.

 

[eek2121]

3D chiplet SKUs will be announced at the end of this month (hot chips) FYI. No idea on the actual launch, but I imagine a month or two after.

 

[jpiniero]

3D chiplet SKUs will be announced at the end of this month (hot chips) FYI. No idea on the actual launch, but I imagine a month or two after.

I don't know why you think that, when Lisa said they weren't going into production until the end of the year. It almost has to be a Q1 release.

 

[xilli_fiberbit]

AMD at the hotchips conference will talks about 3D V-Cache technology but it's not the place generaly where AMD makes product announcement and talks about product already released : ZEN3 and RDNA2

 

[eek2121]

AMD at the hotchips conference will talks about 3D V-Cache technology but it's not the place generaly where AMD makes product announcement and talks about product already released : ZEN3 and RDNA2

Sorry if I was misleading. I did not mean to imply AMD would or would not announce those products at Hot Chips (actually, I started to write "Around Hot Chips", but I was on mobile and I felt the need to clarify, but did not want to type more). From what I've heard, the announcement would be "around" that time. My source happens to be a leaker, we'll see if he or she is right, though they've been right in the past and they've allowed me to correctly predict things in the past (Lab 3 GHz RDNA2 with 2.8 GHz actual clocks Anyone? Oh boy did I catch it for that...I was right). We'll see.

I would be shocked if the actual launch wasn't this year (I wasn't given a launch date, but typical AMD launch date is a month or two after announcement...with some exceptions). It MIGHT be CES, but much later then that? Not really. I also expect Zen 4 to launch as late as possible thanks to the chip shortage.

 

[Joe NYC]

Sorry if I was misleading. I did not mean to imply AMD would or would not announce those products at Hot Chips (actually, I started to write "Around Hot Chips", but I was on mobile and I felt the need to clarify, but did not want to type more). From what I've heard, the announcement would be "around" that time. My source happens to be a leaker, we'll see if he or she is right, though they've been right in the past and they've allowed me to correctly predict things in the past (Lab 3 GHz RDNA2 with 2.8 GHz actual clocks Anyone? Oh boy did I catch it for that...I was right). We'll see.

I was accused of being "infected with some lunacy-inducing disease", playing "twisted cynical scrabble game", "pretending to have supernatural powers", "100% cynical just to mask the silly nature of (my answer)"

All for using some analytical skills that pointed to AMD and TSMC have all the incentives in the world to put the highest priority on this product, which would likely result in it being shipped this year.

Not even any non-public leaks.

I would be shocked if the actual launch wasn't this year (I wasn't given a launch date, but typical AMD launch date is a month or two after announcement...with some exceptions). It MIGHT be CES, but much later then that? Not really. I also expect Zen 4 to launch as late as possible thanks to the chip shortage.

AMD putting in the Zen 3D for 2021 on the very latest roadmap slide I posted above IMO points to high degree of confidence AMD has right now in being able to launch it.

Another slides from the latest roadmap show Genoa to be the leading Zen 4 product:


And Desktop Ryzen Zen 4 falling off of the roadmap for now:



Both pointing to the highest priority to get Zen 3D out of the door, and Zen 3D being the Alder Lake competitor for most of 2022.

For Zen 3D to be a successful competitor, it may need to bring out > 1 layer of of V-Cache and to max out a gaming oriented chips.

So, it is probably my turn to get all the grief... But one thing I like more than anything else : getting all the down votes for using my brain and being right..

 

[A///]

I'm more or less curious why they've been drilling chips since the beginning if they were going to implement it this late in Zen 3's life. Not that I'm one to question AMD or their timing, mostly because I don't engage in deep discussion about these matters outside of this site, but why.

Thought he left almost immediately due to family matters.

You thought correctly. His son being sick was one of the reasons for his swift departure.

 

[DisEnchantment]

Another slides from the latest roadmap show Genoa to be the leading Zen 4 product:

The slide says Data Center Roadmap and underneath it says EPYC, so naturally it would be Genoa.
I doubt AMD will be open ever again for client roadmaps

 

[LightningZ71]

I'm more or less curious why they've been drilling chips since the beginning if they were going to implement it this late in Zen 3's life. Not that I'm one to question AMD or their timing, mostly because I don't engage in deep discussion about these matters outside of this site, but why.


You thought correctly. His son being sick was one of the reasons for his swift departure.

They've been doing it from the beginning of Zen3 because they've been using those same features in the buildout of one of their supercomputer contracts.

 

[moinmoin]

I doubt AMD will be open ever again for client roadmaps

No surprise there considering (unlike the server market) in that market surprise announcements like Zen 3D are way more impactful than long term roadmap predictability.

Which is exactly why we now get piecemeal feature announcements, if at all.