64 core EPYC Rome （Zen2）Architecture Overview？

[Abwx]

Density improvement is different for logic and SRAM, and SRAM shrank a lot more than logic. Based on published numbers, a high-density SRAM bitcell should take 0.42x the space on TSMC 7nm of what one took on a GF 14nm process.

AMD stated 2x surely as a whole, SRAM among others compensating for what doesnt shrink as much.

That s for what was included in the chiplet, wich mean Cores + Caches + IF as well as all the power management, it s possible that such parts as the MC and I/O doesnt scale much comparatively, in wich case it was a smart move to keep those circuitries in 14nm.

That being said i wonder if the 20-28mm2 left in the chiplet are reserved to DT SKUs use, this way they could better amortize this chiplet by selling it in a mass market, without Ryzen the server business wasnt sustainable and nothing has changed in this respect.

 

[Yotsugi]

Or outside Vega mobile (can't remember it's code name

VEGA12.

There is a Vega 11. It isn't and never was what you think it was.

It's exactly what I think it was, and it's dead.
Canned.

 

[Topweasel]

Never existed or existed as Vega 11 the Raven Ridge GPU part.

Here is an article with an actual AMD roadmap. Same time period.

https://wccftech.com/amd-vega-navi-gpu-hbm2/

What is missing Vega11? The article includes Vega 11 but you can tell that it's an attempt compare Vega to Polaris. But it was always a replacement for the Fury. AMD was never going to make a low cost version. The HBM2 used should tell you that.

Navi is the Polaris replacement. Always was.

That terrible fake slide you showed is nothing more than taking articles like this one and manufacturing a slide to match.

No canned Vega 11. It was a never was and not a what might have been.

 

[Yotsugi]

The HBM2 used should tell you that.

I don't remember AMD dGPU IP ever being tied to any kind of memory.

No canned Vega 11. It was a never was and not a what might have been

So why does smaller VEGA12 exist?
Oops.

 

[Topweasel]

I don't remember AMD dGPU IP ever being tied to any kind of memory.

So why does smaller VEGA12 exist?
Oops.

So a couple things. Obviously you don't know know the market as well as you proclaim. Fury and Vega are missing controllers for memory other than HBM. No GDDR support there. Technically it could piggy back off of HBCC to use other memory. I think that's technically how the APU's work. This is why Vega mobile and even Vega in the Intel CPU use HBM.

Looked more and more into Vega 12. It is not Vega mobile. Every reference to Vega 12 out there is rumors from the middle of 2018 as a potential product along with Vega 20. Certainly not the code name for a product released a year ago. Most places reference it as a newly added device in drivers in linux.

Vega mobile to be Vega mobile. I am pretty sure the only reason even that exists is because of the semi custom work with Intel. If Intel didn't want a chip that supported discrete memory on their CPU than Vega Mobile probably doesn't exist. Including GDDR probably wouldn't have worked in that package so Polaris was out.

 

[Yotsugi]

Fury and Vega are missing controllers for memory other than HBM. No GDDR support there.

Are you genuinely-genuinely clueless about the way AMD dGPU IP works?

This is why Vega mobile and even Vega in the Intel CPU use HBM.

They use it to save power and package space.

Looked more and more into Vega 12. It is not Vega mobile.

It is, down to SP count and yadda-yadda-yadda.

I am pretty sure the only reason even that exists is because of the semi custom work with Intel.

KBL-G and Vega M are two different-different products.

 

[exquisitechar]

[ Insert more cores meme ] pic.twitter.com/QKpbyBtgQo​

— VideoCardz.com (@VideoCardz) November 22, 2018​

​

As the replies say, 16 x 16MB L3 implies a 4 core CCX?​

 

[Yotsugi]

[ Insert more cores meme ] pic.twitter.com/QKpbyBtgQo​

— VideoCardz.com (@VideoCardz) November 22, 2018​

​

As the replies say, 16 x 16MB L3 implies a 4 core CCX?​

Pretty much.

 

[Topweasel]

Are you genuinely-genuinely clueless about the way AMD dGPU IP works?

They use it to save power and package space.

It is, down to SP count and yadda-yadda-yadda.

KBL-G and Vega M are two different-different products.

Since you want to brash. We will ignore the last three because that can back and forth. Please show me the support for Gddr in Vega.

 

[Yotsugi]

Please show me the support for Gddr in Vega.

That Subor-Z semi-custom SoC.
KBL-G is Polaris with HBM.
Flexibility is fun.

 

[Topweasel]

That Subor-Z semi-custom SoC.
And KBL-G is Polaris with HBM.
Flexibility is fun.

KBL-G is not Polaris. The Soc is a Soc and much like AMD's APU or hell even the consoles, uses the CPU's memory connection to feed the GPU. Neither proves that Vega as a dGPU supports GDDR in anyway. Something understood to be the exact opposite. Vega doesn't support GDDR.

 

[Yotsugi]

KBL-G is not Polaris.

It is, GFX804, part of GFX8 family (Tonga/Polaris).

The Soc is a Soc and much like AMD's APU or hell even the consoles, uses the CPU's memory connection to feed the GPU.

It's still bunch of DDR interfaces.
Y'know, the same interfaces Polaris uses.

Vega doesn't support GDDR.

Please stop, this is borderline self-humilation.

 

[Topweasel]

It is, GFX804, part of GFX8 family (Tonga/Polaris).

At best worst it's a side development of Polaris while Vega was being developed, for Intel, both are GCN anyways. But it's closer to Vega than it is polaris.

It's still bunch of DDR interfaces.
Y'know, the same interfaces Polaris uses.

Not if the DDR interface is in the CPU and it's getting fed from IF.

Please stop, this is borderline self-humilation.

Vega Doesn't support GDDR. Still haven't shown me otherwise.

 

[Yotsugi]

At best worst it's a side development of Polaris while Vega was being developed

It's quite literally a semi-custom Polaris.

both are GCN anyways

Well, that's an ISA.

But it's closer to Vega than it is polaris.

And PS4 PRO APU is even closer.
Still Polaris.

Not if the DDR interface is in the CPU and it's getting fed from IF.

Please stop.

Vega Doesn't support GDDR. Still haven't shown me otherwise.

I beg you.
Stop.

 

[CatMerc]

There is nothing tying Polaris or Vega to any specific memory controller. AMD designs GPU's in modular blocks, and the memory controller is just another block that can be mixed and matched. For example Fiji was basically just Tonga scaled up with HBM. Same architecture.

As for Vega 11, it existed. Per Raja's words, the numeric just indicates when the development started. For Vega 12 to exist there had to be a Vega 11. There were also Linux patches and even MacOS updates with references to Vega 11, and it's not Vega 11 the Raven ridge GPU because in the same place you found the first references to Polaris 20 XL.

As for the leaked roadmap, it's real. The absolute majority of the information on that roadmap wasn't known when it was first released. I know because I kept track of Vega's timeline of information very closely. Vega 20 being a 7nm FP64 GPU with 4 HBM2 stacks and xGMI came from that slide a literal year before anything else came out about it.

 

[Zapetu]

[ Insert more cores meme ] pic.twitter.com/QKpbyBtgQo​

— VideoCardz.com (@VideoCardz) November 22, 2018​

​

As the replies say, 16 x 16MB L3 implies a 4 core CCX?​

Sure seems to suggest that. But I'm no expert in these kinds of leaks so I let others decide how legit this is down to details. There are still many open questions, though.

More links (SiSoftware Sandra 28.20) in the spoiler tag if you haven't found them already. 1.4Ghz base / 2.0Ghz turbo.

Spoiler: AMD Eng sample: 2S1404E2VJUG5_20/14_N

SiSoftware Official Live Ranker
Details for Result ID 2x AMD Eng Sample: 2S1404E2VJUG5_20/14_N (64C 1.4GHz, 800MHz IMC, 64x 512kB L2, 16x 16MB L3):

http://ranker.sisoftware.net/show_r...d4ecdfebdceedcfa88b585a3c6a39eae88fbc6fe&l=en

How To Decode AMD Code Names V4.1:

http://www.moepc.net/content/uploadfile/201811/8d7b1542898939.png

 

[Veradun]

Picasso should have been called <Something> Ridge to signify that it would be just a 12LP refresh. I hope that AMD will release this one soon, so all the speculation will end.

Raven Ridge and Picasso are internal names. Why do you care so much?

 

[DisEnchantment]

Sure seems to suggest that. But I'm no expert in these kinds of leaks so I let others decide how legit this is down to details. There are still many open questions, though.

More links (SiSoftware Sandra 28.20) in the spoiler tag if you haven't found them already. 1.4Ghz base / 2.0Ghz turbo.

Spoiler: AMD Eng sample: 2S1404E2VJUG5_20/14_N

SiSoftware Official Live Ranker
Details for Result ID 2x AMD Eng Sample: 2S1404E2VJUG5_20/14_N (64C 1.4GHz, 800MHz IMC, 64x 512kB L2, 16x 16MB L3):

http://ranker.sisoftware.net/show_r...d4ecdfebdceedcfa88b585a3c6a39eae88fbc6fe&l=en

How To Decode AMD Code Names V4.1:

http://www.moepc.net/content/uploadfile/201811/8d7b1542898939.png

Compare this to one of the early AMD's Naples ES which also came out at 1.4GHz base
2S1451A4VIHE4_29/14_N --> A Stepping Naples came out almost 10 months before Naples release
2S1905A4VIHF4 --> B Stepping Naples, almost final
But looks like the silicon was reworked a lot. 4 revision of the Second ES.

 

[Zapetu]

Raven Ridge and Picasso are internal names. Why do you care so much?

I really don't. Maybe for a while I did because I mixed some things up but not anymore. I'm mostly interested in speculating about all the technical stuff and drawing illustrations of them. Bristol Ridge and Stoney Ridge also exists.

Maybe I should care a little more if Ryzen 3000 APUs will be Zen+ and Ryzen 3000's (without iGPU) will be Zen2 but even that doesn't bother me too much, different market segments. Still would be nice if AMD could benefit from 7 nm also in mobile segment as soon as possible.

I'm mostly interested in that SiSoftware Sandra leak and it's relevance to 8C CCX vs. 2x 4C CCX debate. If 16 x 16MB is true then it's pretty obvious what it would indicate. I really don't know much about benchmarking and especially Sandra and was hoping that others would have more to say about it and how legit that Result ID is (related to 4C CCX).

 

[thigobr]

I wouldn't read too much into the Sandra leak. As with any HW information software it just reads hardware identification codes and translates that into user friendly strings based on an internal database. So unless SiSoftware engineers have new information about Zen2 architecture they are just re-using what's there for first Zen until more is know.

 

[Yotsugi]

I wouldn't read too much into the Sandra leak. As with any HW information software it just reads hardware identification codes and translates that into user friendly strings based on an internal database. So unless SiSoftware engineers have new information about Zen2 architecture they are just re-using what's there for first Zen until more is know.

We know the (maybe) current Rome clocks now, though.

 

[positivedoppler]

Maybe Keller wasn't the hero most people thought he was.
https://www.bizjournals.com/sanjose...papermaster-turned-companys-failure-into.html

According to the article, Mark Papermaster had to "redesign" the Zen and postpone it for 2 years since it was fundamentally flawed.

 

[Vattila]

According to the article, Mark Papermaster had to "redesign" the Zen and postpone it for 2 years since it was fundamentally flawed.

Nah. That's highly likely to be just journalistic sloppy reporting. What is probably meant is that Mark Papermaster decided to initiate a revamp of the CPU architecture roadmap (then based on the Bulldozer architecture). Part of that was bringing Jim Keller aboard. Papermaster started at AMD in October 2011. Lisa Su came aboard in January 2012. Keller didn't arrive until August 2012. Former CEO Rory Read and the AMD board (in particular Nicholas Donofrio) were instrumental in recruiting Papermaster and Su. Papermaster recruited Keller and Raja Koduri.

http://fortune.com/2017/06/28/amd-ai-chips-comeback/

This effort on a revamped CPU architecture led to K12 (Keller's high-performance custom ARM core, which was shelved) and Zen (the x86 version, named "Zen" by the chief architect, Mike Clark).

 

[Topweasel]

Nah. That's highly likely to be just journalistic sloppy reporting. What is probably meant is that Mark Papermaster decided to initiate a revamp of the CPU architecture roadmap (then based on the Bulldozer architecture). Part of that was bringing Jim Keller aboard. Papermaster started at AMD in October 2011. Lisa Su came aboard in January 2012. Keller didn't arrive until August 2012. Former CEO Rory Read and the AMD board (in particular Nicholas Donofrio) was instrumental in recruiting Papermaster and Su. Papermaster recruited Keller and Raja Koduri.

http://fortune.com/2017/06/28/amd-ai-chips-comeback/

This effort on a revamped CPU architecture led to K12 (Keller's high-performance custom ARM core, which was shelved) and Zen (the x86 version, named "Zen" by the chief architect, Mike Clark).

Yeah there isn't timeline that makes shelving Zen for 2 years possible. I mean even if AMD gave up on Bulldozer a year before BD's launch. They still barely had time to develop it and be ready to launch towards the end of 16 early 17. You figure it wasn't until Su came on on before they decided to nearly end all BD development. It was a bit after Keller came on before they ended all non-zen development (finishing of BD for good and killing Keller's K12). So you figure heavy Zen development didn't start till early 2013. 4 Year development cycle doesn't leave room for 2 years of sitting on the shelf.

What is probably important in pointing out though is that Keller while a great engineer in his own right. Was never the Savoir of AMD. We remember him as a big shot because of DEC and K8. But he came in to play around with arm in working on the K12, was instrumental in reorganizing how AMD did things on the development side, and worked with Papermaster on Zen till his contract was up. But that's the thing. He wasn't working on Zen early and left as soon as he could when the project he wanted was shelved. Zen wasn't his baby and it wasn't his work that put AMD where it is now. He helped and I don't want to take that away from him. But what Keller often gets credit for should go to Papermaster, Clark and others, most of which are still there.

 

[moinmoin]

Keller's influence on Zen was indirect by having supervised the team responsible both for K12 and Zen. He directed the team to combine the positive parts of both Bulldozer and Jaguar design for Zen. On the development side he improved time to market by making self monitoring (SCF) and verification a central part of the chip designs and letting the team better leverage the existing modularized IPs on CPU side as well. A big part of the development optimization started as ARM infrastructure for K12 they continued to use for Zen.

See the talk from 2014: